JPH0728161B2 - Microwave semiconductor switch - Google Patents

Description

TECHNICAL FIELD The present invention relates to a microwave semiconductor switch that switches a propagation path of incident radio waves.

[Prior Art] FIG. 6 is a diagram showing an example of the structure of a conventional microwave semiconductor switch disclosed in, for example, Japanese Patent Application No. 60-238138.

(1) is a semiconductor substrate, (2) is this semiconductor substrate (1) is a ground conductor provided on the back surface, (3) is the first input / output line,
(4) is a second input / output line, and (5) is a third input / output line having a microstrip line structure.

(6) is the first field effect transistor (hereinafter referred to as the first FET
(7) is the drain electrode of the first FET (6), (8) is the source electrode of the first FET (6), and (9) is the gate electrode of the first FET (6). is there. First FET (6)
The drain electrode (7) of the first input / output line (3) and the second
Connected to the connection point (10) of the input / output line (4) of
The source electrode (8) of the FET (6) is connected to the third input / output line (5).

On the other hand, (11) is the second field effect transistor (hereinafter referred to as the second field effect transistor).
(12) is the drain electrode of the second FET (11), (13) is the source electrode of the second FET (11), and (1
4) is the gate electrode of the second FET (11).

The drain electrode (12) of the second FET (11) is connected to the connection point (1
0) is connected to the second input / output line (4) of approximately 1/4 wavelength, and the source electrode (13) of the second FET (11) is grounded to the ground conductor (2). The configuration of FIG. 6 shows an example of grounding via the via hole (15).

Further, the gate electrode (9) of the first FET (6) and the gate electrode (14) of the second FET (11) are each composed of a bias circuit (16) composed of a microstrip line.
From the first bias terminal (17) and the second bias terminal (18) via the bias circuit (16) is a high impedance bias line (19) having a length of 1/4 wavelength, also 1/4 wavelength Low impedance line for bias (20) and high impedance line for bias (1
9) and the low impedance line (20) for bias, the first bias terminal (17), the second bias terminal (1
8) Bias terminal connecting line (21) connecting each. Moreover, in order to set the drain electrode (7) of the first FET (6) and the drain electrode (12) of the second FET (11) to the ground potential in terms of direct current, the first electrode having a length of 1/4 wavelength is used. One end of the grounding high impedance line (22) is connected to the second input / output line (4), and the other end is connected to the via hole (15). Similarly, the source electrode (8) of the first FET (6)
In order to set DC to the ground potential, one end of the second grounding high impedance line (23) having a length of 1/4 wavelength is connected to the third input / output line (5), and the other end is connected. Is connected to the via hole (15). In addition, (24), (2
Reference numerals 5) and (26) denote the first, second, and third input / output terminals, respectively.

Next, the operation will be described.

FIG. 7 is an equivalent circuit diagram for explaining the operation of the conventional microwave semiconductor switch shown in FIG. In the description of the operation using FIG. 7, first, when a microwave of a low power level is incident from the first input / output terminal (24), then a microwave of a high power level of about several w is incident. The operation will be described separately for each case.

First, consider a switch state in which a microwave of a low power level is incident from the first input / output terminal (24) and propagates to the second input / output terminal (25) with low loss. This is called a reception state for convenience.

In this state, the first and second bias terminals (17)
A negative bias voltage V _BIAS smaller than the pinch-off voltage V _{P of the} FET is applied to (18), and the first and second FETs (6), (1
1) exhibits high impedance. Therefore, the connection point (1
The impedance seen from the side of (0) to the side of the third input / output terminal (26) becomes high, and the microwaves incident from the first input / output terminal (24) enter the second input from the first input / output line (3). Propagate to the output line (4). Further, the second input / output line (4)
Since the second FET (11) connected in parallel with H2 also exhibits high impedance, it has little influence on the propagating microwave.

In addition, since the distance between the first FET (6) and the second FET (11) is set to about 1/4 wavelength, minute reflections cancel each other out, and at the design center frequency, low reflection and low loss occur. It becomes the performance.

Next, consider a case where a microwave of a high power level is incident from the first input / output terminal (24). In this case, the microwave is propagated to the third input / output terminal (26) with low loss, and the microwave is cut off to the second input / output terminal (25) side.

This state is referred to as a transmission state for convenience.

In this state, the first and second bias terminals (17)
A gate bias voltage of 0V equal to the ground potential is applied to (18), and the first and second FETs (6) and (11) exhibit low impedance. Here, the first input / output line (3) and the second
Connection point (10) of the input / output line (4) and the second FET (11)
Since the interval of is set to about 1/4 wavelength, the connection point (10)
The impedance seen from the side of the second input / output terminal (25) is a high impedance close to an open state. On the other hand, the first FE
Since T (6) has a low impedance, the impedance seen from the connection point (10) to the side of the third input / output terminal (26) is the characteristic impedance of the third input / output line (5) (this is equal to the load impedance). ). Therefore, the microwave of high power level incident from the first input / output terminal (24) passes through the first input / output line (3) and the first FET (6), and the third input / output line (5 ) And appears at the third input / output terminal (26). Consider a case where a microwave having a peak power of P watts is incident in this state. At this time, the peak RF current I flowing through the first and second FETs (6) (11)
Are equal and are given by the following equation (1).

Where Z ₀ is the power source impedance and Rds is the first and second
It is the resistance between the drain and source of the FETs (6) and (11).

For example, assuming that the input peak power is 5 W, Z ₀ = 50 Ω, and Rds = 2.5 Ω, the peak RF current I is about 0.43 A from equation (1), and the drain current of the first and second FETs (6) and (11) The peak RF voltage applied between the source electrodes is about 1.1V. At this time, the gate
The peak RF voltage applied between the drain and gate-source electrodes is 0.55V. This is close to the built-in voltage at which the forward rectified current starts to flow in the gate, and when Rds becomes large, a large forward current may flow in the gate and damage the FET.

This phenomenon will be described with reference to FIGS. 8 and 9.

FIG. 8 is a diagram showing a cross-sectional structure of the FET used for the switch.

In the figure, (27) is a source electrode, (28) is a gate electrode, and (2)
9) is a drain electrode, (30) is an active layer, (31) is a buffer layer, (32) is a depletion layer, and (33) is an inductor, which has a high impedance in terms of RF by grounding the electrode. Have a role. Now the microwave enters and the source electrode (27)
It is assumed that the RF current Ids indicated by the arrow in the figure flows between the drain electrode (29) and the drain electrode (29).

At this time, the relationship between the drain-source voltage Vds and Ids shows a substantially linear relationship up to Vds of about ± 1.0 V as shown in Fig. 9, and above that, Ids saturates and Rds increases. To do. In addition, the gate rectification current (I
g) does not flow, but when this voltage is exceeded, a large rectified current suddenly flows. This is because the gate electrode (28) is located between the drain electrode (29) and the source electrode (27), so Vds between the gate electrode (28) and the drain electrode (29) and the source electrode (27) is 1/2 of the voltage difference occurs, which causes the gate electrodes Igd, I between the gate electrode (28) and the drain electrode (29) or between the gate electrode (28) and the source electrode (27).
This is because gs flows.

[Problems to be Solved by the Invention] Since the conventional microwave semiconductor switch is configured as described above, the first FE cannot be used when it is used at a low frequency.
Since the second input / output line between T and the second FET becomes long, the switch becomes large in size, and the size of the device using this switch becomes large, or the cost increases due to the decrease in the number of products manufactured per unit wafer. There was such a problem.

The present invention has been made to solve the above problems, and an object thereof is to obtain a compact microwave semiconductor switch.

[Means for Solving the Problems] A microwave semiconductor switch according to the present invention includes a first input / output terminal, a second input / output terminal, a third input / output terminal, and a first field effect transistor. A second field effect transistor whose source electrode is grounded, a first input / output line provided between the first input / output terminal and the drain electrode of the first field effect transistor, and the second input / output line. A second input / output line provided between the output terminal and the drain electrode of the first field effect transistor and connected to the drain electrode of the second field effect transistor, the third input / output terminal, and the first input / output line. A third input / output line provided between the source electrodes of the field effect transistors, and a first inductor inserted in the middle of the third input / output line and connected in series to the third input / output line. , The second electric field A second inductor connected between the drain electrode and the source electrode of the effect transistor; a first capacitor having one end connected between the third input / output terminal and the first inductor and the other end grounded; A second input / output line inserted between the drain electrode of the first field-effect transistor and the drain electrode of the second field-effect transistor and connected in series to the second input / output line. A capacitor and a third field-effect transistor that is inserted in the middle of the second input / output line between the drain electrode of the second field effect transistor and the second input / output terminal and is connected in series to the second input / output line. A capacitor; a gate electrode of the first field effect transistor; and a second electrode of the second field effect transistor.
Of the first field effect transistor and the second field effect transistor are connected to the gate electrode of the field effect transistor, and the first field effect transistor and the second field effect transistor are turned on. Bias means for switching between a state and an off state are provided.

[Operation] In the microwave semiconductor switch according to the present invention, a radio wave transmission line having a high-pass characteristic having a required frequency as a pass band is formed between the first and second input / output terminals in the receiving state. In the transmission state, a radio wave transmission line having a low-pass characteristic having a required frequency as a pass band is formed between the first and third input / output terminals, and is configured by using a lumped element. Therefore, it is not necessary to set the interval between the first and second FETs to 1/4 wavelength, and it is possible to achieve miniaturization when the required frequency is low.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of an embodiment of the present invention.

The first FET (6) and the second FET (11) are gate electrodes (9) that are bent and arranged to widen the gate width.
I have (14).

The drain electrode (7) of the first FET (6) is connected to the connection point (10) of the first input / output line (3) and the second input / output line (4). A first inductor (34) is inserted and connected in series in the middle of the third input / output line (5) to which the source electrode (8) of the first FET (6) is connected.
Moreover, one end is connected to the ground conductor (2) through the via hole (15).
The other end of the first capacitor (35) connected to is connected to the third input / output terminal (2) from the insertion position of the first inductor (34).
It is connected on the 6) side to the third input / output line (5). Further, the drain electrode (12) of the second FET (11) is connected to the second input / output line (4) connecting the connection point (10) and the second input / output terminal (25), Second FET (1
The source electrode (13) of 1) is connected to the ground conductor (2) through the via hole (15). The second FET (11) above
The drain electrode (12) of the second FET (11) and the second F
The second inductor (36) is connected between the source electrode (13) of the ET (11). Further, the second capacitor (37) and the third capacitor (38) are provided on both sides of the connection point of the drain electrode (12) of the second FET (11) of the second input / output line (4). Inserted and connected in series.

In addition, here, the first FET (6) and the second FET (1
As an example of a bias means for applying a bias to 1), there is shown an example of a bias circuit in which a resistor and a capacitor are connected in series and parallel, and the gate electrode (9) of the first FET (6) and the second A bias is applied to the gate electrode (14) of the FET (11). The gate electrode (9) of the first FET (6) and the gate electrode (14) of the second FET (11) have one end of the first bias resistor (39) and one end of the second bias resistor (40), respectively. Are connected. The other ends of the first bias resistor (39) and the second bias resistor (40) are connected to the other end of the bias circuit capacitor (41) whose one end is connected to the via hole (15) and is grounded. Is
Further, the other end of the bias circuit capacitor (41) and the common bias terminal (42) are connected by a bias line (43). The common bias terminal (42) is connected to an externally provided FET driving bias applying circuit (not shown), and the gate electrode (9) of the first FET (6) and the second FET (11) are connected. ) Is applied to the gate electrode (14).

Next, the operation and operation of the present invention will be described.

FIG. 2 is an equivalent circuit diagram for explaining the operation of the microwave semiconductor switch according to the present invention having the configuration shown in FIG. In the transmission state, the common bias terminal (42) is set to the ground potential (0V), and in the reception state, the pinch-off voltage is applied to the common bias terminal (42). Below, these two
The operation in each of the two states will be described.

FIG. 3A shows an equivalent circuit in the transmission state. First FE
T (6) and the drain-source of the second FET (11) are represented by resistors R ₁ and R ₂ having small values. The sizes of the resistors R ₁ and R ₂ are respectively set to the first inductor (34) and the second inductor (3
If it is set to a value that is negligible compared to the magnitude of the impedance presented in 6), it can be considered as R ₁ , R ₂ ~ 0,
The equivalent circuit of FIG. 3 (a) is represented by the equivalent circuit of FIG. 3 (b). Here, by appropriately selecting the inductance value of the first inductor (34) and the capacitance values of the first capacitor (35) and the second capacitor (37), a low-pass type having a required frequency in a pass band. A filter can be realized. In this case, the radio wave propagates between the first and third input / output terminals (24) and (26) with little loss. On the other hand, the first
The second input / output terminal (24) (25) is cut off by the R ₂ because the second input / output terminal (25) is grounded on the way.

Next, FIG. 4 (a) shows an equivalent circuit in the receiving state.
Capacitors C ₁ and C ₂ are provided between the drain and source of the first and second FETs (6) and (11). Since the impedance of the capacitor C ₁ is set sufficiently high at the required frequency, it can be considered that the first and third input / output terminals (24) and (26) are cut off. On the other hand, by selecting the second inductor (36) so that the impedance exhibited by the second inductor (36) becomes lower than the impedance exhibited by the capacitor C _{2 at the} required frequency, the second inductor (36 ) And C ₂ in parallel can be equivalently represented as inductor Le. Therefore, the equivalent circuit of FIG. 4 (a) is represented by the equivalent circuit of FIG. 4 (b). Here, by appropriately selecting the capacitance values of the second and third capacitors (37) and (38) and the inductance value of the second inductor (36), a high-pass filter having a required frequency in the pass band can be obtained. realizable. In this case, the radio wave propagates between the first and second input / output terminals (24) and (25) with a small loss. The capacitance value of the second capacitor (37) is determined in consideration of the conditions in the transmission state.

In this way, by switching the bias voltage applied to the gate electrodes (9) and (14) of the first and second FETs (6) and (11), the radio wave propagation path is changed to the first and second input / output. Between the terminals (24) and (25) and the first and third input / output terminals (24) (2
6) You can switch between and.

In the above embodiment, the case where the impedance of the capacitor C ₁ is sufficiently high was described. However, when the impedance is low and the leakage of radio waves cannot be ignored, the third inductor (44) is connected in parallel as shown in FIG. May be loaded. By making the third inductor (44) and the capacitor C ₁ resonate in parallel at a required frequency, the isolation between the first and third input / output terminals (24) and (26) can be enhanced.

[Effects of the Invention] As described above, according to the present invention, a capacitor and an inductor are connected in parallel and in series to the third input / output line, and an inductor is provided between the drain electrode and the source electrode of the second FET. Since the two capacitors are connected in series and are connected in series to the second input / output line at positions such that the second FET is sandwiched between them, the microwave semiconductor switch can be downsized and the power handling performance can be improved. It is possible to reduce the cost of the microwave semiconductor switch with high cost.

[Brief description of drawings]

1 is a configuration diagram showing an embodiment of a microwave semiconductor switch of the present invention, FIG. 2 is an equivalent circuit diagram for explaining the operation of the microwave semiconductor switch of the present invention, and FIG.
FIG. 4 is an equivalent circuit diagram of a transmitting state, FIG. 4 is an equivalent circuit diagram of a receiving state, FIG. 5 is a configuration diagram showing another embodiment of the microwave semiconductor switch of the present invention, and FIG. 6 is a conventional microwave semiconductor. FIG. 7 is a configuration diagram showing an example of a switch structure, FIG. 7 is an equivalent circuit diagram for explaining the operation of a conventional microwave semiconductor switch, and FIG. 8 is a configuration diagram showing a cross-sectional structure of a FET used in the switch, FIG. FIG. 4 is a characteristic diagram showing a relationship between a drain-source voltage Vds, a current Ids, and gate currents Igd and Igs. In the figure, (1) is a semiconductor substrate, (2) is a ground conductor,
(3) is the first input / output line, (4) is the second input / output line, (5) is the third input / output line, and (6) is the first FET.
(7) is the drain electrode of the first FET (6), (8) is the source electrode of the first FET (6), and (9) is the first FET (6).
Gate electrode, (10) is a connection point, (11) is a second FET,
(12) is the drain electrode of the second FET (11), (13) is the source electrode of the second FET (11), and (14) is the second FET (11).
Gate electrode, (15) via hole, (16) bias circuit, (17) first bias terminal, (18) second bias terminal, (19) bias high impedance line, (20) ) Is a low impedance line for bias, (21)
Is a bias terminal connection line, (22) is a first grounding high impedance line, (23) is a second grounding high impedance line, (24) is a first input / output terminal, and (25) is a second grounding high impedance line. Input / output terminal, (26) third input / output terminal, (27) source electrode, (28) gate electrode, (29) drain electrode,
(30) is an active layer, (31) is a buffer layer, (32) is a depletion layer, (33) is an inductor, (34) is a first inductor,
(35) is the first capacitor, (36) is the second inductor, (37) is the second capacitor, (38) is the third capacitor, (39) is the first bias resistor, and (40) is A second bias resistor, (41) a bias circuit capacitor, (4
2) is the common bias terminal, (43) is the bias line, (4
4) is the third inductor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first input / output terminal, a second input / output terminal, a third input / output terminal, a first field effect transistor, and a second field effect transistor whose source electrode is grounded. A first input / output line provided between the first input / output terminal and the drain electrode of the first field effect transistor, and between the second input / output terminal and the drain electrode of the first field effect transistor. A second input / output line that is provided and connected to the drain electrode of the second field effect transistor; and a third input / output line that is provided between the third input / output terminal and the source electrode of the first field effect transistor. I / O line,
A first inductor inserted in the middle of the third input / output line and connected in series to the third input / output line, and connected between the drain electrode and the source electrode of the second field effect transistor. A second inductor; a first capacitor having one end connected between the third input / output terminal and the first inductor and the other end grounded; a drain electrode of the first field effect transistor; A second capacitor inserted in the middle of the second input / output line between the drain electrodes of the field effect transistor and connected in series to the second input / output line; and a drain electrode of the second field effect transistor. A third capacitor inserted in the middle of the second input / output line between the second input / output terminal and the second input / output line and connected in series to the second input / output line, and the gate electrode of the first field effect transistor. And above The first field effect transistor and the second field effect transistor are connected to the gate electrode of the second field effect transistor, and apply a predetermined bias to the first field effect transistor and the second field effect transistor. A microwave semiconductor switch, comprising: biasing means for switching the ON state and the OFF state.