JPH0727635Y2 - High frequency hybrid integrated circuit - Google Patents
High frequency hybrid integrated circuitInfo
- Publication number
- JPH0727635Y2 JPH0727635Y2 JP1989040367U JP4036789U JPH0727635Y2 JP H0727635 Y2 JPH0727635 Y2 JP H0727635Y2 JP 1989040367 U JP1989040367 U JP 1989040367U JP 4036789 U JP4036789 U JP 4036789U JP H0727635 Y2 JPH0727635 Y2 JP H0727635Y2
- Authority
- JP
- Japan
- Prior art keywords
- copper block
- heat dissipation
- integrated circuit
- hybrid integrated
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052802 copper Inorganic materials 0.000 claims description 29
- 239000010949 copper Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 230000017525 heat dissipation Effects 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 230000005855 radiation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 この考案は、高周波帯域で動作する高周波混成集積回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high frequency hybrid integrated circuit which operates in a high frequency band.
第3図は従来の高周波混成集積回路の銅プレート上に半
導体を組み立てた部分の斜視図であり、第4図は、前記
第3図中のB−B線の断面図である。FIG. 3 is a perspective view of a portion where a semiconductor is assembled on a copper plate of a conventional high frequency hybrid integrated circuit, and FIG. 4 is a sectional view taken along the line BB in FIG.
第3図,第4図において、1は上面に各回路、下面に全
面接地電極を持ち、高周波混成集積回路を構成する基
板、2は前記基板1上に半田付け等の方法で固定された
銅ブロック、3は前記銅ブロック2上に取り付けられ、
高周波混成集積回路の能動素子である半導体チップ、4
は前記基板1上の回路パターン、5は前記基板1の上面
に構成され、銅ブロック2が取り付けられる接地パター
ン、6は前記基板1の下面に取り付けられた放熱フイ
ン、7は前記半導体チップ3と銅ブロック2および回路
パターン4とを接続するワイヤ、8は前記基板1の下面
全面の接地電極と上面の接地パターン5を接続するスル
ーホールである。In FIGS. 3 and 4, reference numeral 1 denotes a substrate having circuits on the upper surface and a ground electrode on the lower surface to form a high frequency hybrid integrated circuit, and 2 denotes copper fixed on the substrate 1 by a method such as soldering. Blocks 3 are mounted on said copper block 2,
Semiconductor chips which are active elements of high frequency hybrid integrated circuits, 4
Is a circuit pattern on the substrate 1, 5 is a ground pattern on the upper surface of the substrate 1 to which the copper block 2 is attached, 6 is a radiating fin attached to the lower surface of the substrate 1, 7 is the semiconductor chip 3 A wire connecting the copper block 2 and the circuit pattern 4 is a through hole connecting the ground electrode on the entire lower surface of the substrate 1 and the ground pattern 5 on the upper surface.
半導体チップ3は、ワイヤ7により回路パターン4およ
び銅ブロック2へ接続される。この時、銅ブロック2
は、接地パターン5,スルーホール8を通じて放熱フイン
6に接続されており、半導体チップ3の共通端子が接地
され、共通端子以外が他部の回路へ接続される。The semiconductor chip 3 is connected to the circuit pattern 4 and the copper block 2 by the wire 7. At this time, copper block 2
Is connected to the heat dissipation fin 6 through the ground pattern 5 and the through hole 8, the common terminal of the semiconductor chip 3 is grounded, and the parts other than the common terminal are connected to the circuits of other parts.
また、半導体チップ3で発生した熱は、銅ブロック2に
より、熱の流れる断面積を広げられ、基板1を通じて放
熱フイン6から放熱される。Further, the heat generated in the semiconductor chip 3 is radiated from the heat radiating fin 6 through the substrate 1 by expanding the cross-sectional area through which the heat flows by the copper block 2.
以上のように構成された従来の高周波混成集積回路は、
半導体チップ3の共通端子はワイヤ7−銅ブロック2−
スルーホール8を通して放熱フイン6に接地されてお
り、動作周波数が高くなると、放熱フイン6と半導体チ
ップ3の共通端子間のリアクタンス成分が大きくなり、
特性が低下するという問題点があった。The conventional high-frequency hybrid integrated circuit configured as described above is
The common terminal of the semiconductor chip 3 is a wire 7-copper block 2-
It is grounded to the heat dissipation fin 6 through the through hole 8, and when the operating frequency becomes high, the reactance component between the heat dissipation fin 6 and the common terminal of the semiconductor chip 3 becomes large,
There is a problem that the characteristics are deteriorated.
また、放熱の面でも半導体チップ3で発生した熱は銅ブ
ロック2−基板1を通じて放熱フイン6へと放熱される
ため、基板1の部分の熱抵抗が高くなるという問題点が
あった。Also, in terms of heat dissipation, the heat generated in the semiconductor chip 3 is dissipated to the heat dissipation fins 6 through the copper block 2 and the substrate 1, so that there is a problem that the thermal resistance of the part of the substrate 1 increases.
この考案は、上記のような従来の問題点を除去するため
になされたもので、リアクタンス成分および熱抵抗を低
減させ、半導体チップの共通端子−放熱フイン間のリア
クタンス成分を小さくし、かつ半導体チップ−放熱フイ
ン間の熱抵抗を小さくできる高周波混成集積回路を得る
ことを目的とする。The present invention has been made to eliminate the above-mentioned conventional problems, and reduces the reactance component and thermal resistance, reduces the reactance component between the common terminal of the semiconductor chip and the heat dissipation fin, and reduces the semiconductor chip. -To obtain a high-frequency hybrid integrated circuit that can reduce the thermal resistance between the heat dissipation fins.
この考案に係る高周波混成集積回路は、半導体チップ−
放熱フイン間の熱抵抗を下げるための銅ブロックを基板
外部に突出せしめ、前記放熱フインを断面L字形に形成
し、前記銅ブロックと放熱フインとが直接接触する構造
としたものである。A high frequency hybrid integrated circuit according to the present invention is a semiconductor chip-
A copper block for reducing the thermal resistance between the heat radiation fins is projected to the outside of the substrate, the heat radiation fin is formed in an L-shaped cross section, and the copper block and the heat radiation fin are in direct contact with each other.
この考案に係る高周波混成集積回路は、半導体チップが
取り付けられる銅ブロックが直接放熱フインと接触して
いるため、半導体チップの共通端子から放熱フインへは
ワイヤ−銅ブロックの接続となり、スルーホール分のリ
アクタンス成分が低減できる。また、放熱の面でも半導
体チップで発生した熱は銅ブロックのみを通して放熱フ
インへ放熱されるため、基板の部分の熱抵抗が低減でき
る。In the high frequency hybrid integrated circuit according to the present invention, since the copper block to which the semiconductor chip is attached is in direct contact with the heat dissipation fin, a wire-copper block is connected from the common terminal of the semiconductor chip to the heat dissipation fin, and the through hole The reactance component can be reduced. Also in terms of heat dissipation, the heat generated in the semiconductor chip is radiated to the heat dissipation fins only through the copper block, so that the thermal resistance of the substrate part can be reduced.
以下、この考案の一実施例を第1図,第2図について説
明する。An embodiment of the present invention will be described below with reference to FIGS.
第1図はこの考案の高周波混成集積回路の一実施例を示
す図で、銅ブロック上に半導体チップを組み立てた部分
の斜視図であり、第1図のA−A線の断面図を第2図に
示す。FIG. 1 is a diagram showing an embodiment of a high frequency hybrid integrated circuit of the present invention, which is a perspective view of a portion where a semiconductor chip is assembled on a copper block, and a sectional view taken along the line AA of FIG. Shown in the figure.
第1図,第2図において、1および3〜7は第3図に示
したものと同等のものであるので、その説明を省略す
る。2は前記基板1上の接地パターン5に取り付けられ
た銅ブロックであるが、基板1より外にはみだした構
造、すなわち基板端部より突出せしめ、放熱フイン6と
直接接触する構造となっている。In FIGS. 1 and 2, 1 and 3 to 7 are the same as those shown in FIG. Reference numeral 2 denotes a copper block attached to the ground pattern 5 on the substrate 1, which has a structure protruding outside the substrate 1, that is, a structure in which it is made to project from the end of the substrate and directly contacts the heat dissipation fin 6.
また、9は前記放熱フイン6の断面L字形に形成された
曲げ部で、この部分に銅ブロック2の突出部が接触す
る。半導体チップ3はワイヤ7により回路パターン4お
よび銅ブロック2へ接続され動作を行う。Reference numeral 9 is a bent portion formed in the L-shaped cross section of the heat dissipation fin 6, and the protruding portion of the copper block 2 contacts this portion. The semiconductor chip 3 is connected to the circuit pattern 4 and the copper block 2 by the wire 7 and operates.
上記のように銅ブロック2を基板1よりはみ出させ、か
つ放熱フイン6と放熱フイン6の曲げ部9に直接接触し
た構造としたため、半導体チップ3の共通端子と放熱フ
イン6は、ワイヤ−7−銅ブロック2−放熱フイン6の
曲げ部9により接続されており、リアクタンス成分の低
減がなされる。As described above, since the copper block 2 protrudes from the substrate 1 and is in direct contact with the heat dissipation fin 6 and the bent portion 9 of the heat dissipation fin 6, the common terminal of the semiconductor chip 3 and the heat dissipation fin 6 are connected to the wire-7- The copper block 2 is connected by the bent portion 9 of the heat dissipation fin 6, and the reactance component is reduced.
また、半導体チップ3で発生した熱は銅ブロック2−放
熱フイン6の曲げ部9を通じて放熱フイン6より放熱さ
れるため、熱抵抗の低減がはかれる。Further, the heat generated in the semiconductor chip 3 is radiated from the heat radiating fins 6 through the bent portions 9 of the copper block 2 and the heat radiating fins 6, so that the thermal resistance can be reduced.
以上説明したように、この考案は、半導体チップ−放熱
フイン間の熱抵抗を下げるための銅ブロックを基板外部
に突出せしめ、前記放熱フインを断面L字形に形成し、
前記銅ブロックと放熱フインとが直接接触する構造とし
たので、半導体チップの共通端子から放熱フインにかけ
てのリアクタンス成分を低減することができ、特性が向
上するとともに、熱抵抗の低減がはかれるので、放熱効
果を向上することができる等の効果がある。As described above, according to the present invention, the copper block for reducing the thermal resistance between the semiconductor chip and the heat dissipation fin is projected to the outside of the substrate, and the heat dissipation fin is formed into an L-shaped cross section.
Since the copper block and the heat dissipation fin are in direct contact with each other, the reactance component from the common terminal of the semiconductor chip to the heat dissipation fin can be reduced, the characteristics are improved, and the thermal resistance can be reduced. There is an effect that the effect can be improved.
第1図はこの考案の高周波混成集積回路の一実施例を示
す斜視図、第2図は、第1図のA−A線の断面図、第3
図は従来の高周波混成集積回路の斜視図、第4図は、第
3図のB−B線の断面図を示す。 図において、1は基板、2は銅ブロック、3は半導体チ
ップ、4は回路パターン、5は接地パターン、6は放熱
フイン、7はワイヤ、9は放熱フインの断面L字形の曲
げ部を示す。 なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a perspective view showing an embodiment of the high frequency hybrid integrated circuit of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG.
FIG. 4 is a perspective view of a conventional high frequency hybrid integrated circuit, and FIG. 4 is a sectional view taken along the line BB in FIG. In the figure, 1 is a substrate, 2 is a copper block, 3 is a semiconductor chip, 4 is a circuit pattern, 5 is a ground pattern, 6 is a heat radiation fin, 7 is a wire, and 9 is a bent portion having an L-shaped cross section. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
成され、裏面に放熱フインが取り付けられ、さらに、前
記接地パターン上に載置された銅ブロック上に半導体チ
ップが載置され、前記半導体チップの共通端子と前記銅
ブロックおよび回路パターンとがそれぞれワイヤにより
接続された混成集積回路において、前記半導体チップ−
放熱フイン間の熱抵抗を下げるための前記銅ブロックを
前記基板外部に突出せしめ、前記放熱フインを断面L字
形に形成し、前記銅ブロックと放熱フインとが直接接触
する構造としたことを特徴とする高周波混成集積回路。1. A ground pattern and a circuit pattern are formed on a substrate, a radiating fin is attached to a back surface, and a semiconductor chip is mounted on a copper block mounted on the ground pattern. In the hybrid integrated circuit in which the common terminal, the copper block, and the circuit pattern are connected by wires, respectively.
The copper block for reducing the thermal resistance between the heat dissipation fins is projected to the outside of the substrate, the heat dissipation fin is formed in an L-shaped cross section, and the copper block and the heat dissipation fin are in direct contact with each other. High frequency hybrid integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989040367U JPH0727635Y2 (en) | 1989-04-04 | 1989-04-04 | High frequency hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989040367U JPH0727635Y2 (en) | 1989-04-04 | 1989-04-04 | High frequency hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02131351U JPH02131351U (en) | 1990-10-31 |
JPH0727635Y2 true JPH0727635Y2 (en) | 1995-06-21 |
Family
ID=31550095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989040367U Expired - Lifetime JPH0727635Y2 (en) | 1989-04-04 | 1989-04-04 | High frequency hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0727635Y2 (en) |
-
1989
- 1989-04-04 JP JP1989040367U patent/JPH0727635Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02131351U (en) | 1990-10-31 |
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