JPH07273631A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the noise generated at switching of an output circuit provided in the semiconductor integrated circuit. CONSTITUTION:When a signal is given to an input terminal X, output PMOS 41, NMOS 42 are switched by a driver 30. Gates of PMOS 51, NMOS 61 are controlled by a voltage at an output terminal Y, and nodes N31, N32 are feedback-controlled by a voltage at the output terminal Y. Thus, the resistance of the PMOS 41 and the NMOS 42 is increased only at the start of switching without losing current drive capability in a stable state of DC. Thus, a large current flowing transiently through the PMOS 41 or the NMOS 42 is limited and the noise by this current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an MO having an output circuit.
The present invention relates to an S-type semiconductor integrated circuit, and more particularly to an output circuit in which measures are taken against a sudden large current generated at the time of switching and noise caused thereby.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of an output circuit provided in a conventional MOS semiconductor integrated circuit. This output circuit is a circuit for transmitting a signal inside the semiconductor integrated circuit to the outside, and has an input terminal X for inputting a signal inside the semiconductor integrated circuit, to which a driver 10 for signal input is connected. . The driver 10 has two inverters 11, 1
2 and their output side nodes (contact points) N11,
N12 is an output P-channel MOS transistor (hereinafter referred to as PMO) for driving a load connected to the outside.
The gate of an S channel 21 and the gate of an N-channel MOS transistor (hereinafter referred to as NMOS) 22 are connected to each other. The source of the PMOS 21 is connected to the high power supply potential VCC, and the drain thereof is the output terminal Y.
It is connected to the. The output terminal Y is a terminal to which a load is connected to the outside, the drain of the NMOS 22 is connected to the output terminal Y, and the source of the NMOS 22 is connected to the ground potential V.
It is connected to SS. The output PMOS 21 is a transistor for flowing an outflow current -i from the power supply potential VCC side to the output terminal Y, and the NMOS 22 is a transistor for flowing an inflow current i from the output terminal Y to the ground potential VSS side. FIG. 3 is a voltage / current waveform diagram of the output circuit shown in FIG. The signal processed in the semiconductor integrated circuit is input to the input terminal X for transmitting the processing result to the outside and is inverted by the inverters 11 and 12 in the driver 10. The signals inverted by the inverters 11 and 12 are respectively sent to the gate of the PMOS 21 and the gate of the NMOS 22 in the output stage for driving the external load via the output side nodes N11 and N12. Then, the PMOS 21 or N
The MOS 22 is turned on and off to drive the load connected to the output terminal Y. For example, when the signal input to the input terminal X is at "H" level, it is inverted by the inverters 11 and 12, and the output side nodes N11 and N12 thereof become "L" level. When the nodes N11 and N12 become "L" level, the PMOS 21 turns on and the NMOS
22 turns off. Then, the outflow current -i flows from the power supply potential VCC side to the output terminal Y. When the signal input to the input terminal X is at "L" level, it is the inverter 1
1 and 12 are inverted to output nodes N11 and N
12 becomes "H" level. When the nodes N11 and N12 become "H" level, the PMOS 21 turns off and the NMOS 22 turns on, and the inflow current i flows from the output terminal Y to the ground potential VSS side through the NMOS 22.

[0003]

As the speed of semiconductor integrated circuits increases, so does the speedup of their output circuits. Therefore, in the conventional output circuit shown in FIG. 2, in order to drive an external load at a high speed, the transistor sizes of the output PMOS 21 and the NMOS 22 are increased and their ON resistances are set to low resistance values. High speed is realized by charging and discharging the battery with a large current. However, the output PMOS to or from the load
When the charging / discharging current flowing through the NMOS 21 and the NMOS 22 is large,
The following problems occur. As shown in the voltage-current waveform diagram of FIG. 3, when the output terminal Y changes from the “H” level to the “L” level, the inflow current (discharge current) i from the load passes from the load through the NMOS 22 to the ground potential VSS. Flowing to the side.
When the output terminal Y changes from the “L” level to the “H” level, the outflow current (charging current) −i to the load flows from the power supply potential VCC side to the load via the PMOS 21. These currents i and -i generate noise on the power supply potential VCC side or the ground potential VSS side, or on the output itself. This noise is caused by the resistance of the power supply line and the ground line in the semiconductor integrated circuit, the resistance and inductance of the bonding line and the inner lead, and the like. This noise adversely affects not only the external circuit connected to the output terminal Y but also the semiconductor integrated circuit. For example, when a semiconductor integrated circuit is provided with a latch input circuit, a latch circuit, a flip-flop circuit, etc., noise may be generated in the latch input circuit and erroneous data may be input to the latch circuit, or the flip-flop circuit may be input. There is a risk that the circuit will be inverted. Furthermore, output PMOS 21 and NMOS
Electromagnetic noise generated when switching 22 is also a problem. The steeper the rising and falling characteristics of the output voltage output from the output terminal Y, the more noise containing more harmonic components is generated. This electromagnetic noise causes electromagnetic interference in communication equipment such as an external radio. The present invention has the problem that the conventional technique has a problem that in the conventional output circuit, the size of the output transistor is set to a large value so as to drive the external load at a high speed and set to a low resistance value. The present invention provides a semiconductor integrated circuit that solves the problem that a large current flows to generate noise and that reduces the noise generated from the output circuit during switching.

[0004]

In the first invention, in order to solve the above-mentioned problems, the source is a power supply potential (for example, VC).
C or VSS or the like), an output circuit having an output MOS transistor whose drain is connected to an output terminal for load connection, respectively, and the output M is based on an internal signal.
A MOS transistor for control is provided in a semiconductor integrated circuit such as a MOS type which controls the gate of an OS transistor and outputs an output signal corresponding to a signal inside the OS transistor to the output terminal. This control MOS transistor is of the same channel type as the output MOS transistor, has a source connected to the power supply potential, a drain connected to the gate of the output MOS transistor, and a gate connected to the output terminal. In the second invention, the source of the control MOS transistor of the first invention is passed through a clamp MOS transistor of the same channel type as the control MOS transistor and having a drain and a gate commonly connected, It is connected to the power supply potential of. In the third invention,
A first source whose source is connected to a first power supply potential (eg, VCC) and whose drain is connected to an output terminal for connecting a load.
Channel type (eg P type) first output MOS
The transistor and the source have a second power supply potential (for example, V
An output circuit having a second output type MOS transistor of the second channel type (for example, N type, etc.) whose drains are connected to the output terminals, respectively, based on an internal signal. And a semiconductor integrated circuit which controls each gate of the second output MOS transistor to output an output signal corresponding to a signal inside the second output MOS transistor to the output terminal. A 2-channel type second control MOS transistor is provided. Here, in the first control MOS transistor, the source is connected to the first power supply potential, the drain is connected to the gate of the first output MOS transistor, and the gate is connected to the output terminal. Also,
The source of the second control MOS transistor is the second
, The drain is connected to the gate of the second output MOS transistor, and the gate is connected to the output terminal. In a fourth invention, the source of the first control MOS transistor of the third invention is passed through the first channel type first clamp MOS transistor in which the drain and the gate are commonly connected, and the third invention is provided. Is connected to the first power supply potential. Furthermore, the source of the second control MOS transistor of the third invention is connected to the second channel type second clamp MOS transistor of which the drain and the gate are commonly connected, and the second control MOS transistor of the third invention is provided. It is connected to the power supply potential.

[0005]

According to the first invention, since the semiconductor integrated circuit having the output circuit is configured as described above, the control MOS transistor is gate-controlled by the voltage of the output terminal,
The signal voltage applied to the gate of the output MOS transistor that drives an external load is feedback-controlled. As a result, the resistance value of the output MOS transistor increases only when switching of the output MOS transistor is started, and a large current that transiently flows is limited. According to the second invention, when the output MOS transistor is turned on, it is clamped by the clamp MOS transistor so that the gate voltage of the output MOS transistor does not fall below the threshold voltage of the clamp MOS transistor, for example. It According to the third aspect of the invention, the gate control of the first and second control MOS transistors is performed by the voltage of the output terminal, and the gates of the first and second output MOS transistors that drive an external load are applied. The signal voltage is
To be fed back. As a result, the resistance value of the first and second output MOS transistors increases only at the start of switching, and the large current that transiently flows is limited. According to the fourth invention, the first and second
When the output MOS transistors of the
The gate voltage of the OS transistor is clamped by the first and second clamping MOS transistors so that it does not become lower than the threshold voltage of the first and second clamping MOS transistors, for example. Therefore, the above problem can be solved.

[0006]

First Embodiment FIG. 1 is a circuit diagram of an output circuit provided in a MOS type semiconductor integrated circuit showing a first embodiment of the present invention. This output circuit is a circuit for transmitting signals inside the semiconductor integrated circuit to the outside, and has an input terminal X for inputting the signals inside thereof, and a signal input driver for driving the gate of the output transistor. 30 is connected. The driver 30 is composed of two inverters 31 and 32 that invert the signal of the input terminal X. Inverters 31, 32
The output side nodes N31 and N32 have a gate and an NMOS of an output PMOS 41 for driving an external load.
42 gates are connected to each other. PMOS 41
Is connected to the power supply potential VCC, and its drain is connected to the output terminal Y for connecting an external load.
This PMOS 41 has an output terminal Y from the power supply potential VCC side.
This is a transistor for flowing outflow current -i. Output terminal Y
The drain of the NMOS 42 is connected to the
The source of 42 is connected to the ground potential VSS. The NMOS 42 is a transistor that allows an inflow current i to flow from the output terminal Y to the ground potential VSS side. The node N31 has a control PM for controlling the gate potential of the PMOS 41.
The drain of the OS 51 is connected, and the gate of the PMOS 51 is connected to the output terminal Y. The drain and gate of the PMOS 52 for clamping are connected to the source of the PMOS 51, and the source of the PMOS 52 is connected to the power supply potential VCC. Further, the node N32 has N
Controlling NMOS 6 for controlling the gate potential of the MOS 42
The drain of 1 is connected, and the gate of the NMOS 61 is connected to the output terminal Y. The drain and the gate of the clamping NMOS 62 are connected to the source of the NMOS 61, and the source of the NMOS 62 is connected to the ground potential VSS.
It is connected to the.

FIG. 4 is a voltage-current waveform diagram of the output circuit shown in FIG. 1. The operations (1), (2) and (3) of the output circuit of FIG. 1 will be described with reference to this figure. (1) When "H" level is transmitted to the input terminal X When the "H" level is input to the input terminal X, it is inverted by the inverters 31 and 32 and their output side node N
31 and N32 become "L" level. Nodes N31, N
When 32 becomes “L” level, PMOS 41 turns on and N
The MOS 42 is turned off, the outflow current -i flows from the power supply potential VCC side to the output terminal Y through the PMOS 41, and the output terminal Y becomes "H" level. (2) When the potential of the input terminal X changes from "H" level to "L" level When the potential of the input terminal X changes from "H" level to "L" level, the output side node N31 of the inverter 31 The operation is as follows. That is, the gate is the output terminal Y
The PMOS 51 connected to is off. And P
The inverter 31 driving the node N31 immediately receives the change from the "L" level to the "H" level without being affected by the MOSs 51 and 52. Therefore, the PMO that drives the output
S41 is immediately turned off. On the other hand, regarding the operation of the output side node N32 of the inverter 32, the inverter 32 driving the node N32 tries to rise from the "L" level to the "H" level. However, at the initial stage of this change, the level of the output terminal Y is still at the “H” level, so the NMOS 61 is turned on and is temporarily clamped by the threshold voltage V _tN of the NMOS 62. The NMOS 42 that drives the load is weakly turned on, and a sudden inflow of the current (i) is suppressed. However, the NMOS4 that drives the load
Since No. 2 is on, the voltage level of the output terminal Y gradually decreases. When the voltage at the output terminal Y drops,
The gate voltage of the NMOS 61 will drop,
The on resistance of the NMOS 61 is increased. Therefore, the potential of the node N32 is raised to "H" level by the inverter 32 driving the node N32 and gradually rises. Then, the on-resistance of the NMOS 42 is further decreased, and the voltage of the output terminal Y becomes the ground potential VSS.
Approaching. After that, when the voltage of the output terminal Y becomes the ground potential VSS, the NMOS 61 is completely turned off, and the potential of the node N32 becomes completely "H" level. Therefore, the NMOS 42 that drives the load is completely turned on, and the load can be driven with low resistance.

(3) When the input terminal X changes from the "L" level to the "H" level When the input terminal X changes from the "L" level to the "H" level, exactly the opposite of the above (2). It will work. That is, regarding the operation of the node N32, the NMOS 61 whose gate is connected to the output terminal Y is off. And NMOS
Immediately from the “H” level to the “L” level by the inverter 32 driving the node N32 without being affected by the 61 and 62.
Become a level. Therefore, the NMOS 42 that drives the load
Turns off immediately. On the other hand, looking at the operation of the output side node N31 of the inverter 31, the inverter 31 driving the node N31 tries to decrease from the "H" level to the "L" level. However, at the initial stage of the change, since the level of the output terminal Y is still at the “L” level, the PMOS 51 is turned on and is temporarily clamped by the threshold voltage V _tP of the PMOS 52. The PMOS 41 that drives the load is weakly turned on, and abrupt outflow of current (-i) is suppressed. However, the PMOS that drives the load
Since 41 is turned on, the voltage level of the output terminal Y gradually rises. When the voltage of the output terminal Y rises, the gate voltage of the PMOS 51 rises, and the ON resistance of the PMOS 51 rises. Therefore, the potential of the node N31 is lowered to the "L" level by the inverter 31 driving the node N31 and gradually falls. The on resistance of the PMOS 41 further decreases, and the voltage of the output terminal Y approaches the power supply potential VCC. When the voltage of the output terminal Y reaches the power supply potential VCC, the PMOS 51 is completely turned off and the potential of the node N31 is completely set to "L" level. Therefore, the PMOS 41 that drives the load is completely turned on, and the load can be driven with low resistance. As described above, in the first embodiment, the PMOS 41 and NMO for driving the external load are used.
The signal voltage applied to the gate of S42 is set to the PMOS 51, 5
2 and the NMOSs 61 and 62 feed back the voltage of the output terminal Y for control. Therefore, without impairing the current drive capacity when DC is stable,
Since the resistance values of the NMOS 41 and the PMOS 42 that drive the load can be increased only when the switching is started, there is an advantage that a large current that transiently flows is limited and noise due to this current can be reduced.

Second Embodiment FIG. 5 is a circuit diagram of an output circuit provided in a MOS type semiconductor integrated circuit showing a second embodiment of the present invention. Elements that are common to the elements are given common reference numerals. This output circuit is different from the output circuit of the first embodiment in that it is composed of only the inverter 32 of the first embodiment and the PMOSs 42, 61 and 62. In this configuration, the external output terminal Y is usually lifted to a high potential by a pull-up resistor (not shown), for example. The operations (1), (2) and (3) of this output circuit will be described below. (1) When an "H" level signal is transmitted to the input terminal X When an "H" level signal is input to the input terminal X, it is inverted by the inverter 32 and the output side node of the inverter 32. N32 becomes "L" level, and output NMOS
42 turns off. Therefore, the output terminal Y becomes "H" level via the pull-up resistor (not shown). (2) When the input terminal X changes from “H” level to “L” level When the input terminal X changes from “H” level to “L” level, the potential of the output side node N32 of the inverter 32 becomes complete. Attempt to rise from the "L" level, that is, the VSS level to the "H" level. However, since the level of the output terminal Y is still at the “H” level at the beginning of the change, the NMOS 42
Is on, and the threshold voltage V of the NMOS 62 is
Temporarily clamped at _tN . However, N that drives the load
Since the MOS 42 is on, the voltage level of the output terminal Y gradually decreases. When the voltage of the output terminal Y decreases, the gate voltage of the NMOS 61 decreases, and the ON resistance of the NMOS 61 increases. Therefore, the potential of the node N32 is "H" of the inverter 32.
It is raised to a level and gradually rises. NMOS 4
The on-resistance of No. 2 further decreases, and the voltage of the output terminal Y approaches the ground potential VSS. When the voltage of the output terminal Y becomes the ground potential VSS, the NMOS 61 is completely turned off, and the potential of the node N32 becomes completely "H" level. Therefore, the NMOS 42 that drives the load is completely turned on, and the load can be driven with low resistance.

(3) When the input terminal X changes from "L" level to "H" level When the input terminal X changes from "L" level to "H" level, the potential of the node N32 changes from "H" level. Changes to "L" level. However, at this time, the potential of the output terminal Y is VS.
Since it is at the S level, the NMOS 61 is off. Therefore, there is no influence of the NMOSs 61 and 62, and the node N3
The potential of 2 immediately drops to "L" level. An NMOS that drives a load when the potential of the node N32 drops to "L" level
42 is immediately turned off, and the output terminal Y is set to high impedance. When the output terminal Y is hoisted to a high potential by a pull-up resistor (not shown), the output terminal Y immediately becomes "H" level. As described above, in the second embodiment, the signal voltage applied to the gate of the NMOS 42 that drives the external load is controlled by feeding back the voltage of the output terminal Y by the NMOS 61 and 62. As in the first embodiment, the resistance value of the NMOS 42 for driving the load can be increased only at the start of its switching without impairing the current driving capability when the direct current is stable, so that the large current that transiently flows is limited. There is an advantage that noise due to current can be reduced. Moreover, since this output circuit has a smaller number of elements than the output circuit of the first embodiment, there is an advantage that the circuit configuration is simple.

Third Embodiment FIG. 6 is a circuit diagram of an output circuit provided in a MOS type semiconductor integrated circuit showing a third embodiment of the present invention. Elements that are common to the elements are given common reference numerals. This output circuit is different from the output circuit of the first embodiment in that it is composed of only the inverter 31 of the first embodiment and the PMOSs 41, 51 and 52. Normally, the external output terminal Y is suspended at the ground potential VSS by a pull-down resistor (not shown). In this output circuit, the NMOSs 42, 61 and 62 of the second embodiment are PMO.
Since the circuit configuration is replaced with S41, 51, 52, its operation is complementary to that of the second embodiment. Less than,
The operations (1), (2) and (3) of the third embodiment will be described. (1) When "L" level signal is transmitted to the input terminal X When "L" level signal is transmitted to the input terminal X, the output side node N31 of the inverter 31 becomes "H" level, The PMOS 41 is off. Therefore, the output terminal Y is "L" by a pull-down resistor (not shown).
It becomes a level. (2) When the input terminal X changes from the “L” level to the “H” level When the input terminal X changes from the “L” level to the “H” level, the potential of the output side node N31 of the inverter 31 becomes “complete”. Attempts to drop to the H level, that is, the "H" level to the VSS level. However, at the initial stage of the change, the level of the output terminal Y is still at the “L” level, so the PMOS 51
Is on, and the threshold voltage V of the PMOS 52 is
It is temporarily clamped at _tP . PMOS41 driving load
Turns on weakly, and sudden inflow of current is suppressed. However, since the PMOS 41 that drives the load is on,
The voltage level of the output terminal Y gradually rises. When the voltage of the output terminal Y rises, the gate voltage of the PMOS 51 rises, and the ON resistance of the PMOS 51 rises. Therefore, the potential of the node N31 is lowered to the "L" level of the inverter 31 and gradually falls. The on resistance of the PMOS 41 further decreases, and the voltage of the output terminal Y approaches the power supply potential VCC. When the voltage of the output terminal Y reaches the power supply potential VCC, the PMOS 51
Is completely turned off, and the potential of the node N31 becomes completely "L" level. Therefore, the PMOS 41 that drives the load is completely turned on, and the load can be driven with low resistance.

(3) When the input terminal X changes from "H" level to "L" level When the input terminal X changes from "H" level to "L" level, the potential of the output side node N31 of the inverter 31 is changed. The "L" level changes to the "H" level. However, at this time, since the potential of the output terminal Y is at the VCC level, P
MOS51 is off. Therefore, the PMOS 51,
There is no influence of 52, and the potential of the node N31 immediately becomes "H" level. As a result, the PMOS 41 that drives the load is immediately turned off, and the output terminal Y becomes high impedance. When the output terminal Y is suspended to the ground potential VSS by a pull-down resistor (not shown), it immediately goes to "L" level. As described above, in the third embodiment, the signal voltage applied to the gate of the PMOS 41 that drives the external load is controlled by feeding back the voltage of the output terminal Y by the PMOSs 51 and 52. Two
Similar to the embodiment of the above example, the noise can be reduced by limiting the large current that transiently flows without impairing the current drive capability when the direct current is stable, and moreover, since the number of elements is small, the circuit configuration can be simplified. There are advantages.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) The driver 30 of FIG.
It may be constituted by a logic gate such as an R gate or other driver means. Similarly, the inverters 31 and 32 in FIGS. 5 and 6 may be configured by other driver means such as a logic gate. (B) In the output circuit of FIG. 1 and FIG.
2 is for clamping the voltage of the node N31 so as not to be lower than the threshold voltage V _{tP of} the PMOS 52 when the PMOS 41 for driving the load is turned on. Therefore, if the ratio of the output ON resistance of the driver means such as the inverter 31 and the ON resistance of the PMOS 51 is set appropriately, the PMOS 52 is not always necessary. PMOS
When 52 is omitted, the circuit configuration can be further simplified. (C) In the output circuit of FIGS. 1 and 5, the NMOS 6
2 is for clamping the voltage of the node N32 so as not to be lower than the threshold voltage V _{tN of the} NMOS 62 when the NMOS 42 for driving the load is turned on. Therefore, if the ratio of the output ON resistance of the driver means such as the inverter 32 and the ON resistance of the NMOS 61 is set appropriately, the NMOS 62 is not always necessary. NMOS 6
When 2 is omitted, the circuit configuration can be simplified. (D) In the output circuit of FIGS. 1, 5 and 6, PM
OS is replaced with NMOS, NMOS is replaced with PMOS, and accordingly, the power supply potential VCC is changed to the ground potential VSS and the ground potential V is changed.
Even if SS is replaced with the power supply potential VCC, the same operation and effect as in the above-described embodiment can be obtained. In addition, the ground potential VS
The power supply potential VCC including S may be replaced with another constant potential. For example, the power supply potential VCC in FIGS. 1 and 6 may be replaced with the ground potential VSS, and the ground potential VSS may be replaced with a negative potential. Similarly, in the output circuit of FIG. 5, the ground potential VSS may be replaced with a negative potential. (E) Although the MOS type semiconductor integrated circuit has been described in the above embodiment, the inside of the semiconductor integrated circuit is a bipolar transistor or a BiCMO in which a bipolar transistor and a complementary MOS transistor (CMOS) are combined.
Other transistor configurations such as S may be used.

[0014]

As described in detail above, according to the first invention, the signal voltage applied to the gate of the output MOS transistor for driving the external load is fed back by the control MOS transistor. Since the control is performed by doing so, the resistance value of the output MOS transistor can be increased only at the start of the switching without impairing the current driving capability when the direct current is stable.
Therefore, a large current that transiently flows can be limited, and noise due to this current can be reduced. According to the second invention, when the output MOS transistor is turned on, the gate voltage of the output MOS transistor is clamped by the clamp MOS transistor. Therefore, the voltage of the output terminal using the control MOS transistor can be accurately determined. Feedback control can be performed. According to the third invention, the signal voltage applied to the gates of the first and second output MOS transistors driving the external load is fed back to the output terminal voltage by the first and second control MOS transistors. Therefore, as in the first invention, the resistance values of the first and second output MOS transistors can be changed only at the start of the switching without deteriorating the current driving capability when the direct current is stable. Can be made bigger. Therefore, a large current transiently flowing through the first and second output MOS transistors can be limited, and noise due to this current can be reduced. According to the fourth aspect of the invention, since the first and second clamp MOS transistors are provided, when the first and second output MOS transistors are turned on, their gate voltage is set to the first and second clamp MOS transistors. It can be clamped with a MOS transistor. Therefore, accurate feedback control of the voltage at the output terminal using the first and second control MOS transistors can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output circuit provided in a semiconductor integrated circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output circuit provided in a conventional semiconductor integrated circuit.

FIG. 3 is a voltage / current waveform diagram of FIG. 2.

FIG. 4 is a voltage / current waveform diagram of FIG. 1.

FIG. 5 is a circuit diagram of an output circuit provided in a semiconductor integrated circuit showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram of an output circuit provided in a semiconductor integrated circuit showing a third embodiment of the present invention.

[Explanation of symbols]

 30 Driver 31, 32 Inverter 41 Output PMOS 42 Output NMOS 51 Control PMOS 52 Clamp PMOS 61 Control NMOS 62 Clamp NMOS VCC Power supply potential VSS Ground potential X Input terminal Y Output terminal

Claims (4)

[Claims] 1. An output circuit having an output MOS transistor whose source is connected to a power supply potential and whose drain is connected to an output terminal for load connection, and which controls a gate of the output MOS transistor based on an internal signal. In the semiconductor integrated circuit for outputting an output signal corresponding to a signal inside the output terminal to the output terminal, the same channel type as the output MOS transistor, the source at the power supply potential, and the drain at the output MOS transistor.
A semiconductor integrated circuit comprising: a control MOS transistor having a gate connected to the output terminal. 2. The power supply potential according to claim 1, wherein the source of the control MOS transistor according to claim 1 is through a clamping MOS transistor having the same channel type as the control MOS transistor and having a drain and a gate commonly connected. A semiconductor integrated circuit characterized by being connected to. 3. A first channel type first output MOS transistor having a source connected to a first power supply potential and a drain connected to an output terminal for load connection, and a source connected to a second power supply potential. Second channel type second output M having drains connected to the output terminals, respectively
A semiconductor including an output circuit having an OS transistor, and controlling each gate of the first and second output MOS transistors based on an internal signal to output an output signal corresponding to the internal signal to the output terminal. In the integrated circuit, a first channel type first control MOS transistor having a source connected to the first power supply potential, a drain connected to the gate of the first output MOS transistor, and a gate connected to the output terminal, respectively. And a second channel type second control MOS transistor having a source connected to the second power supply potential, a drain connected to the gate of the second output MOS transistor, and a gate connected to the output terminal. A semiconductor integrated circuit characterized by being provided. 4. The first control MOS transistor according to claim 3, the source of the first control MOS transistor, through the first channel type first clamping MOS transistor, the drain and the gate are commonly connected, The source of the second control MOS transistor of claim 3 is connected to the power supply potential of the second control type MOS transistor, and the source and the drain of the second control MOS transistor are connected through a second channel type second clamp MOS transistor of which the drain and the gate are commonly connected. A semiconductor integrated circuit characterized by being connected to a second power supply potential.