JPH07273184A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which high integration is not impeded by well isolation. CONSTITUTION:An N type shield layer 2 is formed on a P type semiconductor substrate 1 and a P type isolated well 3 is formed on the layer 2. A P type substrate well 5 is formed contiguously to the P type isolated well 3 through an isolation region 10b where a trench deeper than the thickness of the P type well 3 is filled with an insulator. An isolation region 10a, where a trench shallower than the thicknesses of the P type isolated well 3 and the P type substrate well 5 is filled with an insulator, is formed between the elements in the wells 3 and 5. The deep trench type isolation region 10b provides well isolation and the shallow trench type isolation region 10a provided element isolation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having various kinds of wells on a substrate and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art A plurality of first conductive layers are formed on a semiconductor substrate of a first conductivity type.
A well structure having conductive type wells in which the first conductive type wells are electrically isolated from each other is called a triple well structure. Here, in the semiconductor device having this triple well structure, a conventionally used isolation method between elements and wells will be described below.

FIG. 27 is a partial cross-sectional view showing the structure of a conventional semiconductor device. In FIG. 27, reference numeral 1 denotes a P-type semiconductor substrate, which extends to the back surface of the substrate 1 below. Two
Is a shield layer made of an N-type semiconductor formed on the semiconductor substrate 1, 3 is a P-type isolated well formed on the shield layer 2, and 4 is an N-type well formed adjacent to the P-type isolated well 3. Thus, the shield layer 2 is in a conductive state. Reference numeral 5 denotes a P-type substrate well formed adjacent to the N-type well 4, which is in conduction with the P-type semiconductor substrate 1.

Reference numeral 6 denotes a P-type high-concentration diffusion region formed in the surface layer of the P-type isolated well 3, to which a wide area wiring 17, which will be described later, for fixing the P-type isolated well 3 to the first potential is connected. . Reference numeral 7 denotes an N-type high-concentration diffusion region formed in the surface layer of the N-type well 4, to which a wide area wiring 17, which will be described later, for fixing the N-type well 4 to the second potential is connected. Reference numeral 8 is a second P-type high-concentration diffusion region formed in the surface layer of the P-type substrate well 5, to which a wide area wiring 17 described later for fixing the P-type substrate well 5 to the third potential is connected. . 9 the source / drain diffusion region serving as a source / drain formed on the surface layer of the semiconductor substrate 1, 10 has a width of about 0.2 [mu] m, SiO ₂ or the like insulator to a depth of about 0.4μm in the trenches is buried In the trench type isolation region, the high concentration diffusion region 6,
It is formed between 7, 8 and the source / drain diffusion region 9.

Reference numeral 11 denotes a gate insulating film having a thickness of about 10 nm formed on the source / drain diffusion region 9, 12 denotes a gate electrode formed on the gate insulating film 11, and 13
Internal wiring, the source / drain diffusion region through the internal wiring hole 15b of the SiO ₂ insulating film 14 16 is electrically connected via internal wiring hole 15a of the source / drain diffusion region 9 and the SiO ₂ insulating film 14 is 9 is a memory capacitor electrically connected to the lower electrode 16a and the dielectric 16
b and the upper electrode 16c. Reference numeral 17 is the source / drain diffusion region 9 or the high concentration diffusion regions 6, 7, 8
And a wide area wiring electrically connected through a wide area wiring connection hole 18 of the SiO ₂ insulating film 14.

In the semiconductor device configured as described above, a large number of elements (not shown) are formed in the same well. Between these elements, that is, between the adjacent source / drain diffusion regions 9, By forming a trench type isolation region 10 having a width of 0.2 μm and a depth of 0.4 μm in which an insulator is embedded in the trench, the distance between the adjacent source / drain diffusion regions 9 in the semiconductor substrate 1 is increased. You can get the same function as taking a big one. That is, the isolation breakdown voltage between the source / drain diffusion regions 9 is improved.

Further, by forming the trench type isolation region 10 between the high concentration diffusion regions 6, 7, 8 for fixing the well potential and the source / drain diffusion region 9,
A function similar to that of increasing the distance between the high concentration diffusion regions 6, 7, 8 and the source / drain diffusion regions 9 can be obtained.
That is, the junction breakdown voltage, which is the maximum applied voltage for maintaining the insulation characteristic of the PN junction in the opposite direction, increases.

Further, in the semiconductor device configured as described above, in order to optimize the characteristics of the N-type semiconductor element formed in the P-type isolated well 3 and the P-type substrate well 5,
Since the potential of the P-type isolated well 3 and the potential of the P-type substrate well 5 are set to different values, it is necessary to electrically separate the P-type isolated well 3 and the P-type substrate well 5. Therefore,
By forming the N-type semiconductor shield layer 2 on the bottom surface of the P-type isolated well 3, the P-type isolated well 3 is electrically separated from the P-type semiconductor substrate 1 which is in conduction with the P-type substrate well 5. Further, an N-type well 4 electrically connected to the N-type semiconductor shield layer 2 is formed on the side surface of the P-type isolated well 3 to electrically separate the P-type isolated well 3 and the P-type substrate well 5. I am letting you.

[0009]

In the conventional semiconductor device as described above, in order to electrically isolate wells of the same conductivity type, it is necessary to surround the periphery with wells of different conductivity types. .

However, in the current industrial technology, the boundary position between the P-type well and the N-type well is set to 0.1 μm.
Is difficult to control, and in this conventional example, the width of the N-type well 4 surrounding the P-type isolated well 3 cannot be reduced to 1 μm or less. Therefore, this has been a major obstacle in promoting high integration of semiconductor devices.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a structure of a semiconductor device in which high integration is not hindered by separation of wells, and a method of manufacturing the semiconductor device. The purpose is to provide.

[0012]

In a semiconductor device according to the present invention, a first conductivity type well formed on a first conductivity type semiconductor substrate through a trench type well isolation region and the first conductivity type well. A second conductivity type buried region formed on the entire bottom surface of at least one of the above, and the trench type well isolation region has a depth reaching the second conductivity type buried region.

In the semiconductor device according to the second invention,
The semiconductor device according to the first aspect of the invention is characterized in that the first conductivity type well has a trench type element isolation region for performing element isolation in the well.

Further, in the semiconductor device according to the third invention, the semiconductor device of the third aspect is provided with a second conductivity type well formed on the first conductivity type semiconductor substrate via a trench type well separation region, and the trench type well separation region is provided. However, it has a depth reaching the substrate.

Further, in the semiconductor device according to the fourth invention, in the semiconductor device according to the third invention, the second conductivity type well has a trench type element isolation region for performing element isolation in the well. It is a feature.

In the semiconductor device according to the fifth invention,
A first conductive type well formed on a first conductive type semiconductor substrate via a trench type well isolation region; and a second conductive type buried region formed on the entire bottom surface of at least one of the first conductive type wells. The trench-type well isolation region has a configuration in which a conductor electrically insulated from the first-conductivity-type well is embedded in a trench having a depth reaching the second-conductivity-type buried region.
It is characterized in that the conductor is electrically connected to the second conductivity type buried region.

In the semiconductor device according to the sixth invention,
The semiconductor device of the fifth invention is characterized in that the first conductivity type well has a trench type element isolation region for performing element isolation in the well.

In the method of manufacturing a semiconductor device according to the seventh invention, a first insulating film made of a first insulating material is formed on a semiconductor substrate, and a second insulating material is made on the first insulating film. A step of forming a second insulating film, patterning a two-layer film consisting of the first and second insulating films into a shape corresponding to the both trenches, and anisotropically etching the semiconductor substrate using this as a mask. A step of forming a first trench corresponding to the depth of the shallow trench which becomes the trench type element isolation region, a first protective film made of the first insulator on the entire surface of the semiconductor substrate, and further the first protective film. Forming a second protective film made of the second insulating material on the protective film, forming an insulating film made of the first insulating material on the entire surface of the semiconductor substrate, and filling the inside of the first trench. After doing full etch back, above Forming a plug made of the first insulator in the first trench; forming a resist film on the entire surface of the semiconductor substrate; and patterning the resist film into a shape corresponding to a deep trench to be the trench well isolation region. Using this as a mask, only the first insulator is selectively etched to remove the plug in the first trench that should be the deep trench, and the first and second protective films in the trench are removed. A step of anisotropically etching the semiconductor substrate below the trench by using the two-layer film as a mask to form the deep trench; removing the resist, covering the deep trench with a resist; Selectively etching only the insulator to remove the plug remaining in the first trench to form the shallow trench; A step of removing the second insulating film and the second protective film by selectively etching only the second insulating material after removing the strike, and from the first insulating material to the entire surface of the semiconductor substrate. And a step of burying the first insulator in the shallow trench and the deep trench by forming the insulating film.

In the method of manufacturing a semiconductor device according to the eighth aspect of the present invention, the first insulating film made of the first insulating material is formed on the semiconductor substrate, and the second insulating material is further formed on the first insulating film. A step of forming a second insulating film, patterning a two-layer film consisting of the first and second insulating films into a shape corresponding to the both trenches, and anisotropically etching the semiconductor substrate using this as a mask. A step of forming a first trench corresponding to the depth of the shallow trench which becomes the trench type element isolation region, a first protective film made of the first insulator on the entire surface of the semiconductor substrate, and further the first protective film. Forming a second protective film made of the second insulating material on the protective film, forming an insulating film made of the first insulating material on the entire surface of the semiconductor substrate, and filling the inside of the first trench. After doing full etch back, above Forming a plug made of the first insulator in the first trench; forming a resist film on the entire surface of the semiconductor substrate; and patterning the resist film into a shape corresponding to a deep trench to be the trench well isolation region. Using this as a mask, only the first insulator is selectively etched to remove the plug in the first trench that should be the deep trench, and the first and second protective films in the trench are removed. A step of anisotropically etching the semiconductor substrate below the trench by using the two-layer film as a mask to form the deep trench, after removing the resist, the first insulator is formed on the entire surface of the semiconductor substrate. Is formed and the first insulator is anisotropically etched to remove the first insulator on the bottom surface of the deep trench to remove the first insulator on the side surface of the deep trench. Insulator is formed,
Further, a conductor film made of a conductor is formed on the entire surface of the semiconductor substrate, the conductor film is embedded in a deep trench, and then a resist film is formed on the entire surface of the semiconductor substrate and patterned into a shape corresponding to the deep trench to mask it. And anisotropically etching the conductor film to form a three-layer structure of insulator / conductor / insulator in a deep trench,
After removing the resist, selectively etching only the first insulator to remove plugs remaining in the first trench to form the shallow trench, only the second insulator Is selectively etched to remove the second insulating film and the second protective film, and an insulating film made of the first insulating material is formed on the entire surface of the semiconductor substrate to form the shallow trench in the shallow trench. The method is characterized by including a step of burying the first insulator.

[0020]

In the semiconductor device of the first aspect of the present invention, the second conductivity type buried region is formed over the entire bottom surface of at least one of the first conductivity type wells in the two first conductivity type wells. Of the conductive type wells and the buried region of the second conductive type are electrically separated from each other by a PN junction, and between the adjacent wells of the first conductive type, the wells of the first conductive type penetrate through the wells of the second conductive type. The trench-type well isolation region reaching the type-embedded region is electrically isolated, and therefore the adjacent first conductivity type wells are electrically isolated from each other.

Further, in the semiconductor device of the second invention, trench type element isolation regions shallower than the thickness of the first conductivity type wells are formed between the elements formed in the first conductivity type wells. As a result, the isolation breakdown voltage between the elements is improved, so that the elements can be formed close to each other.

In the semiconductor device of the third invention, the first
The conductive type semiconductor substrate and the bottom surface of the second conductive type well are PN.
The second wells of the second conductivity type, which are electrically separated by the junction, penetrate through the wells of the second conductivity type, and are electrically separated by the trench well isolation region reaching the semiconductor substrate region of the first conductivity type. As a result, the wells of the second conductivity type are electrically separated from each other.

Further, in the semiconductor device of the fourth invention, the trench type element isolation regions shallower than the thickness of the second conductivity type wells are formed between the elements formed in the second conductivity type wells. Since the isolation breakdown voltage between the elements is improved, the elements can be formed close to each other.

In the semiconductor device of the fifth invention, the second conductivity type buried region is formed on the entire bottom surface of at least one of the first conductivity type wells in the two first conductivity type wells. The bottom surface of the first conductivity type well and the second conductivity type buried region are electrically separated by a PN junction, and between the adjacent first conductivity type wells, these first conductivity type wells are penetrated. The trench-type well isolation regions reaching the second-conductivity-type buried regions are electrically isolated from each other, so that the adjacent first-conductivity-type wells are electrically isolated from each other. Since the conductor is electrically connected to the second conductivity type buried region, the potential of the second conductivity type buried region can be set to an arbitrary value via the conductor.

Further, in the semiconductor device of the sixth invention, a trench type element isolation region shallower than the thickness of these first conductivity type wells is formed between the elements formed in the first conductivity type wells. As a result, the isolation breakdown voltage between the elements is improved, so that the elements can be formed close to each other.

Further, in the method of manufacturing a semiconductor device according to the seventh invention, a trench type element isolation region having an insulator filled in a shallow trench and a trench type well isolation region having an insulator filled in a deep trench. Can be formed.

Further, in the semiconductor device of the eighth invention, a trench type element isolation region in which an insulator is embedded in a shallow trench and a conductor which is surrounded by the insulator are embedded in a deep trench. Well isolation regions can be formed.

[0028]

【Example】

Example 1. Hereinafter, the present invention will be described by taking a semiconductor device having a triple well structure, which is an embodiment, as an example.
In the embodiment, the first conductivity type is the P type and the second conductivity type is the second type.
The conductivity type will be described as N type. FIG. 1 is a partial sectional view showing a semiconductor device according to an embodiment of the present invention. In this figure, reference numeral 1 is a P-type semiconductor substrate, which extends to the back surface of the substrate 1 below in the figure. Reference numeral 2 is a shield layer formed of an N-type semiconductor on the semiconductor substrate 1 and having a thickness of about 0.2 μm, and 3 is a P-type isolated well formed on the shield layer 2 and having a thickness of about 1.0 μm. Reference numeral 5 denotes a P-type substrate well formed adjacent to the P-type isolated well 3 with a separation region interposed therebetween, and is in a conductive state with the P-type semiconductor substrate 1.

Reference numeral 6 denotes a P-type high-concentration diffusion region formed in the surface layer of the P-type isolated well 3, to which a wide area wiring 17, which will be described later, for fixing the P-type isolated well 3 to the first potential is connected. . Reference numeral 8 is a second P-type high-concentration diffusion region formed in the surface layer of the P-type substrate well 5, to which a wide area wiring 17 described later for fixing the P-type substrate well 5 to the third potential is connected. . Reference numeral 9 is a source / drain diffusion region which is formed in the surface layer of the semiconductor substrate 1 and serves as a source / drain.

10a has a width of about 0.2 μm and a depth of about 0.4 μm.
In the shallow trench of m, the SiO ₂ insulator which is the _first insulator is buried, and the shallow trench type isolation region which is the trench type element isolation region for performing element isolation is used. The well 5 has a depth less than the thickness of the well 5, and is formed between the high-concentration diffusion regions 6 and 8 and the source / drain diffusion regions 9. 10b is a first deep trench having a width of about 0.2 μm and a depth of about 0.4 μm.
In the deep trench type isolation region which is the trench type well isolation region in which the SiO ₂ insulator which is the insulator of the above is buried, the shield layer 2 is reached at a depth greater than the thickness of the P type isolated well 3 and the P type It is formed in the isolation region between the isolated well 3 and the P-type substrate well 5.

Reference numeral 11 is a gate insulating film having a thickness of about 10 nm formed on the source / drain diffusion region 9, 12 is a gate electrode formed on the gate insulating film 11, and 13 is the source / drain diffusion region 9 and SiO 2. ₂ Internal wiring electrically connected through the internal wiring hole 15a of the insulating film 14, 16
Is a memory electrically connected to the source / drain diffusion region 9 through the internal wiring hole 15b of the SiO ₂ insulating film 14.
The capacitor is composed of a lower electrode 16a, a dielectric 16b and an upper electrode 16c. Reference numeral 17 denotes the source / drain diffusion region 9 or the high-concentration diffusion regions 6, 7, 8 and Si.
The wide area wiring is electrically connected via the wide area wiring connection hole 18 of the O ₂ insulating film 14.

In the N-type semiconductor shield layer 2 configured as described above, the bottom surface of the P-type isolated well 3 is formed on the P-type substrate well 5.
Is electrically separated from the P-type substrate 1 electrically connected to, and has a depth equal to or larger than the thickness of the P-type isolated well 3,
The deep trench type isolation region 10b reaching the shield layer 2 of the N type semiconductor has a function of electrically isolating the side surface of the P type isolated well 3 from the P type substrate well 5. Therefore, the P-type isolated well 3 is electrically separated from the P-type substrate well 5, and the P-type isolated well 3 and the P-type substrate well 5,
The potentials of the P-type isolated well 3 and the P-type substrate well 5 can be set to different values in order to optimize the characteristics of the N-type semiconductor element formed in each.

In the well separating method as described above, the N-type semiconductor shield layer 2 is the semiconductor substrate 1.
Since it is formed below the element formed on the surface, it does not occupy the area of the surface of the semiconductor substrate 1 and thus does not hinder the progress of high integration. Further, by separating the side surface in the deep trench type isolation region 10b reaching the N-type semiconductor shield layer 2, the conventional width of 1 μm is obtained.
Since the width of only 0.2 μm is required for the N-type well 4, the occupation of the area of the surface of the semiconductor substrate 1 is significantly reduced, which is advantageous in promoting high integration.

Further, in the semiconductor device constructed as described above, a large number of elements (not shown) are formed in the same well, and these elements are formed, that is, between the adjacent source / drain diffusion regions 9. With a width of 0.2μ
By forming the shallow trench type isolation region 10a having a depth of m and a depth of 0.4 μm, the same function as increasing the distance between the adjacent source / drain diffusion regions 9 in the semiconductor substrate 1 can be obtained. That is, the isolation breakdown voltage between the source / drain diffusion regions 9 is improved.

Further, by forming the trench between the high-concentration diffusion regions 6, 7, 8 for fixing the well potential and the source / drain diffusion regions 9, the high-concentration region 6,
A function similar to that of increasing the distance between 7, 8 and the source / drain diffusion region 9 can be obtained. That is, the junction breakdown voltage, which is the maximum applied voltage for maintaining the insulation characteristic of the PN junction in the opposite direction, increases.

Therefore, by forming the shallow trench type isolation region 10a between the elements, the elements can be formed close to each other, and further high integration can be promoted.

It is needless to say that in this embodiment, the above-described effects can be obtained even if the first conductivity type P type is N type and the second conductivity type N type is P type.

Next, a method of manufacturing the above-described semiconductor device will be described with reference to FIGS. 2 to 21 sequentially show steps of the semiconductor device of this embodiment. First, as shown in FIG. 2A, a first insulating film 20 made of SiO ₂ which is a first insulator having a thickness of about 200 nm and a thickness of about 200 n are formed on the P-type semiconductor substrate 1.
The second insulating film 21 made of Si ₃ N ₄ which is the second insulating material of m is sequentially formed. Next, as shown in FIG. 2B, a resist pattern 22 is formed on the P-type semiconductor substrate 1 by photolithography so that the portion where the trench is formed becomes an opening, and then the resist 22 is masked. As
The first insulating film 20 and the second insulating film 21 are anisotropically etched. Next, when the resist 22 is removed, as shown in FIG.
As shown in (c).

Next, the semiconductor substrate 1 is anisotropically etched by using the second insulating film 21 etched as shown in FIG.
First trench 10 corresponding to a depth of about 0.4 μm of 0a
form c. Next, as shown in FIG. 3B, a first protective film made of SiO ₂ which is a first insulator and has a film thickness of about 10 nm is formed on the surface of the P-type semiconductor substrate 1 in the first trench 10c. 23 is formed by thermal oxidation, and a second film having a thickness of about 20 nm is formed on the first protective film 23 and the entire surface of the semiconductor substrate 1.
The second protective film 24 made of Si ₃ N ₄ which is an insulator of
It is formed by the VD method. Here, since the second insulating film 21 and the second protective film 24 formed thereon have the same components as Si ₃ N ₄ , they will be described below by including them in the second insulating film 21. The first protective film 23 is for protecting the surface of the semiconductor substrate 1 in the trench 10c from the second protective film 24 that exerts stress on the surface of the semiconductor substrate 1.

Next, a SiO ₂ insulator, which is a first insulator, is applied on the entire surface of the semiconductor substrate 1 by a glass coating method or the like to fill the inside of the first trench 10c, and then is etched back by an etch back method. SiO ₂ formed on the second insulating film 21
By completely removing the insulating film, the plug 25 made of a SiO ₂ insulator is formed in the first trench 10c as shown in FIG. 4A. Next, FIG.
As shown in (b), the deep trench isolation region 10
By forming a resist pattern 26 having an opening at the portion of the first trench 10c where b is to be formed by photolithography and performing HF chemical treatment for selectively etching the SiO ₂ insulating film, The plug 25 in the trench 10c not covered with the resist is removed. Next, after removing the resist 26, the second protective film 24 formed on the bottom side surface of the first trench 10c from which the plug 25 has been removed is anisotropically removed by etching, and then the second insulating film 24 is formed. Using the film 21 as a mask, the first protective film 23 made of a SiO ₂ insulating film is anisotropically etched, and then the semiconductor substrate 1 below the trench 10c is anisotropically etched.
A deep trench 10d as shown in FIG. 5A is formed. (Hereinafter, the first trench 10c that has not been etched is referred to as a shallow trench 10e).

Next, as shown in FIG. 5B, a resist pattern 27 is formed by photolithography so as to cover the deep trench 10b formed above, and a plug in the shallow trench 10e is formed by HF chemical treatment. Remove 25. Next, as shown in FIG. 6A, after removing the resist 27, the Si ₃ N ₄ insulating film forming the second insulating film 21 and the second protective film 24 is selectively etched. H ₂ PO ₄ chemical treatment is performed to completely remove the second insulating film 21 and the second protective film 24 in the trench. next,
SiO ₂ which is the first insulator is formed on the entire surface of the semiconductor substrate 1.
6 is formed by depositing an insulating film 28 made of
As shown in (b), the insulating film 28 made of SiO ₂ is embedded in the shallow trench 10e and the deep trench 10d to complete the shallow trench isolation region 10a and the deep trench isolation region 10b. Here, the first protective film 23
Since the first insulating film 20 and the insulating film 28 have the same components, the following description will be made by including them in the insulating film 28.

Next, as shown in FIG. 7, a resist pattern 29 for forming the N-type semiconductor shield layer 2 is formed on the semiconductor substrate 1, and this resist pattern 29 is formed.
As a mask, by high-energy ion implantation method,
Phosphorus ions are implanted at an energy of about 1 MeV to form the N-type shield layer 2 in the deep trench 10d.
Next, as shown in FIG. 8, the resist pattern 29 is formed.
Is removed, a resist pattern 30 for forming an active region is formed by a photoengraving method, and the insulating film 28 is etched using the resist pattern 30 as a mask.
An active region 31 for forming a semiconductor device is obtained.
Next, as shown in FIG. 9, after removing the resist pattern 30, a third protective film 32 made of a SiO ₂ insulating film having a thickness of about 20 nm is formed on the active region 31. Next, a resist pattern (not shown) for forming a P-type well is formed by photolithography. At this time, the third protective film 32
Protects the active region 31 from a resist that adversely affects the semiconductor. By using this resist pattern as a mask and by implanting boron ions of about 10 ¹³ / cm ² at an energy of about 400 KeV by a high-energy implantation method, a P-type isolated well 3 as shown in FIG.
A P-type substrate well 5 is formed. Next, by the high energy injection method, for example, with an energy of about 50 KeV,
Boron ions of about 0 ¹² / cm ² are implanted, and channel doping is performed on the active regions 31 of the isolated well 3 and the substrate well 5.

Next, the resist is removed from the semiconductor substrate 1 and, as shown in FIG. 11, another resist pattern 34 is formed by photolithography so that the substrate well 5 becomes an opening, and then this resist pattern is formed. Using the mask 34 as a mask, boron ions are additionally implanted at an energy of about 50 KeV at about 10 ¹² / cm ² , and the active region 31 of the substrate well 5 is channel-doped. Next, as shown in FIG. 12, after removing the resist 34 from the semiconductor substrate 1, Si
O ₂ the third protective film 32 made of an insulating film is removed to form a gate insulating film 11 made of SiO ₂ insulating film of approximately 10nm on the active region 31, on the SiO ₂ insulating film 28 and the gate insulating film 11 About 100 nm conductor film 35, this conductor film 35
A SiO ₂ insulating film 36 having a thickness of about 100 nm is sequentially deposited thereon.

Next, as shown in FIG. 13, a resist pattern to be a gate electrode is formed on the substrate by photolithography, and the resist pattern is used as a mask for SiO ₂
After anisotropically etching the insulating film 36, the resist pattern is removed and the anisotropically etched SiO 2 is removed.
_{2 Using the} insulating film 36 as a mask, the conductor film 35 is anisotropically etched to form the gate electrode 12.

Next, as shown in FIG. 14, a resist pattern 37 for forming an N-type diffusion region is formed on the substrate 1, and the resist pattern 37 is used as a mask.
About 10 ¹⁵ / cm ² of phosphorus ions at an energy of about 30 KeV, or about 10 ¹⁵ / c at an energy of about 50 KeV
Arsenic ions of m ² are implanted to form source / drain diffusion regions 9 which are N type diffusion regions. Next, as shown in FIG. 15, after removing the resist pattern 37 on the substrate, a resist pattern 38 for forming a P-type diffusion region is formed by photolithography, and this resist pattern 38 is used as a mask. BF ₂ ions of 10 ¹⁵ / cm ² at an energy of about 20 KeV, or high concentration regions 6 and 8 which are P-type diffusion regions of about 10 ¹⁵ / cm ² at an energy of 10 KeV or less are formed. After that, the resist pattern 38 is removed, and as shown in FIG.
An insulating film 39 of 0 nm SiO ₂ is deposited.

Next, the internal wiring connection hole 1 is formed by photolithography.
A resist pattern for forming 5a is formed, and using this resist pattern as a mask, the SiO ₂ insulating film 39 is formed.
Is anisotropically etched to form the internal wiring connection hole 15a, and then the resist pattern is removed. After that, FIG.
As shown in, conductive film 4 of about 100 nm is formed on the entire surface of substrate 1.
After depositing 0, a resist pattern for forming the internal wiring 13 is formed by a photolithography method, and the conductive film 40 is anisotropically etched using the resist pattern as a mask to form the internal wiring 13. , Remove the resist,
As shown in FIG. 18, the SiO ₂ insulating film 4 is formed on the entire surface of the substrate 1.
1 is deposited and flattened by a resist etch back method or the like.

Next, as shown in FIG. 19, a resist pattern for forming the internal wiring connection hole 15b is formed, and this SiO _{2 is used} as a mask.
The insulating film 41 is anisotropically etched to form the internal wiring hole 15b.
And then removing the resist, about 100
A conductive film 42 having a thickness of nm is deposited. After that, a resist pattern for forming the lower electrode 16a of the memory capacitor 16 is formed by photolithography, and the conductive film 42 is anisotropically etched using the resist pattern as a mask.
After forming the lower electrode 16a, the resist is removed,
As shown in 0, a dielectric film 16b is formed on the upper surface and the side surface of the lower electrode 16a, and a conductor film 43 to be the upper electrode 16c is deposited on the entire surface of the substrate.

Next, a resist pattern for forming the upper electrode 16c is formed on the substrate by photolithography, and the conductor film 43 is used as a mask with the resist pattern.
Is etched to form the upper electrode 16c of the memory capacitor, the resist is removed, and the SiO ₂ insulating film 44 is formed on the entire surface of the substrate to flatten it. After that, a resist pattern for forming the wide-area wiring connection hole 18 is formed by photolithography, and the resist pattern is used as a mask to form an S
The iO ₂ insulating film 44 is anisotropically etched to form the wide area wiring connection hole 18, the resist is removed, a metal film is deposited on the entire surface of the substrate, and a resist pattern for forming the wide area wiring 17 is formed by photoengraving. Thereafter, the metal film is anisotropically etched using the resist as a mask to form the wide area wiring 17, and the resist is removed, whereby the semiconductor device according to the embodiment of FIG. 1 is formed.

In the method of manufacturing the semiconductor device described above, the shallow trench 10e is used to make use of the deep trench 1
Since 0d is formed, the deep trench 10d can be easily etched.

Example 2. A semiconductor device according to another embodiment of the present invention will be described below. This semiconductor device is
Has a plurality of P-type wells on a semiconductor substrate of
It has a twin well configuration in which the mold wells are electrically isolated from each other. 22 is a partial cross-sectional view of the semiconductor device according to the second embodiment.
3, 6, 9, 10a, 10b to 18 are exactly the same as those in the first embodiment. 50 is an N-type semiconductor substrate,
It extends to the back surface of the substrate in the lower part of the figure.

In the semiconductor device constructed as described above, the bottom surface of the P-type isolated well 3 is the N-type semiconductor substrate 50.
And electrically separated. Furthermore, the deep trench type isolation region 10b having a depth equal to or larger than the thickness of the P type isolated well 3 and having an insulator embedded in the trench reaching the N type semiconductor substrate 50 is adjacent to the adjacent P type isolated well 3. The deep trench type isolation region 10b, which is formed between them and reaches the N type semiconductor substrate 50, electrically separates the side surfaces of these P type isolated wells 3 from each other. Therefore, the adjacent P-type isolated wells 3 are electrically separated from each other, and
As described above, different potentials can be set in the P-type isolated wells 3, and the semiconductor element characteristics can be optimized.

Further, similar to the first embodiment, the same effect as the first embodiment can be obtained by forming the shallow trench type isolation region 10a in which the SiO ₂ insulator is embedded in the trench.

Example 3. Hereinafter, a semiconductor device according to still another embodiment of the present invention will be described. FIG. 23 is a partial cross-sectional view of the semiconductor device of the third embodiment. The difference from the semiconductor device of the first embodiment described above is that the deep trench isolation region 10b is formed by filling the trench with an insulator. Instead, the conductor 52 is embedded in the trench and is surrounded by the insulating film 51. The conductor 52 serves as the internal wiring 13, and one end of the internal wiring 13 is N The mold shield layer 2 and the other end are electrically connected to the wide area wiring 17.

Also in the semiconductor device configured as described above, the P-type isolated well 3 and the P-type substrate well 5 are electrically isolated by the insulator 51 formed in the deep trench isolation region 10b. Therefore, the first embodiment
It has the same effect as the effect described above.

Further, in the semiconductor device of this embodiment, the N-type shield layer 2 and the deep trench type isolation region 10b are formed.
Since the internal wiring 13 therein is connected, the N-type shield layer can be set to an arbitrary potential.

Next, a method of manufacturing the semiconductor device in this embodiment will be described below with reference to FIGS. 2 to 5A, 7 to 21 and 24 to 26. 2 to 5
The steps until forming the shallow trench type isolation region 10a and the deep trench type isolation region 10b shown in (a) are exactly the same as those described in the first embodiment. Next, FIG.
As shown in (a), the third process is performed by the LP-CVD method.
The insulating film 51 made of SiO ₂ which is the insulator of
m is deposited and this insulating film 51 is anisotropically etched by the reactive ion etching method to form the second insulating film 21.
When the insulating film 51 on the top and the bottom of the deep trench 10d is removed and the first protective film 23 on the bottom of the deep trench 10d is removed, as shown in FIG. _{2 The} insulating film 51 remains.

Next, as shown in FIG. 25A, a Si semiconductor film 52 having a high concentration of N-type impurities added thereto is deposited to a thickness of about 150 to 200 nm on the entire surface of the substrate by the CVD method to fill the deep trench 10d. . Next, as shown in FIG. 25B, after forming a resist pattern 53 for forming the internal wiring 13 by a photoengraving method, the resist pattern 53 is used as a mask to remove the Si semiconductor film 52 from the reactive ion beam. The internal wiring 13 is formed by anisotropic etching by the etching method. Then, the resist is removed, as shown in FIG. 26 (a), the HF chemical treatment for selectively etching the SiO ₂ insulating film to remove the SiO ₂ insulating film plug 25 in the shallow trench 10e,
Further, H ₃ P for selectively etching the Si ₃ N ₄ insulating film
The second insulating film 21 and the second protective film 24 are completely removed by the O ₄ chemical treatment.

Next, as shown in FIG. 26B, C
SiO ₂ formed of the first insulator on the entire surface of the substrate by the VD method
Insulating film 28 is deposited to a thickness of about 150 nm to form shallow trench 10e.
The SiO ₂ insulating film 28 is embedded in the inside to form a shallow trench type isolation region 10a. After that, the semiconductor device shown in FIG. 23 is obtained by the same manufacturing method as that shown in FIGS. 7 to 21 in the first embodiment.

[0059]

In the semiconductor device of the first invention, since the well isolation is performed by the trench type well isolation region, the isolation region for isolating the well can be made small, and high integration can be promoted. Have an effect.

Further, in the semiconductor device of the second invention, since the element isolation is performed by the trench type element isolation region formed in the first conductivity type well, the elements can be formed close to each other, so that the integration is further enhanced. It has the effect that it can be promoted.

Also, in the semiconductor device of the third invention, since the well isolation is performed by the trench type well isolation region, the isolation region for isolating the well can be made small, and the high integration can be promoted. Have.

Further, in the semiconductor device of the fourth aspect of the present invention, since the element isolation is performed by the trench type element isolation region formed in the second conductivity type well, the elements can be formed close to each other, so that higher integration is achieved. Has the effect that it becomes possible to proceed.

Further, in the semiconductor device of the fifth invention, the first well adjacent to each other by the trench type well isolation region is used.
The conductive type well is electrically isolated, and the conductor in the trench type well isolation region is electrically connected to the second conductive type buried region to set the second conductive type buried region to an arbitrary potential. It has an effect that it becomes possible to do.

Further, also in the semiconductor device of the sixth invention, since the element isolation is performed by the trench type element isolation region formed in the first conductivity type well, the elements can be formed in close proximity to each other, so that the degree of integration is further improved. It has the effect that it can be promoted.

In the method of manufacturing a semiconductor device of the seventh invention, a trench type element isolation region having an insulator filled in a shallow trench and a trench type well isolation region having an insulator filled in a deep trench are provided. Has an effect that can be efficiently formed.

In the method of manufacturing a semiconductor device according to the eighth aspect of the invention, a trench type element isolation region having an insulator filled in a shallow trench and a conductor surrounded by the insulator in a deep trench are provided. This has the effect that the buried trench type well isolation region can be efficiently formed.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing the configuration of a semiconductor device that is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a part of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 22 is a partial cross-sectional view showing the configuration of a semiconductor device that is Embodiment 2 of the present invention.

FIG. 23 is a partial cross-sectional view showing the configuration of a semiconductor device that is Embodiment 3 of the present invention.

FIG. 24 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 26 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 27 is a partial cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N-type shield layer 3 P-type isolated well 5 P-type substrate well 10a Shallow trench isolation region 10b Deep trench isolation region 10c First trench 10d Deep trench 10e Shallow trench 20 First insulating film 21 Second insulating film 23 First protective film 24 Second protective film 25 Plug 28 Insulating film 50 N-type semiconductor substrate 51 Insulator 52 Conductor

Claims (8)

[Claims] 1. A first conductivity type well formed on a first conductivity type semiconductor substrate via a trench type well isolation region, and a second conductivity formed on the entire bottom surface of at least one of the first conductivity type wells. A semiconductor device comprising a type buried region, wherein the trench type well isolation region has a depth reaching the second conductivity type buried region. 2. The semiconductor device according to claim 1, further comprising a trench type element isolation region for performing element isolation in the well of the first conductivity type well. 3. A second conductivity type well formed on a first conductivity type semiconductor substrate via a trench type well isolation region, wherein the trench type well isolation region has a depth reaching the substrate. A semiconductor device characterized by: 4. The semiconductor device according to claim 3, wherein the second conductivity type well has a trench type element isolation region for performing element isolation in the well. 5. A first conductivity type well formed on a first conductivity type semiconductor substrate through a trench type well isolation region, and a second conductivity formed on the entire bottom surface of at least one of the first conductivity type wells. And a trench-type well isolation region in which a conductor electrically isolated from the first-conductivity-type well is embedded in a trench having a depth reaching the second-conductivity-type buried region. In addition, the semiconductor device is characterized in that the conductor is electrically connected to the second conductivity type buried region. 6. The semiconductor device according to claim 5, wherein the first conductivity type well has a trench type element isolation region for performing element isolation in the well. 7. A step of forming a first insulating film made of a first insulating material on a semiconductor substrate, and further forming a second insulating film made of a second insulating material on the first insulating film, A shallow trench which becomes a trench type element isolation region by anisotropically etching the semiconductor substrate by patterning a two-layer film consisting of the first and second insulating films into a shape corresponding to both the trench type isolation regions A step of forming a first trench corresponding to the depth of the first insulating film, a first protective film made of the first insulating material on the entire surface of the semiconductor substrate, and the second insulating material on the first protective film. A step of forming a second protective film made of the above-mentioned semiconductor film, the insulating film made of the first insulating material is formed on the entire surface of the semiconductor substrate, the first trench is buried, and then the entire surface is etched back to make the first protective film. Consists of the first insulator in the trench Step of forming a plug, after forming a resist film on the entire surface of the semiconductor substrate, patterning this into a shape corresponding to a deep trench to be a trench type well isolation region, and using this as a mask to select only the first insulator The first plug and the second protective film in the first trench, which are to be deep trenches, and the first and second protective films in the trench are removed. Anisotropically etching the semiconductor substrate to form the deep trench, the resist is removed, the deep trench is covered with a resist, and only the first insulator is selectively etched to etch the first trench. A step of removing the plug remaining in the trench to form the shallow trench, and a step of selectively removing only the second insulator after removing the resist. Removing said second insulating film and the second protective film is etched,
And a step of burying the first insulator in the shallow trench and the deep trench by forming an insulating film made of the first insulator on the entire surface of the semiconductor substrate. Method. 8. A step of forming a first insulating film made of a first insulating material on a semiconductor substrate, and further forming a second insulating film made of a second insulating material on the first insulating film, A two-layer film composed of a first insulating film and a second insulating film is patterned into a shape corresponding to both the trenches, and the semiconductor substrate is anisotropically etched using this as a mask to form a shallow trench depth to be a trench type element isolation region. A step of forming a first trench corresponding to, a first protective film made of the first insulating material on the entire surface of the semiconductor substrate, and a second protective material made of the second insulating material on the first protective film. In the step of forming the second protective film, an insulating film made of the first insulator is formed on the entire surface of the semiconductor substrate, the first trench is buried, and then the entire surface is etched back to form the first trench in the first trench. Form a plug made of the first insulator In the step of forming, a resist film is formed on the entire surface of the semiconductor substrate and then patterned into a shape corresponding to a deep trench to be a trench type well isolation region, and this is used as a mask to selectively select only the first insulator. The first trench and the second protective film in the trench are removed by etching to remove the plug in the first trench that is to be the deep trench, and the semiconductor under the trench is further masked by the two-layer film. A step of anisotropically etching the substrate to form the deep trench, and after removing the resist, an insulating film made of a first insulator is formed on the entire surface of the semiconductor substrate to anisotropically form the first insulator. The first insulator on the bottom of the deep trench is removed by etching to form an insulator only on the side surface of the deep trench, and the conductor is formed on the entire surface of the semiconductor substrate. After forming a body film and burying a conductor film in a deep trench, a resist film is formed on the entire surface of the semiconductor substrate, and this is patterned into a shape corresponding to the deep trench. Etching to form a conductor surrounded by an insulator in a deep trench; after removing the resist, only the first insulator is selectively etched to remain in the first trench. Removing the plugs to form the shallow trench, and selectively etching only the second insulator to form the second insulating film and the second insulating film.
The step of removing the protective film and the step of burying the first insulator in the shallow trench by forming an insulating film made of the first insulator on the entire surface of the semiconductor substrate. Of manufacturing a semiconductor device.