JPH07264069A - Analog-digital conversion unit and signal processing system using the same - Google Patents

Abstract

(57) [Abstract] [Purpose] The first purpose is to provide an inexpensive analog-digital conversion unit that enables high-speed sampling processing, and high-speed signal processing is possible using the analog-digital conversion unit. It is a second object to provide a signal processing system as follows. [Structure] A plurality of analog-digital conversion elements (8-
1, 8-2, 8-3, 8-4) and the plurality of analog-
Digital conversion element (8-1, 8-2, 8-3, 8-4)
And a selector (18) for selecting and outputting each digital value sampled in (1) according to a predetermined order.
Further, the processing unit (14) processes each digital value output from the selector (18) by the output rate from the selector (18).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital conversion unit and a signal processing system using the same,
More specifically, the present invention relates to an analog-digital conversion unit that can perform signal conversion at high speed and a signal processing system that enables high-speed signal processing using the same.

[0002]

2. Description of the Related Art A technique for demodulating information recorded with partial response characteristics by using the maximum likelihood decoding (Viterbi decoding) is proposed in the field of optical discs as well as the improvement of the recording density of optical disc recording media such as magneto-optical discs. Has been done.
In an optical disc device (magneto-optical disc device) in which the information recorded by the partial response characteristic is demodulated by using the maximum likelihood decoding method, the reproduction signal obtained from the optical disc is sampled by an analog-digital converter, and the sampling value is sampled. The most probable (maximum likelihood) signal state transition is determined according to a predetermined algorithm, and the reproduction data is generated based on the determined signal state transition.

In a signal processing system such as a reproduction system of an optical disk device, in order to process (reproduce) data at high speed, an analog-digital converter capable of performing sampling operation in synchronization with a high speed clock signal is required. Become.
Conventionally, a flash type analog-digital converter has been developed as an analog-digital converter capable of sampling operation in synchronization with a high-speed clock signal.

[0004]

However, the flash type analog-digital converter has a large element size and consumes a large amount of power. Moreover, this flash-type analog-to-digital converter is expensive at the present time. The price of analog-to-digital converters generally increases exponentially with higher speed types. Therefore, the conventional analog-digital converter causes a cost increase when used in a device that realizes high-speed processing.

Further, even if the speed of the device is further increased in the future, the processing speed of the device is limited by the performance of the analog-digital converter. Therefore,
A first object of the present invention is to provide an inexpensive analog-digital conversion unit that enables high-speed sampling processing. A second object of the present invention is to provide a signal processing system which enables high speed signal processing by using the analog-digital conversion unit.

[0006]

A first object of the present invention is to provide a plurality of analog-to-digital conversion elements (8-) that input signals to be processed in parallel from the outside and perform sampling processing of the input signals at different timings. 1,8-2,8-3,8-
4) and the plurality of analog-digital conversion elements (8-
1, 8-2, 8-3, 8-4) are selected according to a predetermined order at a timing determined based on the timing of sampling processing in each analog-digital conversion element. It is achieved by an analog-digital conversion unit provided with an output means (18) for outputting as an output.

From the standpoint of being able to easily operate with a single external clock, the method according to claim 2 further comprises:
The plurality of analog-digital conversion elements (8-1, 8-
2, 8-3, 8-4) performs a sampling process at different timings to generate a clock for synchronization of each analog-digital conversion element based on a clock signal from the outside (11-1). , 11-2, 11
-3) is preferable.

According to a third aspect of the present invention, a synchronous clock to be supplied to each analog-digital conversion element can be easily generated.
The clock generation means (11-1,
11-2 and 11-3) preferably generate clocks having the same frequency but different phases. From the viewpoint that the sampling digital value can be easily selected with a single external clock, the output means includes the plurality of analog-digital conversion elements (8-1, 8).
Selecting means (18) for selecting each digital value sampled in (2, 8-3, 8-4) according to a control signal
And a control means (12) for generating a control signal to be supplied to the selection means (18) based on a clock generated from the single external clock by the clock generation means.

The second object mentioned above is to provide signal generating means (1, 2, 6, 7a, 7b) for outputting an analog signal to be processed.
And an analog-digital conversion unit (80, 81) for sampling analog signals from the signal generating means (1, 2, 6, 7a, 7b) at a timing determined by a timing clock, and the analog-digital conversion A processing unit (14) for processing the digital values sampled by the units (80, 81) in synchronization with a synchronization clock, and the analog-digital conversion unit (8).
0, 81) and a clock generating means (10, 19) for generating a timing clock to be supplied to the processing unit (14) and a synchronous clock to be supplied to the processing unit (14). (1,
2, 6, 7a, 7b), and a plurality of analog-digital conversion elements (8-) that perform sampling processing of the analog signal at different timings determined based on the timing clock from the clock generation means.
1, 8-2, 8-3, 8-4) and the plurality of analog-
Digital conversion element (8-1, 8-2, 8-3, 8-4)
And an output means (12, 18) for selecting and outputting each digital value sampled in 1. in accordance with a predetermined order at a timing determined based on the timing of sampling processing in each analog-digital conversion element. The signal processing system is adapted to supply the digital value output from the output means (18) to the processing unit.

An analog-digital conversion unit (80, 8) generated by the clock generation means (10, 19)
The timing clock to be supplied to 1) is supplied to the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4) as described in claim 6, for example. It should be multiple synchronous clocks. From the viewpoint of easy generation, it is preferable that the plurality of synchronous clocks have the same frequency but different phases.

From the viewpoint that a synchronous clock to be supplied to the signal processing unit and a plurality of synchronous clocks to be supplied to the analog-digital conversion element can be generated in association with each other,
The clock generating means is as described in claim 8.
Based on the synchronous clock to be supplied to the processing unit (14), the plurality of analog-digital conversion elements (8-1,
It is preferable to have means (19) for generating a plurality of synchronous clocks ((1), (2), (3), (4)) to be supplied to 8-2, 8-3, 8-4).

From the same point of view, the clock generation means may include the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4) as described in claim 9. From the plurality of synchronous clocks to be supplied, the processing unit (1
It is preferable to have a clock synthesizing means (13) for generating a synchronous clock to be supplied to 4). The output means of the analog-digital conversion unit (80, 81) is, for example, as described in claim 10, the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8). −
4) has a selecting means (18) for selecting each digital value sampled in accordance with a control signal, and the signal processing system further generates a control signal to be supplied to the selecting means (18). (12, 191, 192, 19
7) is provided.

From the standpoint that the control signal can be easily generated, the control means has the analog-digital conversion unit (80, 81) as described in claim 11.
Means (12) for generating a control signal to be supplied to the selecting means (18) based on a timing clock to be supplied to
It is preferable to have Further, from the same viewpoint, the control means includes means (191, 192, 197) for generating a control signal to be supplied to the selection means (18) based on a synchronous clock to be supplied to the signal processing unit (14). It is preferable to have.

[0014]

Operation: A plurality of analog-digital conversion elements (8-1,
8-2, 8-3, 8-4) inputs signals to be processed from the outside in parallel and performs sampling processing of the input signals at different timings. The digital values sampled by the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4) are sampled by the analog-digital conversion elements according to a predetermined order. The output means (1
8) selects and outputs. Since the digital values sampled by the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4) are output from the output means in a predetermined order, individual analog-digital conversion is performed. The output rate of the sampling value from the output means (18) can be made higher than the sampling rate of the elements (8-1, 8-2, 8-3, 8-4). Further, the signal processing unit (14) can process the sampling digital value from the output means (18) at the same rate as its output rate.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. An analog-digital conversion unit (hereinafter referred to as an A / D conversion unit) according to the present invention reproduces data recorded on an optical disc with a partial response characteristic, and demodulates a reproduction signal using a maximum likelihood decoding method. It is used in a reproducing system of a magneto-optical disk device that obtains recorded data.

The recording system of this type of magneto-optical disk device is
For example, it is configured as shown in FIG. In FIG.
Optical disk 1, optical head 2, data output unit 3,
Laser drive unit 5, travel limit modulator 4 and partial response modulation pre-reader (PR modulation precoder) 12
Is provided. The run length limiting modulator 4 modulates the data from the data output unit 3 according to, for example, the 1/7 modulation rule. Data from the running length limit modulator 4 is PR
It is further modulated by the precoder 12 according to a characteristic corresponding to the partial response class 1, for example. As shown in FIG. 3, the PR precoder 12 has a delay element (D) 15 in which a delay time for one data is set, and output data is input data via the delay element (D) 15. Have been returned to. In this case, the PR modulation precoder 12 performs [1 / (1 + D)] mod2 modulation.
The data obtained by [1 / (1 + D)] mod2 modulation is supplied to the laser drive unit 5, and the laser drive unit 5 outputs a laser drive signal corresponding to the input data. A laser drive signal (recording signal) from the laser drive unit 5 is supplied to the laser diode (LD) of the optical head 2,
Data is recorded on the optical disc 1 by a laser diode (LD) driven by the laser drive signal. The conversion of the data from the data output unit 3 into a laser drive signal (recording signal) is performed by, for example, FIG.
It is shown in (1), (2), (3) and (4).

A reproducing system for reproducing data from the optical disc 1 on which data is recorded by the recording system as described above is constructed as shown in FIG. 1, for example. In FIG. 1, an optical disc 1, an optical head 2, an amplifier 6,
Equalizer 7a, low-pass filter 7b, A / D conversion circuit 8
0, a binarization circuit 9, a PLL circuit 10, a clock synthesis circuit 13, a maximum likelihood decoder 14, and a demodulator 16 are provided. A reproduction signal corresponding to the recorded data is obtained from the optical disc 1 through the optical head 2, and the reproduction signal is amplified by the amplifier 6 and then equalizer 7a and low-pass filter 7b.
The waveform is shaped by being processed in. The waveform-shaped reproduced signal is converted into a digital value by the A / D conversion circuit 80, and the reproduced signal is sampled.
The sample value obtained by the A / D conversion circuit 80 is supplied to the maximum likelihood decoder 14, and the maximum likelihood decoder 14 generates the maximum likelihood decoded signal based on the sample value of the reproduced signal. Binarization circuit 9
Converts the reproduced signal whose waveform has been shaped by the equalizer 7a and the low-pass filter 7b into a binarized signal using, for example, a certain slice level. Then, the PLL circuit 10 generates a timing clock signal synchronized with the reproduction signal based on the binarized signal. The A / D conversion circuit 80 is a PLL
The maximum likelihood decoder 14 operates in synchronization with the timing clock signal from the circuit 10, and the maximum likelihood decoder 14 operates in synchronization with the combined clock from the clock combining circuit 13. The states of each signal from the generation of the reproduced signal to the maximum likelihood decoding process are shown in, for example, FIGS. 4 (5), (6), (7) and (8). Then, the signal obtained by the maximum likelihood decoding process is further demodulated by the demodulator 16 (1/7 demodulation), and final data is obtained.

In FIG. 4, the characteristic converted from the recorded signal (4) to the reproduced signal (6) (the signal whose waveform is shaped by the equalizer 7a and the low-pass filter 7b) corresponds to the characteristic of the partial response class 1. ing. Therefore, the reproduction signal (6) corresponds to the signal obtained by (1 + D) converting the recording signal (4). This recording signal (4) is changed to (1
The + D) converted signal can take three values as shown by the broken line in FIG. Now, let that value correspond to -2, 0, +2. Then, the maximum likelihood decoder 14 generates a recording signal from the sampling digital value of the reproduction signal (6) by the A / D conversion circuit 80. When maximum likelihood decoder 14 detects probable data from an input signal, the most probable data transition path leading to the detected data is determined, and the data on that path is determined as maximum likelihood decoded signal data to be obtained. . For example, when the maximum likelihood decoder 14 processes the reproduction signal shown in FIG. 4 (6), a data transition path as shown in FIG. 4 (8) is obtained, and based on this data transition path, FIG. The same maximum likelihood decoded signal as that of the recorded signal as shown in is generated. The detailed configuration of the maximum likelihood decoder 14 is proposed by the present inventor in Japanese Patent Application No. 5-333355.

In FIG. 1, the A / D conversion circuit 80 has four
A / D conversion elements 8-1, 8-2, 8-3 and 8-4
, Delay elements 11-1, 11-2 and 11-3, a selector 18, and a selection signal generation circuit 12. The reproduced signal waveform-shaped by the equalizer 7a and the low-pass filter 7b is parallel to four A / D conversion elements 8-1, 8-
2, 8-3 and 8-4. PLL circuit 1
The frequency of the timing clock signal 0 generated based on the binarized signal from the binarization circuit 9 is a quarter of the clock frequency corresponding to the originally expected processing speed. Hereinafter, the timing clock signal output from the PLL circuit 10 is referred to as 1/4 clock.

A quarter clock from the PLL circuit 10 is A
Is supplied to the A / D conversion element 8-1 and the A / D conversion element 8-
1 performs sampling processing of the reproduction signal in synchronization with 1/4 clock. Also, the 1/4 clock is the delay circuit 11-1.
The phase is delayed by 1/4 cycle by the delay circuit 11
-1 outputs the first delay 1/4 clock. This first delay 1/4 clock is supplied to the A / D conversion element 8-2, and the A / D conversion element 8-2 performs sampling processing of the reproduction signal in synchronization with the first delay 1/4 clock. To do. The phase of the first delayed 1/4 clock from the delay circuit 11-1 is further delayed by 1/4 cycle by the delay circuit 11-2, and the delay circuit 11-2 outputs the second delayed 1/4 clock. Output. The second delay 1/4 clock is supplied to the A / D conversion element 8-3, and the A / D conversion element 8-3 performs sampling processing of the reproduction signal in synchronization with the second delay 1/4 clock. To do. Furthermore, the second delay 1/4 clock from the delay circuit 11-2 is 1 /
The phase is delayed by 4 cycles, and the delay circuit 11-3 outputs the third delayed 1/4 clock. This third delay 1 /
4 clocks are supplied to the A / D conversion element 8-4,
The D conversion element 8-4 performs sampling processing of the reproduction signal in synchronization with the third delay 1/4 clock.

The phase relationship among the 1/4 clock, the first delay 1/4 clock, the second delay 1/4 clock and the third delay 1/4 clock is as shown in FIG. In FIG. 5, the value of the circled point of the reproduced signal is sampled at the rising edge of the 1/4 clock, and the value of the triangled point that is delayed by ¼ cycle from the circled point of the reproduced signal is the first delay. Sampling is performed at the rising edge of 1/4 clock. Also, 1 from the point marked with a triangle in the playback signal
/ 4 is the value of the point marked with □ that is delayed by 4 cycles and the second delay is 1 /
Sampled at the rising edge of 4 clocks,
The value of the point of x, which is delayed by ¼ cycle from the point of □ of the reproduction signal, is sampled at the rising edge of the third delayed 1/4 clock.

The digital values sampled by the A / D conversion elements 8-1, 8-2, 8-3 and 8-4 are the selector 1
8 and the selector 18 supplies a selection signal S1, which will be described later.
One of the digital values to be input is selected according to the state of S2. The digital value selected by the selector 18 is supplied to the maximum likelihood decoder 14. 1/4 clock whose phase is shifted by 1/4 cycle, first delay 1/4 clock,
The second delay 1/4 clock and the third delay 1/4 clock are supplied to the clock synthesis circuit 13. In the clock synthesizing circuit 13, each clock is made into a short pulse by the monostable multivibrator, and the synthesized clock signal is generated by taking the logical sum of the pulse signals. The frequency of this combined clock signal is four times the frequency of the 1/4 clock, which corresponds to the originally expected processing speed. Then, the combined clock output from the clock combining circuit 13 is supplied to the maximum likelihood decoder 14, and the maximum likelihood decoder 14 synchronizes with the combined clock signal and the A / D conversion circuit 80.
The digital value from is taken in and the processing as described above is performed.

In the selector 18, as shown in FIG. 6A, the digital value (a) sampled by the A / D conversion element 8-1 and the digital value (a) sampled by the A / D conversion element 8-2 are sampled. The digital value (b), the digital value (c) sampled by the A / D conversion element 8-3 and the digital value (d) sampled by the A / D conversion element 8-4 are input in parallel. As shown in FIG. 6B, 2-bit selection signals S1 and S representing the four states A, B, C and D.
Any of the digital values input by 2 is selected. That is, in state A (S1, S2 = 1, 1), the digital value (a) is selected, and state B (S1, S2 = 1, 0)
Then, the digital value (b) is selected, and the state C (S1, S
At 2 = 0,0), the digital value (c) is selected, and at state D (S1, S2 = 0,1), the digital value (d) is selected.

The selection signal generation circuit 12 generates the 2-bit selection signals S1 and S2 based on the 1/4 clock and the first to third delay 1/4 clocks. In the selection signal generation circuit 12, as shown in FIG. 7, an inverted signal (* 0) of 1/4 clock (0) (* X represents a signal obtained by inverting the signal X. The same applies to the following.) S1 is obtained by the logical relationship (AND) of the delay 1/4 clock (2), and the inverted signal (* 3) of the first delay 1/4 clock (1) and the third delay 1/4 clock (3) The logical relation (AND) of S1 is obtained. By such selection signals S1 and S2, the state of the selector 18 is cyclically switched in the order of A, B, C and D. As a result, from the selector 18,
In the reproduction signal shown in FIG. 5, a digital value (a) sampled at a circle point, a digital value (b) sampled at a triangle point, a digital value (c) sampled at a square point, x Digital values (d) sampled at the mark points are sequentially and cyclically output at predetermined intervals to.

This interval to corresponds to the cycle of the combined clock. As a result, the selector 18 outputs the sampling value in synchronization with the synthesized clock having a frequency corresponding to the originally expected processing speed. That is, this A /
The D conversion circuit 80 operates as if synchronized with the synthetic clock. FIG. 8 shows an example of another reproducing system of the magneto-optical disk device.

In FIG. 8, this reproducing system is the same as that shown in FIG. 1, including the optical disc 1, the optical head 2, the amplifier 6, the equalizer 7a, the low pass filter 7b, the binarization circuit 9, the PLL circuit 10, and the maximum. It has a likelihood decoder 14 and a demodulator 16. The reproduction system further includes an A / D conversion circuit 81 and a clock generation circuit 19 having different structures from those shown in FIG. 1, and the digital value of the reproduction signal sampled by the A / D conversion circuit 81. Are supplied to the maximum likelihood decoder 14. The PLL circuit 10 also generates a timing clock based on the binarized signal synchronized with the reproduction signal from the binarization circuit 9. This timing clock has a frequency corresponding to the originally expected processing speed. The timing clock from the PLL circuit 10 is the clock generation circuit 1
9 is being supplied.

The A / D conversion circuit 81 is the A / D converter shown in FIG.
Similar to the conversion circuit 80, four A / D conversion elements 8-1,
It has 8-2, 8-3 and 8-4 and a selector 18. The selector 18 has four A / D conversion elements 8-1, 8 according to the selection signals S1, S2, as in the case shown in FIG.
Any one of the digital values sampled at -2, 8-3, and 8-4 is selected (see FIG. 6B). Based on the timing clock from the PLL circuit 10, the clock generation circuit 19 has four clocks (1), (2), which have a frequency that is ¼ the frequency of the timing clock.
(3) and (4) are generated. Clock (1) is A / D
The clock (2) is supplied to the A / D conversion element 8 by the conversion element 8-1.
-2, the clock (3) is supplied to the A / D conversion element 8-3, and the clock (4) is supplied to the A / D conversion element 8-4. Each A / D conversion element performs sampling processing of the reproduction signal waveform-shaped by the equalizer 7a and the low-pass filter 7b in synchronization with the supplied clock. The sampling digital value of the reproduction signal selected by the selector 18 is supplied to the maximum likelihood decoder 14, and a recording signal is obtained by the maximum likelihood decoding process as in the above-described embodiment. Then, the output signal from the maximum likelihood decoder 14 is further demodulated by the demodulator 16
To obtain the final data.

The clock generation circuit 19 is constructed, for example, as shown in FIG. 9, the clock generation circuit 19 is basically configured as a binary 2-bit counter and has flip-flops 191, 192 and 197 and AND gates 193, 194, 195 and 196. The flip-flop 191 divides the timing clock from the PLL circuit 10 by two and outputs a signal Q1 and an inverted signal * Q1. The flip-flop 192 further divides the signal Q1 from the flip-flop 191 into two and outputs a signal Q2 and an inverted signal * Q2. AND gate 1
A signal 93 receives the signals Q1 and Q2 and outputs their logical relationship as a clock (1). And gate 194
Inputs the inverted signal * Q1 and the signal Q2 and outputs their logical relationship as a clock (2). And gate 19
The signal 5 receives the signal Q1 and the inverted signal * Q2 and outputs their logical relationship as a clock (3). AND gate 1
96 inputs the inverted signal * Q1 and the inverted signal * Q2, and outputs their logical relationship as a clock (4). Also,
The flip-flop 197 further divides the inverted signal * Q1 from the flip-flop 191 by two and outputs a signal Q3.
The signal Q2 from the flip-flop 192 and the signal Q3 from the flip-flop 197 are output from the clock generation circuit 19 as selection signals S1 and S2.

The clock generation circuit 19 having the above configuration is shown in FIG.
It operates according to the timing chart shown in FIG. Figure 10
In the above, the clocks (1), (2), (3), and (4) rise every four cycles of the timing clock, and the rising timings thereof are deviated by one cycle of the timing clock. That is, the phase of the timing clock is shifted by one cycle of the timing clock.
It will be decomposed into two clocks (1), (2), (3) and (4). And four clocks (1),
The relationship between the rising timings of (2), (3) and (4) and the phases of the selection signals S1 and S2 is 1/4 shown in FIG.
The relationship between the rising timings of the clock and the first to third delay 1/4 clocks and the phases of the selection signals S1 and S2 is the same. Therefore, as in the embodiment shown in FIG.
The selector 18 includes A / D conversion elements 8-1, 8-2, 8-3.
And cyclically select the sampling digital values at 8-4. As a result, the selected sampling digital value is supplied to the maximum likelihood decoder 14 in synchronization with the timing clock generated by the PLL circuit 10.

In each of the above embodiments, an example in which four A / D conversion elements are used is shown, but the present invention is not limited to this, and a plurality of A / D conversion elements can be similarly applied. Further, although the reproducing system of the magneto-optical disk device (optical disk device) having the maximum likelihood decoder has been described, the present invention is not limited to this and can be applied to other signal processing systems.

[0031]

As described above, according to the present invention,
A plurality of analog-digital conversion elements (8-1, 8-2,
Since the digital values sampled in 8-3, 8-4) are output from the output means (18) in a predetermined order, the individual analog-digital conversion elements (8-1, 8-
The output rate of the sampling value from the output means (18) can be made larger than the sampling rate of 2, 8-3, 8-4). Therefore, a high-speed analog-digital conversion unit can be configured by using a plurality of inexpensive low-speed analog-digital conversion elements. Further, by using such an analog-digital conversion unit, it is possible to obtain a signal processing system capable of high-speed signal processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a reproduction system of an optical disc according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a recording system of an optical disc.

FIG. 3 is a block diagram showing a configuration of a PR precoder.

FIG. 4 is a timing chart showing operations of a recording system and a reproducing system of the optical disc.

FIG. 5 is a timing chart showing the relationship between clocks and sampling timings of reproduced signals.

FIG. 6 is a diagram showing a relationship between a selection signal and a signal selected by a selector.

FIG. 7 is a timing chart showing the operation of the A / D conversion unit.

FIG. 8 is a block diagram showing a reproducing system of an optical disc in another example of the present invention.

9 is a block diagram showing a configuration of a clock generation circuit shown in FIG.

10 is a timing chart showing the operation of the clock generation circuit shown in FIG.

[Explanation of symbols]

 1 Optical Disc 2 Optical Head 3 Data Output Unit 4 Travel Length Limiting Modulator 5 Laser Driving Unit 6 Amplifier 7a Equalizer 7b Low Pass Filter 80, 81 A / D Conversion Circuit 8-1 to 8-4 A / D Conversion Element 9 Binary Circuit 10 PLL circuit 11-1 to 11-3 delay circuit 12 selection signal generation circuit 13 clock synthesis circuit 14 maximum likelihood decoder 15 PR precoder 16 demodulator

Claims (13)

[Claims] 1. A plurality of analog-to-digital conversion elements (8-1, 8) which input signals to be processed from the outside in parallel and sample the input signals at different timings.
-2,8-3,8-4) and the plurality of analog-digital conversion elements (8-1,8-
Output that selects and outputs each digital value sampled in (2, 8-3, 8-4) according to a predetermined order at a timing determined based on the timing of sampling processing in each analog-digital conversion element An analog-to-digital conversion unit comprising means (18). 2. The analog-to-digital conversion unit according to claim 1, wherein the plurality of analog-to-digital conversion elements (8-1, 8-2, 8-3, 8-4) are sampled at different timings. Clock generation means (1) for generating a synchronization clock for each analog-to-digital conversion element for performing processing based on an external clock signal.
An analog-digital conversion unit including 1-1, 11-2, 11-3). 3. The analog-digital conversion unit according to claim 2, wherein the clock generation means (11-1, 11-2, 11-3).
Is an analog-to-digital conversion unit that generates clocks with the same frequency but different phases. 4. The analog-to-digital conversion unit according to claim 2 or 3, wherein the output means is the plurality of analog-to-digital conversion elements (8-1, 8-2, 8-3, 8-4). Selection means (18) for selecting each sampled digital value according to a control signal, and control means (12) for generating a control signal to be supplied to the selection means (18) based on the clock generated by the clock generation means. ) And an analog-to-digital conversion unit. 5. Signal generation means (1, 2, 6, 7a, 7b) for outputting analog signals to be processed, and sampling processing of analog signals from the signal generation means (1, 2, 6, 7a, 7b) And an analog-digital conversion unit (80, 81) for performing the process at a timing determined by a timing clock, and a process for processing a digital value sampled by the analog-digital conversion unit (80, 81) in synchronization with a synchronization clock. The unit (14), the timing clock to be supplied to the analog-digital conversion unit (80, 81), and the processing unit (1).
4) and a clock generation means (10, 19) for generating a synchronous clock to be supplied to the analog-digital conversion unit. , And a plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4) for sampling the analog signal at different timings determined based on the timing clock from the clock generation means. ), And the plurality of analog-digital conversion elements (8-1, 8-
Output that selects and outputs each digital value sampled in (2, 8-3, 8-4) according to a predetermined order at a timing determined based on the timing of sampling processing in each analog-digital conversion element Means (12, 1
8) and a signal processing system which supplies the digital value output from the output means (18) to the processing unit. 6. The signal processing system according to claim 5, wherein the timing clock to be supplied to the analog-digital conversion unit (80, 81) generated by the clock generation means (10, 19) is the plurality of timing clocks. A signal processing system which is a plurality of synchronous clocks to be supplied to analog-digital conversion elements (8-1, 8-2, 8-3, 8-4). 7. The signal processing system according to claim 6, wherein the plurality of synchronous clocks have the same frequency but different phases. 8. The signal processing system according to claim 6 or 7, wherein said clock generation means is based on a synchronous clock to be supplied to said processing unit (14). , 8-2, 8-3, 8-4), a plurality of synchronous clocks ((1), (2),
A signal processing system having means (19) for generating (3) and (4). 9. The signal processing system according to claim 6, wherein the clock generation means supplies the plurality of analog-digital conversion elements (8-1, 8-2, 8-3, 8-4). Clock synthesizing means (1) for generating a synchronous clock to be supplied to the processing unit (14) from a plurality of synchronous clocks to be processed.
A signal processing system having 3). 10. The signal processing system according to claim 5, wherein the output means of the analog-digital conversion unit (80, 81) is the plurality of analog-digital converters.
Digital conversion element (8-1, 8-2, 8-3, 8-4)
The signal processing system further includes a selection unit (18) for selecting each digital value sampled in step S1 according to a control signal, and the signal processing system further generates a control signal to be supplied to the selection unit (18). , 191, 192, 197)
Signal processing system equipped with. 11. The signal processing system according to claim 10, wherein said control means comprises said analog-digital conversion unit (8).
0, 81), and a signal processing system having means (12) for generating a control signal to be supplied to the selecting means (18) based on a timing clock to be supplied. 12. The signal processing system according to claim 10, wherein the control means generates a control signal to be supplied to the selection means (18) based on a synchronous clock to be supplied to the signal processing unit (14). Means (191, 192, 197)
A signal processing system having. 13. The signal processing system according to claim 5, wherein the signal processing system reproduces the data from an optical disc (1) on which data is recorded according to a rule corresponding to a partial response characteristic. In the system, the signal generating means (1, 2, 6, 7a, 7b) is a circuit for obtaining a reproduction signal from the optical disc (1), and the processing unit (14) is an analog-digital conversion unit (80). , 81) based on the sampled digital value of the reproduced signal from
A signal processing system that is a maximum likelihood decoder that obtains reproduced data from the determined transition path of the data.