JPH07262125A - Information processor - Google Patents

Abstract

PURPOSE:To access the memory or the overall area or a map in a first address bus from a bus master connected to a second address bus with respect to the information processor where first and second address busses are provided and the bus width of the second address bus is narrower than that of the first address bus. CONSTITUTION:An upper address register 8 is provided which outputs the value, which is preliminarily written from a bus master 5 to the address signal which is given to an internal address bus 3 and is not included in direction control of an address buffer 7, in accordance with the indication of a bus arbiter 6 at the time of access from the bus master 5 to an internal memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a first address bus and a second address bus, and a bus width of a second address bus is smaller than a bus width of a first address bus. Regarding a processing device.

[0002]

2. Description of the Related Art A conventional information processing apparatus of this type has a configuration shown in FIG. As shown in FIG. 5, a conventional information processing apparatus includes a central processing unit (hereinafter referred to as “CPU”) 1
And a first memory (hereinafter referred to as “internal memory”) 2,
A first address bus (hereinafter referred to as "internal address bus") 3, a second address bus (hereinafter referred to as "external address bus") 4, a bus mask 5, and a bus arbiter 6
1, an address buffer 7, a fixed value output unit 10, and a second memory (hereinafter referred to as “external memory”) 9.

A data read operation or a data write operation performed by the CPU 1 with respect to the internal memory 2 or the external memory 9 is performed as follows. Hereinafter, a data read operation or a data write operation is called an access.

The CPU 1 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 grants the bus occupation right of the CPU 1, the bus arbiter 6 notifies the CPU 1, the fixed value output unit 10 and the address buffer 7 of that fact. The CPU 1 outputs the address of the memory to be accessed to the internal address bus 3.

The address buffer 7 is an internal address bus 3
A part of the signal is output to the external address bus 4. For example, when the bus width of the internal address bus 3 is 32 from bit 31 to bit 0 and the bus width of the external address bus 4 is 24 from bit 23 to bit 0, the internal address bus 3 is This means that 24 bits from bit 23 to bit 0 are output to the external address bus 4. The internal memory 2 monitors the internal address bus 3, and the external memory 9 monitors the external address bus 4. When both recognize that they are addresses assigned on the map, the access from the CPU 1 is executed. .

The access that the bus master 5 makes to the internal memory 2 or the external memory 9 is performed as follows.

The bus master 5 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 permits the bus mastership of the bus master 5, the bus arbiter 6 notifies the bus master 5, the fixed value output unit 10 and the address buffer 7 of that fact. The bus master 5 outputs the address of the memory to be accessed to the external address bus 4.

The address buffer 7 is an external address bus 4
Signal is output to a part of the internal address bus 3. For example, in the case where the bus width of the internal address bus 3 is 32 from bit 31 to bit 0 and the bus width of the external address bus 4 is 24 from bit 23 to bit 0, 24 of the external address bus 4 is used. Book the internal address bus 3
It means that the data is output from bit 23 of 24 to bit 0 of 24 lines.

At the same time, the fixed value output unit 10 outputs a fixed logical value, for example, 0 to 8 bits from bit 31 to bit 23 of the internal address bus 3. The state of each bit of the internal address bus 3 at this time is shown in the column of the prior art example of FIG. The internal memory 2 monitors the internal address bus 3 and the external memory 9 monitors the external address bus 4. When both recognize that they are assigned addresses on the map, the access from the bus master 5 is executed. It

[0010]

However, in the conventional information processing apparatus, when the bus master accesses the internal memory, an address signal which the internal address bus has and is not included in the direction control of the address buffer is addressed. Since the fixed value output unit outputs a fixed logical value according to the instruction of the bus arbiter, the area in which the bus master can access the internal memory is limited to only a part of the map in the internal address bus. was there.

It is an object of the present invention to provide an information processing apparatus which enables a bus master to access the internal memory of all areas of a map on an internal address bus.

[0012]

In order to solve the above problems, the present invention provides a central processing unit and an address having the same address bus width as the address bus of the address bus connected to the central processing unit and held by the central processing unit. A first address bus having a bus width, a first memory connected to the first address bus, and a second address bus width smaller than the address bus width of the first address bus. Address bus, a bus master connected to the second address bus and having the same address bus width as the address bus width having the second address bus, the central processing unit and the bus master acquisition request of the bus master. A bus arbiter that arbitrates and is connected between the first address bus and the second address bus and corresponds to the bus width of the second address bus. An address buffer for controlling the direction of an address according to an instruction of the bus arbiter, and a value written in advance by the bus master for an address signal which the first first address bus has and which is not included in the direction control of the address buffer. Is output according to the instruction of the bus arbiter.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

An example in which an external memory is not provided will be described as a first example, and an example in which an external memory is provided will be described later as a second example.

In the present embodiment, the case where the bus width of the internal address bus is 32 from bit 31 to bit 0 and the external address bus width is 24 from bit 23 to bit 0 will be described.

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing a state of the internal address bus when the bus master acquires the bus occupation right in the embodiment of the present invention and the conventional information processing apparatus. FIG. 3 is a diagram showing the relationship between the set value of the upper address register and the map on the internal address bus in the embodiment of the present invention. FIG. 4 is a diagram showing the relationship between the map on the external address bus and the allocation area of the external memory in the embodiment of the present invention.

In FIG. 1, when the CPU 1 has the internal memory 2 or the external memory 9, the access to the external memory 9 is similar to the operation in the conventional information processing apparatus.

That is, the CPU 1 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 grants the bus occupation right of the CPU 1, the bus arbiter 6 notifies the CPU 1, the upper address register 8 and the address buffer 7 to that effect.
The CPU 1 outputs the address of the memory to be accessed to the internal address bus 3.

The address buffer 7 is an internal address bus 3
A part of the signal is output to the external address bus 4. This means that 24 bits from bit 23 to bit 0 of the internal address bus 3 are output to the external address bus 4. The internal memory 2 monitors the internal address bus 3, and when the external memory 9 exists, the external memory 9 monitors the external address bus 4, and when both recognize that they are addresses assigned on the map, the CPU 1 Access is executed.

Further, in FIG. 1, the bus master 5 accesses the internal memory 2 in the following manner.

First, from each bit of the address signal except for the address signal output to the internal address bus 3 by the address buffer 7 among the addresses assigned to the internal memory 2 to be accessed on the map, from bit 31 An 8-bit value up to bit 24 is set in the upper address register 8. At this time, the relationship between the value set in the upper address register 8 and the map on the internal address bus 3 is shown in FIG. In the example shown in FIG. 3, the 4-gigabyte space is divided into 256 areas in units of 16 mega, and the addresses of all areas of the 4-gigabyte space can be designated by the setting value of the upper address register 8.

Next, the bus master 5 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 grants the bus mastership right of the bus master 5, the bus arbiter 6 notifies the bus master 5, the upper address register 8 and the address buffer 7 to that effect. The bus master 5 outputs 24 bits from bit 23 to bit 0 to the external address bus 4 among the addresses of the memory to be accessed. The address buffer 7 transfers the signal of the external address bus 4 to the bit 23 of the internal address bus 3.
To 24 lines of bit 0.

At the same time, the upper address register 8 outputs a preset value for eight bits 31 to 23 of the internal address bus 3. The state of each bit of the internal address bus 3 at this time is shown in the column of the embodiment in the case where there is no external memory in FIG. The internal memory 2 monitors the internal address bus 3 and recognizes that it is an assigned address, and the access from the bus master 5 is executed.

The above is the first embodiment when the external memory 9 is not provided. If there is an external memory 9 connected to the external address bus 4 in this embodiment, when the bus master 5 accesses the internal memory 2, it is possible that the bus master 5 collides with the area of the external memory 9 on the external address bus 4. Next, as an information processing apparatus for avoiding this collision, a second embodiment in which the external memory 9 is provided will be described.

In the second embodiment, the bus master 5 is a bus master that outputs a fixed value to one or more address signals of the external address bus 4, and the address buffer 7 is from the external address bus 4 to the internal address bus. When outputting the address signal to 3, the bus master 5 is an address buffer that outputs an address signal excluding the address signal that outputs a fixed value among the address signals that the external address bus 4 has.

In the example shown in FIG. 4, the external memory is allocated to an area of the 16-megabyte space in the external address bus 4 in which the bit 23 has the logical value 0 and the bit 22 has the logical value 1.

When the bus master 5 accesses the internal memory 2, first, in addition to the 8 bits from bit 31 to bit 24, a total of 10 bits of bit 23 and bit 22 is set in the upper address register 8.

Next, the bus master 5 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 grants the bus master 5 the exclusive right to the bus, the bus arbiter 6 notifies the bus master 5 of that fact.
The upper address register 8 and the address buffer 7 are notified. The bus master 5 outputs 22 bits from bit 21 to bit 0 to the external address bus 4 among the addresses of the memory to be accessed.

At this time, a logical value indicating an area other than the area to which the external memory 9 is allocated on the external address bus 4 is output to the bit 23 and the bit 22.
This outputs, for example, a logical value 1 to bit 23 and bit 2
It means that the logical value 0 is output to 2. The address buffer 7 outputs 22 bits 21 to 0 of the signal of the external address bus 4 to 22 bits 21 to 0 of the internal address bus 3. At the same time, the upper address register 8 outputs a preset value for 10 bits from bit 31 to bit 22 of the internal address bus 3. The state of each bit of the internal address bus 3 at this time is shown in the column of the embodiment in the case where the external memory 9 is provided in FIG. The internal memory 2 monitors the internal address bus 3 and recognizes that it is an address assigned on the map, and the access from the bus master 5 is executed.

When the bus master 5 accesses the external memory 9, the bit 3 is first stored in the upper address register 8.
A logical value 0 is set in 8 bits from 1 to 24, a logical value 0 is set in bit 23, and a logical value 1 is set in bit 22.

Next, the bus master 5 requests the bus arbiter 6 to acquire the bus exclusive right. When the bus arbiter 6 grants the bus master 5 the exclusive right to the bus, the bus arbiter 6 notifies the bus master 5 of that fact.
The upper address register 8 and the address buffer 7 are notified. The bus master 5 outputs the address of the memory to be accessed to the external address bus 4. At this time, a logical value indicating an area to which the external memory 9 is allocated on the external address bus 4 is output to the bit 23 and the bit 22. This means that a logical value 0 is output to bit 23 and a logical value 1 is output to bit 22. The external memory 9 monitors the external address bus 4, recognizes that it is an address assigned on the upper map, and the access from the bus master 5 is executed.

[0032]

According to the information processing apparatus of the present invention, when a bus master accesses an internal memory, a value written in advance from the bus master for an address signal which the internal address bus has and which is not included in the direction control of the address buffer. Is provided in accordance with the instruction of the bus arbiter, the internal memory of the entire area of the map on the internal address bus can be accessed from the bus master.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a state of an internal address bus when a bus master in an information processing apparatus according to an embodiment of the present invention and a conventional information processing apparatus acquire a bus exclusive right.

FIG. 3 is a diagram showing a relationship between a set value of a high-order address register and a map in an internal address bus in the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a map on an external address bus and an allocation area of an external memory in the embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional information processing apparatus.

[Explanation of symbols]

 1 Central Processing Unit (CPU) 2 Internal Memory 3 Internal Address Bus 4 External Address Bus 5 Bus Master 6 Bus Arbiter 7 Address Buffer 8 Upper Address Register 9 External Memory 10 Fixed Value Output Section

Claims (2)

[Claims] 1. A central processing unit, a first address bus connected to the central processing unit, having a same address bus width as the address bus width of the address bus of the central processing unit, and the first address bus. Connected to the first memory, a second address bus having an address bus width smaller than the address bus width of the first address bus, and the second address bus connected to the second address bus. A bus master having the same address bus width as that of the address bus, a bus arbiter for arbitrating the central processing unit and the bus master's bus ownership acquisition request, the first address bus and the second address. The direction control of the address corresponding to the bus width of the second address bus connected between the buses is performed according to the instruction of the bus arbiter. Address buffer, and an upper address for outputting a value written in advance from the bus master to an address signal which the first first address bus has and which is not included in the direction control of the address buffer, according to an instruction of the bus arbiter. An information processing device comprising: a register. 2. The information processing apparatus according to claim 1, further comprising a second memory connected to the second address bus, wherein the bus master is connected to the second address bus. A fixed value is output to one or more address signals of the address bus, and the address buffer outputs the second address when the address signal is output from the second address bus to the first address bus. An information processing apparatus, wherein the bus master outputs an address signal other than an address signal that outputs a fixed value among the address signals of the bus.