JPH0725829Y2 - Liquid crystal drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a liquid crystal driving device for driving a liquid crystal display panel in which common electrodes and segment electrodes are arranged in a matrix.

[Prior Art and Problems to be Solved] In recent years, liquid crystal display panels have been used in portable small-sized television receivers and the like. In this type of liquid crystal display panel, common electrodes and segment electrodes are arranged in a matrix. Has become. The drive circuit for driving the liquid crystal display panel is generally constructed as shown in FIG. FIG. 4 shows a drive circuit for the common electrode. In the figure, 11a and 11b are power supply lines, and the selection voltages V0 and V4 are alternately applied to one line 11a for each frame and the non-selection voltage V2 is applied to the other line 11b. The selection voltages V0 and V4 have different polarities centered on the V0 voltage as shown in the waveform diagram of FIG. Then, the power supply lines 11a, 11b, the analog switch 12a, which is provided corresponding to each common electrode of the liquid crystal display panel,
One end of 12b, ..., 13a, 13b, ... Is connected. Then, the analog switches 12a, 12b, ... And corresponding switches
The other ends of 13a, 13b, ... Are commonly connected, and common signals X1, X2 ,. Further, 14 is a shift register, which is composed of flip-flops 15a, 15b, ... With the number of stages corresponding to the number of common electrodes, and the vertical timing signal synchronized with the vertical synchronizing signal is input to the input terminal 1 of the first stage flip-flop 15a. It Further, the clock pulse φn synchronized with the horizontal synchronizing signal is applied to the clock terminals CK of all the flip-flops 15a, 15b, ... The shift register 14 reads the vertical timing signal SR by the clock pulse φn and sequentially shifts it. The output signals of the flip-flops 15a, 15b, ... Of the shift register 14 are
.. are respectively input to the gates of the analog switches 12a, 12b, ... And are also input to the gates of the analog switches 13a, 13b ,.

In the above configuration, if the vertical timing signal SR is input to the shift register 14 in the frame where the V0 voltage is being applied to the power supply line 11a, the vertical timing signal SR is sent to the first-stage flip-flop 15a by the clock pulse φn. When read, the output signal becomes "1", analog switch 12a turns on, and analog switch 1
3a turns off. Therefore, as the common signal X1, the V0 voltage (selection voltage) applied to the power supply line 11a is output as shown in FIG. At this time, in the shift register 14, since the outputs of the flip-flops 15b, 15c, ... Are held in the “0” signal state, the analog switches 12b, 12
... are off, and the analog switches 13b, 13c, ... are on. Therefore, the other common signals X2, X3, ... Are held at the level of the non-selection voltage V2. Then, when the "1" signal held in the flip-flop 15a is shifted to the next-stage flip-flop 15b by the next clock pulse φn, the output signal becomes "1", and the analog switch
12b turns on and the analog switch 13b turns off.
As a result, the V0 voltage applied to the power supply line 11a is output as the common signal X2. At this time, the output signal of the flip-flop 15a becomes "0", so that the analog switch 12a is turned off and the analog switch 13a is turned on, and the common signal X1 is supplied to the power line 11b at V2.
It becomes the voltage level. Similarly, shift register
Common signals X1, X2, ... Are sequentially output in accordance with the shift operation of 14. Then, in the next frame, the voltage applied to the power supply line 11a is switched from V0 to V4 voltage, so that the V4 voltage is output as the common signals X1, X2, .... On the other hand, as shown in FIG. 5, V2 is used for the segment electrode of the liquid crystal display panel.
The voltages V1 and V3 whose polarities are inverted with respect to the voltage are given as the segment signal Ym according to the gradation level of the display image. The liquid crystal display panel is driven for display by the voltage difference between the segment signal Ym and the common signal Xn.

As described above, in the conventional method, the common signals X1, X2, ...
The voltage becomes V0, V4 voltage when selected, and V2 voltage when not selected. The maximum on / off ratio of the applied voltage that determines the contrast is unilaterally determined by the duty (ratio of selection time and non-selection time), and the number of common electrodes However, if the duty increases and the duty decreases, it is not possible to obtain an image with good contrast.

On the other hand, if the non-selected outputs of the common signals X1, X2, ... are made to have a high impedance instead of the V2 voltage, due to the capacitive property of the liquid crystal, the segment voltage is pulled to the common potential, and the actual value during this period becomes a pixel. It lowers and the contrast is dramatically improved. However, in this case, there is a problem that a tailing phenomenon occurs due to a decrease in effective value due to pixels having no correlation with the image, and the image quality is significantly deteriorated.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal driving device that can obtain good contrast without lowering image quality even when the duty is low.

[Means and Actions for Solving Problems] The present invention relates to a liquid crystal driving device for driving a liquid crystal display panel in which a plurality of common electrodes and segment electrodes are arranged in a matrix, and when the common electrodes are not selected, The non-selection voltage, and when selected, the selection voltage is output and sequentially driven, and when the selection voltage is applied to the common electrode, the output of the non-selection voltage is prohibited for a period of one or several back plates before and after the selection, and the high impedance state is achieved. It is designed to be held at.

As described above, when the selection voltage is output to the common electrode, only one or several back plate periods before and after that,
By prohibiting the output of the non-selection voltage and setting it in a high impedance state, the effective voltage applied during this period can be lowered, and the contrast can be increased without changing the duty.

[Embodiment of the Invention] Hereinafter, a case where the present invention is applied to a liquid crystal television receiver will be described with reference to the drawings. First, the overall schematic configuration will be described with reference to FIG. In the figure, 21 is an antenna, and the radio waves received by this antenna 21 are
Entered in. The tuner 22 selects a desired channel from the received radio waves, converts it into an intermediate frequency signal, and inputs it to the TV linear circuit 23. The TV linear circuit 23 amplifies the intermediate frequency signal from the tuner 22, extracts the video signal and outputs the video signal to the A / D conversion circuit 24, and separates the sync signal from the video signal to the sync control circuit 25. Output. The synchronization control circuit 25 generates various timing signals based on the synchronization signal supplied from the TV niria circuit 23, and supplies the timing signals to the A / D conversion circuit 24, the segment electrode drive circuit 26 and the common electrode drive circuit 27. The A / D conversion circuit 24 converts the video signal sent from the RV linear circuit 23 into digital data of, for example, 3 to 4 bits in synchronization with the timing signal from the synchronization control circuit 25, and the segment electrode drive circuit 26 Output to. Further, the segment electrode drive circuit 26 is supplied with VI and V3 voltages from the liquid crystal drive voltage generation circuit 28. The segment electrode drive circuit 26 creates a gradation signal according to the digital data provided from the A / D conversion circuit 24, selects V1 and V3 electrodes according to the gradation signal, and selects the liquid crystal display panel 2
Drive 9 segment electrodes. Further, from the liquid crystal drive voltage generation circuit 28 to the common electrode drive circuit 27, V0, V4,
V2 voltage is applied. The common electrode drive circuit 27 creates common signals X1 to Xn composed of a selection voltage and a non-selection voltage based on the vertical timing signal SR and the clock pulse φn from the synchronization control circuit 25, as will be described later in detail, and displays the liquid crystal display. The common electrodes of the panel 29 are sequentially driven. in this case,
When outputting the selection voltage, the common electrode drive circuit 27 prohibits the output of the non-selection voltage and puts it in a high impedance state for only one or several backplate periods before and after the selection voltage.

Next, details of the common electrode drive circuit 27 will be described with reference to FIG. The same parts as those of the common electrode drive circuit shown in FIG. 4 are designated by the same reference numerals and the detailed description thereof will be omitted. The common electrode drive circuit 27 in this embodiment is
The NOR circuits 31a, 31b, ... Are provided corresponding to the flip-flops 15a, 15b, ... Of the shift register 14, and the output signals of the respective flip-flops 15a, 15b, ... Are input to the gates of the analog switches 12a, 12b ,. , Via the NOR circuits 31a, 31b, ... To the gates of the analog switches 13a, 13b ,.
In this case, the output signals of the flip-flops 15a, 15b, ... Are input not only to the corresponding NOR circuits 31a, 31b ,. For example flip-flop 15
The output signal of a is input to the NOR circuits 31a and 31b, and the output signal of the flip-flop 15b is input to the NOR circuits 31a, 31b and 31c.
Other than that, as in the case of FIG. 4, the analog switches 12a, 12b, ... Are connected to the power supply line 11a, and the analog switches 13a, 13b ,. The liquid crystal drive voltage generation circuit 28 alternately supplies V0 and V4 voltages to the power supply line 11a on a frame-by-frame basis, and the power supply line 11b receives
2 Voltage is applied. The analog switches 12a, 12b, ...
Keeps the output terminal in a high-impedance state when turned off.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. Now, in a frame in which the V0 voltage is applied to the power supply line 11a, if the vertical timing signal SR is applied from the synchronization control circuit 25 to the shift register 14, the vertical timing signal SR is clock pulse φ.
It is read by the flip-flop 15a in synchronization with n. As a result, the output signal of the flip-flop 15a becomes "1",
When the analog switch 12a turns on, the output signal of the NOR circuit 31a becomes "0", and the analog switch 13a turns off. Therefore, as shown in FIG. 3, the V0 voltage applied to the power supply line 11a is output from the analog switch 12a as the common signal X1. Also, the above flip-flop 15
Since the "1" signal output from a is input to the NOR circuit 31b, the output signal becomes "0", and the analog switch 13b
Turns off. Furthermore, at this point, flip-flop 15b
Since the output signal of is 0, the analog switch 12b is off. As described above, the analog switches 12b and 13b are both turned off during the period of one back plate in which the V0 voltage is output as the common signal X1, so that the common signal X2 is in a high impedance state as shown by the broken line in FIG. Becomes Further, at this time, since the output signals of the flip-flops 15b, 15c, ... Of the shift register 14 are all held at “0”, the analog switches 12c ,.
The analog switches 13c, ... Are off. Therefore, all the other common signals X3, ... Are held at the non-selected V2 voltage level.

Then, when the "1" signal held in the flip-flop 15a of the shift register 14 is shifted to the flip-flop 15b by the next clock pulse φn, the output signal of the flip-flop 15a is "0" and the output signal of the flip-flop 15b is changed. The output signal becomes "1". Therefore, the analog switch 12b is turned on, and the output of the NOR circuit 31b becomes "0", and the analog switch 13b is turned off. Therefore, the power supply line 11a
The V0 voltage applied to the analog switch 12b is output as the common signal X2. Also flip flops
When the "1" signal is output from 15b, the outputs of the NOR circuits 31a and 31c become "0", and the analog switches 13a and 13c are turned off. As described above, both the analog switches 12a and 13a in the front stage and the analog switches 12c and 13c in the rear stage are turned off and the common signals X1 and X3 are in a high impedance state during one back plate during which the selection voltage V0 is output as the common signal X2. Becomes

Similarly, the common signals X1, X2, ... Are sequentially output in accordance with the shift operation of the shift register 14, but the selection voltage V0
Is held in the high impedance state for one back plate period before and after the output of
Held in. In the next frame, the V4 voltage is applied to the power supply line 11a as the selection voltage. However, the same operation as in the case of the V0 voltage is performed, and the common electrode to be selectively scanned is high only for one back plate period before and after that. It is kept in the impedance state.

When the common electrodes are sequentially scanned as described above, the high impedance state is maintained for one back plate period before and after the common electrodes, whereby the effective voltage during this period is lowered due to the capacitive property of the liquid crystal, and the contrast ratio is improved. At this time, a tailing phenomenon occurs, but since it is a very short time, its influence is very small and deterioration of image quality can be suppressed.

In the above embodiment, the common signal is held in the high impedance state for one back plate period before and after the selection voltage is output. However, the period of holding the high impedance state is not noticeable. It may be set within the range of one to several backplate periods.

[Effects of the Invention] As described in detail above, according to the present invention, when a liquid crystal display panel in which common electrodes and segment electrodes are arranged in a matrix is driven, a selection voltage is applied to a common signal that drives the common electrodes. Since the high impedance state is maintained for one to several backplate periods before and after output, the applied effective voltage can be reduced during this period without degrading image quality, and good contrast can be obtained without changing the duty. It is what is done.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 3 show an embodiment of the present invention. FIG. 1 is a block diagram showing a schematic configuration of the whole, and FIG. 2 is a common electrode in FIG. FIG. 3 is a block diagram showing the configuration of a drive circuit, FIG. 3 is a timing chart for explaining the operation of the same embodiment, FIG. 4 is a block diagram showing the configuration of a conventional common electrode drive circuit, and FIG. 5 is FIG. 3 is a timing chart for explaining the operation of FIG. 11a, 11b ... Power line, 12a, 12b, ..., 13a, 13b, ... Analog switch, 14 ... Shift register, 15a, 15b, ... Flip-flop, 31a, 31b ,.

Claims (1)

[Scope of utility model registration request] 1. A liquid crystal display panel in which a plurality of common electrodes and segment electrodes are arranged in a matrix, segment electrode driving means for displaying and driving the segment electrodes according to display data, and non-selection with respect to the common electrodes. A common electrode driving unit that outputs a non-selection voltage at times and a selection voltage at the time of selection and sequentially drives it, and when a selection voltage is applied to the common electrode by this driving unit, the non-selection voltage is applied for a period of one or several back plates before and after that. A liquid crystal drive device, which is provided with a state holding means for prohibiting the output of the device and holding it in a high impedance state.