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JPH07254774A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH07254774A
JPH07254774A JP6245895A JP6245895A JPH07254774A JP H07254774 A JPH07254774 A JP H07254774A JP 6245895 A JP6245895 A JP 6245895A JP 6245895 A JP6245895 A JP 6245895A JP H07254774 A JPH07254774 A JP H07254774A
Authority
JP
Japan
Prior art keywords
solder
printed wiring
wiring board
conductor lands
lands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6245895A
Other languages
Japanese (ja)
Other versions
JP2568813B2 (en
Inventor
Fumio Miyasaka
文男 宮坂
Shinji Kasahara
慎二 笠原
Shigeru Anzai
茂 安斉
Ryoichi Kawamura
僚一 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7062458A priority Critical patent/JP2568813B2/en
Publication of JPH07254774A publication Critical patent/JPH07254774A/en
Application granted granted Critical
Publication of JP2568813B2 publication Critical patent/JP2568813B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To reinforce the electrical and mechanical coupling between lead terminals and conductor lands while avoiding the solder bridging in the soldering step. CONSTITUTION:Within the printed wiring board, the first soldering resistor layer 16 is formed on the lower surface of an insulating substrate while taper protrusions 16a are point symmetrically formed on the through holes 15 respectively extending in the two orthogonal directions to the arrayal direction of the conductor lands 12 on the other hand, almost semispherical notch parts 16c, 16d are symmetrically formed along the arrayal direction of the conductor lands 12 centered on the through holes 15 as if running on to the conductor lands 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路部品のよう
に、極めて小さいピッチで連続したリード端子が設けら
れた電子部品をはんだ付けするのに適したプリント配線
板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board suitable for soldering an electronic component such as an integrated circuit component provided with continuous lead terminals at an extremely small pitch.

【0002】[0002]

【従来の技術】一般に、この種のプリント配線板は、電
子部品のリード端子を挿入するための貫通孔の回りに導
箔等により導電パターンを形成し、電子部品のリード端
子が貫通孔に挿入された状態で導電パターンの面を溶融
はんだ層や噴流はんだ層に浸漬することにより、はんだ
でリード端子と導電パターンの間を電気的、機械的に結
合するように構成されている。
2. Description of the Related Art Generally, in this type of printed wiring board, a conductive pattern is formed by a conductive foil or the like around a through hole for inserting a lead terminal of an electronic component, and the lead terminal of the electronic component is inserted into the through hole. The surface of the conductive pattern is immersed in the molten solder layer or the jet solder layer in this state, so that the lead terminals and the conductive pattern are electrically and mechanically coupled by solder.

【0003】第1の従来のプリント配線板としては、隣
接するランドの相隣接し対向する部分の表面にシルク印
刷層が形成されていた(実開昭62−26074号公
報)。図4、図5に示すように、シルク印刷層2,2は
ランド並設方向に沿って180度の間隔をおいて設けら
れ、ランド1の導電箔面を覆っている。電子部品Aのリ
ード端子aをプリント配線板3の端子孔4に挿入し、次
いでその導電パターン面をはんだ槽内の溶融はんだに浸
すと、はんだ5がランド1の表面にのみ付着し、リード
端子aがはんだ付け固定されて、電子部品Aがプリント
配線板3に装着される。その際、ランド1に付着するは
んだの量は、シルク印刷層2,2の形成により、リード
端子aを確実にはんだ付け固定するに必要かつ十分な最
小限に減らされる。しかも、はんだディップのとき、相
隣接する部分からレジスト6の層を通して隣接するラン
ドに乗り越えようとするはんだ5は、このレジスト6な
らびにシルク印刷層2で阻止される。したがって、隣接
ランド1,1間にはんだのブリッジが生じにくくなる。
In the first conventional printed wiring board, a silk printing layer was formed on the surface of the adjacent and opposing portions of the adjacent lands (Japanese Utility Model Laid-Open No. 62-26074). As shown in FIGS. 4 and 5, the silk-printed layers 2 and 2 are provided at intervals of 180 degrees along the land juxtaposition direction and cover the conductive foil surface of the land 1. When the lead terminal a of the electronic component A is inserted into the terminal hole 4 of the printed wiring board 3 and then its conductive pattern surface is immersed in the molten solder in the solder bath, the solder 5 adheres only to the surface of the land 1 and the lead terminal a a is fixed by soldering, and the electronic component A is mounted on the printed wiring board 3. At this time, the amount of solder that adheres to the land 1 is reduced to the minimum necessary and sufficient for securely soldering and fixing the lead terminal a by forming the silk printing layers 2 and 2. Moreover, at the time of solder dipping, the solder 5 that tries to get over the adjacent land from the adjacent portions through the layer of the resist 6 is blocked by the resist 6 and the silk printing layer 2. Therefore, a solder bridge is less likely to occur between the adjacent lands 1 and 1.

【0004】第2の従来のプリント配線板としては、一
列に並んだランド方向に対し垂直な方向に、貫通孔を中
心として点対称で鋭角の先細り突出部を有するはんだ付
抵抗層が形成されていた(特開昭61−140193号
公報)。図6、図7に示すように、2層のはんだ付抵抗
層7,8を施し、はんだ付ランド部9の形状をランドの
並ぶ方向に対して垂直方向に鋭角の先細り突出部10が
あるために、電子部品Bのはんだ付時に、はんだはその
突出部10に引っ張られるのではんだブリッジの発生は
著しく低減することになる。
In the second conventional printed wiring board, a soldering resistance layer having a pointed symmetrical acute pointed protruding portion centered on the through hole is formed in a direction perpendicular to the land direction arranged in a line. (Japanese Patent Laid-Open No. 61-140193). As shown in FIGS. 6 and 7, two layers of soldering resistance layers 7 and 8 are applied, and the shape of the soldering land portion 9 has a tapered protruding portion 10 having an acute angle in a direction perpendicular to the direction in which the lands are arranged. In addition, when the electronic component B is soldered, the solder is pulled by the protruding portion 10, so that the occurrence of solder bridges is significantly reduced.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、第1の
従来のプリント配線板では、円形のランドの相隣接し対
向する部分の表面に、シルク印刷層を形成しているが、
シルク印刷層により中央部のランドの面積が小さくな
り、はんだ付けをした際に、はんだは表面張力により大
部分がリード端子、または中央部以外の面積が広い部分
のランドに引き寄せられ、中央部のランドははんだ量が
少なくなり、リード端子、ランド間の半田不足となりや
すく、トンネル現象が発生したり、リード端子、ランド
間の結合力が非常に弱くなるという問題があった。
However, in the first conventional printed wiring board, the silk printing layer is formed on the surfaces of the adjacent and opposing portions of the circular lands.
The silk-printed layer reduces the area of the land in the center, and when soldering, most of the solder is attracted to the lead terminals or the land with a large area other than the center due to surface tension. There is a problem that the amount of solder in the land is small, the solder between the lead terminal and the land is likely to be insufficient, a tunnel phenomenon occurs, and the bonding force between the lead terminal and the land becomes extremely weak.

【0006】また、ランドが円形であり、はんだがラン
ドの配列方向に広がるので、シルク印刷層をランド内に
大きく突き出さなければ、はんだブリッジを防止するこ
とができず、そのため貫通孔を小さくして少しでもラン
ドの面積を大きくするようにしていた。よって、図5が
示すように、リード端子の直径と貫通孔の直径が一致し
ており、リード端子を貫通孔に挿入するのに非常に手間
がかかり、このようなプリント配線板に電子部品を実装
するのは作業性が悪いという問題があった。
Further, since the land is circular and the solder spreads in the arrangement direction of the land, the solder bridging cannot be prevented unless the silk printing layer is largely projected into the land, and therefore the through hole is made small. I tried to increase the land area even a little. Therefore, as shown in FIG. 5, the diameter of the lead terminal and the diameter of the through hole are the same, and it takes a lot of time and effort to insert the lead terminal into the through hole. There was a problem that the workability was poor to implement.

【0007】そして、第2の従来のプリント配線板で
は、先細り形状を有する導体ランドであり、導体ランド
を配列した直交方向では溶融はんだが引っ張られるが、
導体ランドの配列方向では、隣合う導体ランド間が接近
しているので、はんだブリッジが発生してしまうという
問題があった。
In the second conventional printed wiring board, the conductor land has a tapered shape, and the molten solder is pulled in the orthogonal direction in which the conductor lands are arranged.
In the arrangement direction of the conductor lands, since the adjacent conductor lands are close to each other, there is a problem that a solder bridge occurs.

【0008】本発明はこのような従来の問題を解決する
ものであり、リード端子、導体ランド間の電気的、機械
的結合を強くすると共に、隣合うランド間のはんだブリ
ッジを防止することが出来る優れたプリント配線板を提
供することを目的とするものである。
The present invention solves such a conventional problem, and can strengthen the electrical and mechanical coupling between the lead terminal and the conductive land and prevent the solder bridge between the adjacent lands. It is intended to provide an excellent printed wiring board.

【0009】[0009]

【課題を解決するための手段】本発明は上記目的を達成
するために、複数の貫通孔が電子部品のリード端子の配
列方向に沿って形成された絶縁基板と、この絶縁基板の
下面の前記貫通孔の回りにそれぞれ形成された複数の導
体ランドと、先細り突起部が前記導体ランドの配列方向
と直交する2方向にそれぞれ伸びるように前記貫通孔を
中心として点対称に形成され、かつ、略半円形状の切り
欠き部が前記導体ランドの配列方向に沿って前記貫通孔
を中心として対称に形成されたはんだ付け抵抗層とを備
えたものである。
In order to achieve the above object, the present invention provides an insulating substrate in which a plurality of through holes are formed along the arrangement direction of the lead terminals of the electronic component, and the lower surface of the insulating substrate. A plurality of conductor lands each formed around the through hole, and tapered projections are formed point-symmetrically about the through hole so as to extend in two directions orthogonal to the arrangement direction of the conductor lands, and substantially. A semi-circular cutout portion is provided with a soldering resistance layer symmetrically formed around the through hole along the arrangement direction of the conductor lands.

【0010】[0010]

【作用】したがって本発明によれば、はんだ付けした場
合に、先細り突起部が溶融はんだを引っ張り、切り欠き
部がこの引っ張りを助長するので、隣合うランド間のは
んだブリッジを防止すると共に、中央部のランド面積は
大きいので、リード端子、導体ランド間の電気的、機械
的結合を強くする。
According to the present invention, therefore, when soldering, the tapered protrusions pull the molten solder and the notches facilitate this pulling, so that solder bridges between adjacent lands are prevented and the central portion is prevented. Has a large land area, it strengthens the electrical and mechanical coupling between the lead terminal and the conductor land.

【0011】[0011]

【実施例】以下、図面を参照して本発明の実施例を説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0012】図1は本発明のプリント配線板の一実施例
を示す要部平面図、図2は本発明のプリント配線板の要
部側面断面図、図3は本発明と従来のプリント配線板を
比較した説明図である。
FIG. 1 is a plan view of an essential part showing an embodiment of the printed wiring board of the present invention, FIG. 2 is a side sectional view of the essential part of the printed wiring board of the present invention, and FIG. It is explanatory drawing which compared.

【0013】図1、図2において、11は合成樹脂の積
層板等により形成された絶縁基板、12は絶縁基板11
の下面の貫通孔の回りにそれぞれ貫通孔15の配列方向
と直交方向に長くなるように長円形で形成された導体ラ
ンド、15は電子部品13のリード端子14を挿入する
ために、リード端子14の配列方向に沿って形成された
複数の貫通孔である。
In FIGS. 1 and 2, 11 is an insulating substrate formed of a synthetic resin laminated plate or the like, and 12 is an insulating substrate 11.
Conductor lands formed in an oval shape so as to be long in the direction orthogonal to the array direction of the through holes 15 around the through holes on the lower surface of the lead terminal 15 for inserting the lead terminal 14 of the electronic component 13. Is a plurality of through holes formed along the arrangement direction of.

【0014】16はソルダレジスタにより、絶縁基板1
1の下面に形成されると共に、先細り突起部16a、1
6bが導体ランド12の配列方向と直交する2方向にそ
れぞれ伸びるように貫通孔15を中心として点対称に形
成され、かつ、略半円形状の切り欠き部16c、16d
が導体ランド12の配列方向に沿って貫通孔15を中心
として対称で、かつ導体ランド12に乗り上げるように
形成された第1はんだ付け抵抗層である。
Reference numeral 16 denotes a solder resistor, which is an insulating substrate 1.
1 is formed on the lower surface of the taper 1 and has tapered projections 16a, 1
The notch portions 16c and 16d each having a substantially semicircular shape are formed in point symmetry with the through hole 15 as a center so that 6b extends in two directions orthogonal to the arrangement direction of the conductor lands 12.
Is a first soldering resistance layer formed so as to be symmetrical with respect to the through hole 15 along the arrangement direction of the conductor lands 12 and to ride on the conductor lands 12.

【0015】なお、一実施例として1.78mmピッチ間
隔の電子部品を使用する場合、この第1はんだ付け抵抗
層16は、10〜20μの厚さで、先細り突起部16
a、16bの間の距離が2.5mm、切り欠き部16c、
16dの直径が0.2mm、切り欠き部16c、16dの
距離が1.4mm、貫通孔の直径が0.8mmになるように
形成される。
When an electronic component having a pitch of 1.78 mm is used as an example, the first soldering resistance layer 16 has a thickness of 10 to 20 .mu.
The distance between a and 16b is 2.5 mm, the notch 16c,
The diameter of 16d is 0.2 mm, the distance between the notches 16c and 16d is 1.4 mm, and the diameter of the through hole is 0.8 mm.

【0016】17は、絶縁基板11の第1はんだ付け抵
抗層16上で、導体ランド12の回りに形成された第2
はんだ付け抵抗層であり、第2はんだ付け抵抗層17
は、第1はんだ付け抵抗層16と同じ大きさ、形状の先
細り突起部17a、17bと、切り欠き部17c、17
dが形成される。
Reference numeral 17 denotes a second solder layer formed around the conductor land 12 on the first soldering resistance layer 16 of the insulating substrate 11.
The second soldering resistance layer 17 is a soldering resistance layer.
Are tapered protrusions 17a and 17b having the same size and shape as the first soldering resistance layer 16 and cutouts 17c and 17b.
d is formed.

【0017】これら第1はんだ付け抵抗層16、第2は
んだ付け抵抗層17は、シルク印刷で形成しても良い。
The first soldering resistance layer 16 and the second soldering resistance layer 17 may be formed by silk printing.

【0018】次に、上記実施例のプリント配線板に電子
部品をはんだ付けする場合についての動作を説明する。
Next, the operation of soldering an electronic component to the printed wiring board of the above embodiment will be described.

【0019】図1、図2において、電子部品13のリー
ド端子14が貫通孔15に挿入された状態で溶融はんだ
槽や噴流はんだ槽上で搬送され、導体ランド12が形成
された下面がはんだ槽内に入ると、リード端子14と導
体ランド12がはんだSにより電気的、機械的に結合さ
れる。
In FIGS. 1 and 2, the lead terminals 14 of the electronic component 13 are conveyed in a molten solder bath or a jet solder bath with the lead terminals 14 inserted into the through holes 15, and the lower surface on which the conductor land 12 is formed is the solder bath. Once inside, the lead terminals 14 and the conductor lands 12 are electrically and mechanically coupled by the solder S.

【0020】この場合、プリント配線板の下面がはんだ
槽内に入れられて導体ランド12の配列方向又はその直
交方向に搬送されると、第1はんだ付け抵抗層16の先
細り突起部16a、16bと、第2はんだ付け抵抗層1
7の先細り突起部17a,17bがはんだSを先細り突
起部方向に引っ張り、また、切り欠き部16c、16
d、17c、17dがはんだSの先細り突起部方向への
引っ張りを助長して、隣合う導体ランド12間のはんだ
Sが切れるようになり、隣接する導体ランド12間に
は、はんだSが付着すること(はんだブリッジ)を防止
することができる。
In this case, when the lower surface of the printed wiring board is put in the solder bath and conveyed in the arrangement direction of the conductor lands 12 or in the direction orthogonal thereto, the taper protrusions 16a and 16b of the first soldering resistance layer 16 are formed. , Second soldering resistance layer 1
7. The tapered protrusions 17a and 17b of 7 pull the solder S toward the tapered protrusions, and the notches 16c and 16
d, 17c, and 17d promote the pulling of the solder S toward the tapered protrusion, so that the solder S between the adjacent conductor lands 12 is broken, and the solder S adheres between the adjacent conductor lands 12. (Solder bridge) can be prevented.

【0021】また、切り欠き部16c、16d、17
c、17dを設けても中央部の導体ランド12の面積は
大きいので、第1の従来例のように、はんだ付けをした
際に、貫通孔に挿入したリード端子に大部分のはんだが
のり、ランドの一部にしかはんだがのらないことによる
トンネル現象を防止でき、リード端子14、導体ランド
12間の電気的、機械的結合を強くすることができる。
Further, the notches 16c, 16d, 17
Even if c and 17d are provided, since the area of the conductor land 12 in the central portion is large, most of the solder is spread on the lead terminals inserted into the through holes when soldering as in the first conventional example. It is possible to prevent the tunnel phenomenon due to the solder being applied only to a part of the land, and to strengthen the electrical and mechanical coupling between the lead terminal 14 and the conductor land 12.

【0022】図3は、図1、図2に示す上記実施例と、
図6、図7に示す第2の従来例において実験したはんだ
ブリッジの発生件数を示す説明図である。
FIG. 3 shows the above embodiment shown in FIGS. 1 and 2.
FIG. 8 is an explanatory diagram showing the number of occurrences of solder bridges tested in the second conventional example shown in FIGS. 6 and 7.

【0023】この実験例では、電子部品として1.78
mmのピッチ間隔であって64端子のDIP形LSI(端
子間が62個)をそれぞれ実装した20枚のプリント配
線板(導体ランド間の実験総数が1240個)を用い
て、それぞれ導体ランドの配列方向とその直交方向にそ
れぞれ搬送し、はんだ温度が248℃、コンベアスピー
ド(プリント配線板の搬送速度)が1m/分、はんだ浸
漬幅が50mm、はんだ浸漬時間が3秒で、フローソルダ
リング法によりはんだ付けを行った。
In this experimental example, the electronic component is 1.78.
Arrangement of conductor lands using 20 printed wiring boards (the total number of experiments between conductor lands is 1240) each mounted with a DIP type LSI of 64 terminals with a pitch interval of mm (62 between terminals). Direction and its orthogonal direction, solder temperature is 248 ℃, conveyor speed (conveyance speed of printed wiring board) is 1m / min, solder dipping width is 50mm, solder dipping time is 3 seconds, by flow soldering method. Soldering was done.

【0024】図3に示すように、プリント配線板を導体
ランドの配列方向に搬送した場合には、はんだブリッジ
の発生率を「0」にすることができ、他方、導体ランド
の配列方向の直交方向に搬送した場合は、はんだブリッ
ジの発生率を第2の従来例に比べて約1/6に低減する
ことができた。
As shown in FIG. 3, when the printed wiring board is conveyed in the arrangement direction of the conductor lands, the generation rate of solder bridges can be made "0", while the arrangement direction of the conductor lands is orthogonal. When it was conveyed in the direction, the rate of occurrence of solder bridges could be reduced to about 1/6 that of the second conventional example.

【0025】なお、上記実施例では、片面プリント基板
の場合について説明したが、両面プリント基板に適用す
ることができることは勿論である。
In the above embodiment, the case of a single-sided printed circuit board was described, but it goes without saying that it can be applied to a double-sided printed circuit board.

【0026】[0026]

【発明の効果】本発明は上記実施例より明らかなよう
に、先細り突起部が導体ランドの配列方向と直交する2
方向にそれぞれ伸びるように貫通孔を中心として点対称
に形成され、かつ、略半円形状の切り欠き部が導体ラン
ドの配列方向に沿って貫通孔を中心として対称に形成さ
れたはんだ付け抵抗層とを備えたので、はんだ付けした
場合に、先細り突起部が溶融はんだを引っ張り、切り欠
き部がこの引っ張りを助長して、隣合うランド間のはん
だが切れるようになるので、リード端子、導体ランド間
の電気的、機械的結合は強くなると共に、隣接する導体
ランド間のはんだブリッジを防止することができるとい
う効果を有する。
According to the present invention, as is apparent from the above-mentioned embodiment, the tapering protrusions are orthogonal to the arrangement direction of the conductor lands.
The soldering resistance layer is formed symmetrically about the through hole so as to extend in each direction, and the substantially semicircular notch is formed symmetrically about the through hole along the arrangement direction of the conductor lands. Since, when soldering, the tapered protrusion pulls the molten solder, and the notch facilitates this pull, and the solder between adjacent lands is cut off. This has the effect of strengthening the electrical and mechanical coupling between them and preventing solder bridges between adjacent conductor lands.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のプリント配線板の一実施例を示す要部
平面図
FIG. 1 is a plan view of an essential part showing an embodiment of a printed wiring board according to the present invention.

【図2】同実施例のプリント配線板の要部側面断面図FIG. 2 is a side sectional view of a main part of the printed wiring board according to the embodiment.

【図3】本発明と従来例のプリント配線板を比較した説
明図
FIG. 3 is an explanatory diagram comparing the present invention with a conventional printed wiring board.

【図4】第1の従来例のプリント配線板を示す要部平面
FIG. 4 is a plan view of a main part showing a printed wiring board of a first conventional example.

【図5】同従来例のプリント配線板の要部側面断面図FIG. 5 is a side sectional view of a main part of the printed wiring board of the conventional example.

【図6】第2の従来例のプリント配線板を示す要部平面
FIG. 6 is a plan view of an essential part showing a printed wiring board of a second conventional example.

【図7】同従来例のプリント配線板の要部側面断面図FIG. 7 is a side sectional view of a main part of the printed wiring board of the conventional example.

【符号の説明】[Explanation of symbols]

11 絶縁基板 12 導体ランド 13 電子部品 14 リード端子 15 貫通孔 16 第1はんだ付け抵抗層 17 第2はんだ付け抵抗層 16a、16b、17a、17b 先細り突起部 16c、16d、17c、17d 切り欠き部 11 Insulating Substrate 12 Conductor Land 13 Electronic Component 14 Lead Terminal 15 Through Hole 16 First Soldering Resistance Layer 17 Second Soldering Resistance Layer 16a, 16b, 17a, 17b Tapered Protrusion 16c, 16d, 17c, 17d Notch

───────────────────────────────────────────────────── フロントページの続き (72)発明者 川村 僚一 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryoichi Kawamura 4-3-1, Tsunashima-higashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】複数の貫通孔が電子部品のリード端子の配
列方向に沿って形成された絶縁基板と、この絶縁基板の
下面の前記貫通孔の回りにそれぞれ形成された複数の導
体ランドと、先細り突起部が前記導体ランドの配列方向
と直交する2方向にそれぞれ伸びるように前記貫通孔を
中心として点対称に形成され、かつ、略半円形状の切り
欠き部が前記導体ランドの配列方向に沿って前記貫通孔
を中心として対称に形成されたはんだ付け抵抗層とを備
えたプリント配線板。
1. An insulating substrate having a plurality of through holes formed along an arrangement direction of lead terminals of an electronic component, and a plurality of conductor lands formed around the through holes on a lower surface of the insulating substrate, respectively. The tapered projections are formed point-symmetrically with respect to the through holes so as to extend in two directions orthogonal to the arrangement direction of the conductor lands, and substantially semicircular cutout portions are formed in the arrangement direction of the conductor lands. A printed wiring board having a soldering resistance layer symmetrically formed around the through hole.
【請求項2】はんだ付け抵抗層がシルク印刷により形成
されていることを特徴とする請求項1記載のプリント配
線板。
2. The printed wiring board according to claim 1, wherein the soldering resistance layer is formed by silk printing.
JP7062458A 1995-03-22 1995-03-22 Printed wiring board Expired - Fee Related JP2568813B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7062458A JP2568813B2 (en) 1995-03-22 1995-03-22 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7062458A JP2568813B2 (en) 1995-03-22 1995-03-22 Printed wiring board

Publications (2)

Publication Number Publication Date
JPH07254774A true JPH07254774A (en) 1995-10-03
JP2568813B2 JP2568813B2 (en) 1997-01-08

Family

ID=13200790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7062458A Expired - Fee Related JP2568813B2 (en) 1995-03-22 1995-03-22 Printed wiring board

Country Status (1)

Country Link
JP (1) JP2568813B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0989789A2 (en) * 1998-09-21 2000-03-29 Mitsubishi Denki Kabushiki Kaisha Printed wiring board and manufacturing method thereof
EP1708551A1 (en) * 2005-03-29 2006-10-04 Mitsumi Electric Co., Ltd. Land structure, printed wiring board, and electronic device
JP2011100912A (en) * 2009-11-09 2011-05-19 Mitsubishi Electric Corp Mounting structure of power semiconductor module on printed wiring board
DE102012105439A1 (en) 2011-06-24 2012-12-27 Fanuc Corporation Printed wiring board (PWB) with pads

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117816A (en) * 1983-11-29 1985-06-25 Mitsubishi Electric Corp Delay circuit of power supply control signal
JPS61140193A (en) * 1984-12-13 1986-06-27 松下電器産業株式会社 Printed wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117816A (en) * 1983-11-29 1985-06-25 Mitsubishi Electric Corp Delay circuit of power supply control signal
JPS61140193A (en) * 1984-12-13 1986-06-27 松下電器産業株式会社 Printed wiring board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0989789A2 (en) * 1998-09-21 2000-03-29 Mitsubishi Denki Kabushiki Kaisha Printed wiring board and manufacturing method thereof
EP0989789A3 (en) * 1998-09-21 2001-06-13 Mitsubishi Denki Kabushiki Kaisha Printed wiring board and manufacturing method thereof
US6383603B1 (en) 1998-09-21 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Printed wiring board and manufacturing method thereof
EP1708551A1 (en) * 2005-03-29 2006-10-04 Mitsumi Electric Co., Ltd. Land structure, printed wiring board, and electronic device
US7488898B2 (en) 2005-03-29 2009-02-10 Mitsumi Electric Co., Ltd. Land structure, printed wiring board, and electronic device
JP2011100912A (en) * 2009-11-09 2011-05-19 Mitsubishi Electric Corp Mounting structure of power semiconductor module on printed wiring board
DE102012105439A1 (en) 2011-06-24 2012-12-27 Fanuc Corporation Printed wiring board (PWB) with pads
US8847083B2 (en) 2011-06-24 2014-09-30 Fanuc Corporation Printed wiring board (PWB) with lands

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