JPH07254292A - Non-volatile memory and microcomputer using the same memory - Google Patents

Abstract

PURPOSE:To execute reading of one non-volatile memory by accessing other address in parallel with writing of the memory in parallel with writing of the memory even when the writing of the memory is executed. CONSTITUTION:An address set to a first address register 6a is selected, and data set to a first data register 7a is written in a first non-volatile memory array 1a. An address set to a second address register 6b is selected by a controller 5, and data is stored from a second non-volatile memory array 1b in a second data register 7b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory, particularly to an electrically rewritable non-volatile memory and a microcomputer using this non-volatile memory.

[0002]

2. Description of the Related Art EEPROM as a non-volatile memory
Is electrically rewritable and does not lose data even when the power is turned off, like ROM.
Products have been developed that are built into a one-chip microcomputer (MCU) equipped with a microprocessor, RAM, ROM, and peripheral functions. Whether the EEPROM is built in the microcomputer or used alone, the method of rewriting data is as follows.

FIG. 4 is a flow chart showing a procedure for rewriting the data of the EEPROM, according to
First, an address is designated by an instruction from the outside (step ST1), and then, data corresponding to this address is set (step ST2). Then, electrically rewriting of data is started (step ST3), and this data is stored. After rewriting for a certain period of time, the process ends (step ST4). In this case, when the rewriting of the above data starts, E
The EPROM requires a wait time (writing time) of about several ms, and during that time, the microcomputer itself has to perform another process, but the EEPROM itself is in a completely dead state in which it does not accept any instruction. become.

FIG. 5 is a block diagram showing an EEPROM incorporated in a conventional microcomputer. In the figure, 1 is an EEPROM memory array, 2 is a high voltage decoder, 3 is an address decoder, and 4 is these high voltage decoders 2. And a booster circuit for applying a high voltage (Vpp) to the address decoder 3, 5 is a control circuit for controlling the operation of the address register, data register and timer described later together with the booster circuit 4, and 6 is an address set by an external instruction Address register, 7 is a data register in which data is set, 8 is a data bus, and 9 is the above timer.

Next, the operation will be described. First, data and addresses are set in the data register 7 and the address register 6 via the data bus 8 by control signals B and C based on an instruction from a microprocessor (CPU) incorporated in a one-chip microcomputer. Next, writing to the EEPROM memory array 1 is started by the control signals A and D which are write start signals from the control circuit 5. That is, the booster circuit 4 operates by the output of the control signal A, a predetermined high voltage is applied to the address decoder 3 and the high voltage decoder 2, and the data register 7 is set to the EEPROM memory array 1 of the designated address. Value is written in the period set by the timer 9.

The value set by the timer 9 is, for example, about several ms to 10 ms. When the timer 9 reaches the set value, the control signal E is output as a stop signal and the operation of the booster circuit 4 is stopped. . Therefore, the writing of data is completed.

Incidentally, US Pat. No. 4,382,279 is similar to such a conventional technique.

[0008]

Since the conventional EEPROM is constructed as described above, when data is being written at a specified address of the EEPROM, the other EEPROM is not written during the writing time. However, since there is a dead state, that is, no instruction is accepted, there is a problem that another address cannot be read during this writing period.

The inventions of claims 1 to 3 have been made in order to solve the above-mentioned problems, and even when writing is being performed, other addresses are accessed in parallel while reading is performed. The purpose is to obtain a non-volatile memory that enables it.

According to a fourth aspect of the present invention, when data is being written in the built-in EEPROM, the EEPROM
The purpose is to obtain a microcomputer that can read data from M.

[0011]

According to a first aspect of the present invention, there is provided a nonvolatile memory, wherein an address set in a first address register is selected and a first data is stored in a first nonvolatile memory array. While the data set in the register is being written, the control circuit selects the address set in the second address register to transfer the data from the second non-volatile memory array to the second data register. Is stored.

A nonvolatile memory according to a second aspect of the invention is
A timer that counts the write time to the non-volatile memory array is provided, and during the period of writing data by selecting a specific address for the non-volatile memory array,
Addresses and data are saved by the control circuit to read data at other addresses in the nonvolatile memory array, and after this read is completed, the save is performed within the time obtained by subtracting the write time from the required write time. This is released and the writing is restarted.

A nonvolatile memory according to a third aspect of the present invention is
In the invention according to claim 1 or 2, a plurality of addresses of the nonvolatile memory array can be simultaneously selected at the time of writing.

A microcomputer according to a fourth aspect of the present invention incorporates the nonvolatile memory according to the first aspect of the present invention.

[0015]

According to the non-volatile memory of the present invention, the control circuit electrically rewrites a non-volatile memory of another address while writing to the electrically rewritable non-volatile memory array of a specific address. Access to the memory array and read data, and write and read data in parallel,
Increase system efficiency.

In the non-volatile memory according to the second aspect of the present invention, while the electrically rewritable non-volatile memory array of a specific address is accessed for writing, another address is accessed. When a read operation is performed, the control circuit interrupts the write operation to save the address and data to be written. After the read operation, the save operation is canceled within the remaining required write time, and the write operation can be executed again. .

The non-volatile memory according to the third aspect of the present invention enables reading even when a plurality of electrically rewritable non-volatile memory addresses are simultaneously selected at the time of writing.

The non-volatile memory according to the fourth aspect of the present invention performs the same operation as the non-volatile memory according to the first to third aspects of the present invention.

[0019]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. In FIG. 1, 1a and 1b are electrically rewritable first and second EEPROM memory arrays (nonvolatile memory arrays), and 2a and 2b are first and first EEPROM memory arrays provided for the respective EEPROM memory arrays 1a and 1b. Two high voltage decoders 3a and 3b are first and second address decoders, 4 is a booster circuit, 5 is the above booster circuit 4, and first and second corresponding to the respective EEPROM memory arrays 1a and 1b.
Is a control circuit for controlling the operations of the address registers 6a and 6b and the first and second data registers 7a and 7b, 8 is a data bus in the one-chip microcomputer, and 9 is a timer.

Next, the operation will be described. First, a data bus 8 is generated by a control signal C1 based on an instruction from a microprocessor in a 1-chip microcomputer.
An address is set in the first address register 6a via the, and a predetermined data is set in the first data register 7a via the data bus 8 by the control signal B1.

Next, the control signals A and D, which are write start signals, are output from the control circuit 5 to start writing in the first EEPROM memory array 1a. Then, by the control signal A, the booster circuit 4
Operates and the predetermined high voltage is applied to the first address decoder 3a.
And applied to the first high voltage decoder 2a to the first EEPROM memory array 1a at the specified address,
The data set in the first data register 7a is written during the period set by the timer 9.

On the other hand, when another address is read during the write period, the second address is first set in the second address register 6b by an external instruction. Next, the control circuit 5 outputs the control signal C2 to the second address register 6b, and based on this, the second address decoder 3b operates, and the second EEPRO.
The data in the M memory array 1b is read and stored in the second data register 7b.

That is, the writing to the first EEPROM memory array 1a does not affect the operation of reading or storing the data from the second EEPROM memory array 1b, and the timer 9 counts the set time. After that, the control signal E is input to the booster circuit 4 to end both operations.

Example 2. FIG. 2 shows an embodiment of the invention of claim 2, in which 6c and 7c are address registers for saving used for temporarily saving the address and data of the address register 6 and the data register 7, respectively, and for saving It is a data register.

Further, 1 is a single EEPROM memory array (nonvolatile memory array), 2 is a high voltage decoder, and 3 is a high voltage decoder.
Is an address decoder, 4 is a booster circuit, 8 is a data bus,
Reference numeral 9 is a timer, which basically has the same function as that shown in FIG. 3, and the control circuit 9 is EEPRO.
It functions to control switching between writing and reading of the M memory array 1.

Next, the operation will be described. First, the control signal Q is activated by an instruction from the outside, whereby the control circuit 5 outputs the control signals B and C, and the data and address are set in the data register 7 and the address register 6. Next, the control circuit 5 outputs the control signals A and D to start writing, and the booster circuit 4 starts to operate by the control signals A and E to output a predetermined high voltage to the high voltage decoder 2 and the address decoder 3. Apply to.

As a result, the EEP of the specified address
The data set in the data register 7 is written to the ROM memory array 1 and the timer 9
Counts the time from the start of writing. In addition,
As the timer 9, a timer that counts down a preset time required for writing (for example, 4 msec) is used.

Next, during the write period, if there is a read command for another address, the control signal R is generated from the microprocessor in the one-chip microcomputer and transmitted to the control circuit 5.
Therefore, the control circuit 5 receives the control signal R and generates the control signal H to stop the timer and maintain the state.

Next, the control circuit 5 saves the address and the data of the address register 6 and the data register 7 to the separate address register 6a for saving and the data register 7a for saving, respectively, and the address for which a new access is requested. Is set in the address register 6 and a read operation is performed. Therefore, the accessed E
The data on the EPROM memory array 1 is stored in the data register 7, placed on the data bus, and stored in another general-purpose register or the like.

Next, the control circuit 5 subtracts the count value of the timer 9 stopped as described above from the preset write required time, and updates the count value of the timer 9. After the completion of this update, the address register and the data register are reset to the original address values and data values that have been saved, thereby generating the control signal T, and based on this, the control circuit 5
Inputs the control signal D to the timer 9. As a result, the writing of data to the EEPROM memory array 1 by the previous address is restarted, and this writing is performed within the remaining write-required time.

FIG. 3 is a timing chart of signals of respective parts of the block showing a series of operations of the microcomputer shown in FIG. 2. In FIG. 3, A, D, E, H, Q, R,
T is a control signal in each part of the block.

In each of the above embodiments, EEPRO
The data written in M is often very important data in a system equipped with it. For example, even if something urgent happens and the system needs to read the data in the EEPROM, other systems cannot access other addresses while writing data in the existing system, so Although fatal, this problem can be avoided by the present invention.

Example 3. In each of the above embodiments, electrically rewritable EEPROM memory arrays 1, 1a,
Although the case where the address selection method of 1b is the selection of one address has been described, it can be adopted when a plurality of addresses are simultaneously selected.

For example, EEPROM memory arrays 1, 1
When writing the same data from address 1 to address n in a and 1b, the writing time becomes 1 / n if a plurality of addresses are selected at the same time and writing is performed at once, rather than writing one address at a time. The writing efficiency can be greatly improved. Even if such a writing method is adopted, the EEP according to each of the above embodiments
ROM can be applied. In each of the above-described embodiments, the EEPROM incorporated in the microcomputer has been described, but it may be configured as an independent EEPROM.

[0035]

As described above, according to the invention of claim 1 or 4, the address set in the first address register is selected, and the first data is stored in the first nonvolatile memory array. While the data set in the register is being written, the control circuit selects the address set in the second address register to transfer the data from the second non-volatile memory array to the second data register. Since it is configured to store the data, it is possible to access the address of the other non-volatile memory array in parallel with the above even when writing to the one non-volatile memory array and perform the reading. effective.

According to the invention of claim 2 or 4, a timer is provided for counting the write time to the non-volatile memory array, and a specific address is selected in the non-volatile memory array to write data. Then, the control circuit causes the address and data to be saved, and the data at another address in the non-volatile memory array is read, and after this read is completed, the save is performed within the time that is the write required time minus the write time. Since it is configured to release the above, and restart the above writing,
Even when writing to the nonvolatile memory array, this writing can be interrupted to read data at another address, and the writing can be restarted promptly after completion of the reading. is there.

According to the third or fourth aspect of the invention, since the above-mentioned configuration is adopted when a plurality of addresses of the electrically rewritable nonvolatile memory are simultaneously selected, a method of simultaneously selecting a plurality of addresses at the time of writing is adopted. Even if it is done, each of the above effects can be achieved.

[Brief description of drawings]

FIG. 1 is an EEPROM according to an embodiment of the invention of claim 1;
It is a block diagram showing.

FIG. 2 is an EEPROM according to an embodiment of the invention of claim 2;
It is a block diagram showing.

FIG. 3 is a timing chart showing signals of respective parts of the block in FIG.

FIG. 4 is a flowchart showing a rewriting procedure of a general electrically rewritable nonvolatile memory.

FIG. 5 is a block diagram showing a conventional EEPROM.

[Explanation of symbols]

1 EEPROM memory array (non-volatile memory array) 1a EEPROM memory array (first non-volatile memory array) 1b EEPROM memory array (second non-volatile memory array) 5 control circuit 6 address register 6a first address register 6b 2 address register 6c save address register 7 data register 7a first data register 7b second data register 7c save data register 9 timer

Claims (4)

[Claims] 1. An electrically rewritable first non-volatile memory array and a second non-volatile memory array, and a first non-volatile memory array and a second non-volatile memory array respectively provided corresponding to the first non-volatile memory array and the second non-volatile memory array. A first address register, an address and data are set by an external instruction, a first data register and a second address register, a second data register, and an address set in the first address register. To select the address set in the second address register during the period in which the data set in the first data register is being written to the first nonvolatile memory array. And a control circuit for storing data from the second non-volatile memory array to the second data register. Non-volatile memory. 2. An electrically rewritable non-volatile memory array, an address register and a data register which are provided corresponding to the non-volatile memory array and in which an address and data are set by an external command, and the address. Address registers and data registers for saving the addresses and data of the registers and data registers, a timer for counting the write time to the nonvolatile memory array, and a specific address for the nonvolatile memory array are selected. During the period in which the data is being written, the address and the data are saved, and the data at the other address in the nonvolatile memory array is read out.
A non-volatile memory comprising: a control circuit that cancels the saving and restarts the writing within a time obtained by subtracting the writing time from the required writing time. 3. The non-volatile memory according to claim 1, wherein a plurality of electrically rewritable non-volatile memory array addresses are simultaneously selected at the time of writing. 4. A microcomputer using a non-volatile memory having the non-volatile memory according to claim 1, 2 or 3 incorporated therein.