JPH07248803A - Synchronizing device for dual device - Google Patents

Abstract

PURPOSE:To always secure synchronization between two systems in the dual constitution of signal maintenance devices. CONSTITUTION:This synchronizing device consists of fixed cycle timers 3a and 3b which send status signals of a prescribed time at intervals of a prescribed certain time and are provided in systems (a) and (b) respectively, counters (5a) and 5b which count signals at the time of input of status signals from fixed cycle timers 3a and (3b) of their own systems and those from fixed cycle timers (3b) and 3a of systems of each other and are provided in respective systems, and a setting control means which sets the fixed cycle timer 3b of the slave system (b) again to make this timer 3b match with the fixed cycle timer 3a of the master system (a) at the time of the counted value of the counter 5b of the slave system (b) is reduced to a prescribed value or below.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device configured in a dual system for improving the reliability of the device, for example, a synchronizing device such as an electronic interlocking device.

[0002]

2. Description of the Related Art Conventionally, for example, a railway signal security device is constructed in a dual system to improve reliability.
A system that has a synchronization signal generator configured in a dual system for synchronization processing of the heavy system and outputs the synchronization signal to the two systems is generally adopted. However, in this method, there are problems of synchronization of the synchronization signal generation unit configured in the dual system and problems of complicated configuration such as failure detection and switching.

Further, the software of a conventional railway signal security device does not perform so-called multitask processing that uses a plurality of interrupt signals because of the difficulty of safety verification. Use only include. That is, each system device (hereinafter, abbreviated as a device) performs input, logical judgment, output to another system, input from another system, output process, etc. in a fixed period timer interrupt process. Therefore,
If the timings of the fixed-cycle timer interrupt signals are matched, the synchronous processing of the two systems can be realized.

However, when each system is processed independently by each fixed-cycle timer without being synchronized with the fixed-cycle timer interrupt signal level, the processing timing is different, and naturally, the processed data is processed between both systems. In addition, there are many inconsistencies in the calculation results, and the slaves have many disadvantages such as waiting for data from the master, which causes unnecessary processing and extra time.

As a means for solving such a problem,
A synchronizer for a dual system device capable of synchronizing a fixed-cycle timer interrupt signal has been proposed (for example, actual Kaihei 3-1285).
59 publication).

The synchronizer according to the above proposal is a CP for each system.
A timer is connected to each U and the outputs of the timers of the other system are input to each other to perform synchronization processing.

[0007]

However, in the synchronizer according to the above-mentioned proposal, since each system resets the timer every system cycle and performs the synchronization process, for example, the number of timer interrupts is counted. In the case of time control, there is a drawback that the control value becomes complicated because the set value must be determined in consideration of the timer reset time and other factors in order to obtain the time equal to the actual time.

Therefore, the present invention has been made in order to solve the above-mentioned drawbacks, and the synchronization process (reset) is not performed while the two systems are kept within a predetermined synchronization range, and the predetermined process is not performed. It is an object of the present invention to provide a dual-system synchronizing device that performs a synchronizing process when it deviates from the synchronizing range.

[0009]

In order to achieve the above-mentioned object, a dual system synchronizing device according to the present invention has a microprocessor unit (hereinafter referred to as a microprocessor unit) which operates by a predetermined program common to both a master system and a slave system. , MPU) of a dual system, and a fixed cycle timer provided for each of the above systems that sends a status signal of a predetermined time at a predetermined fixed time, and a fixed cycle timer of its own system. When the count value of each of the counters provided in each of the above-mentioned systems that counts when the status signal from the above and the status signal from the fixed cycle timer of the other system are input, and the count value of the above-mentioned counter of the slave system are below a predetermined And setting control means for resetting the slave fixed cycle timer so as to match the master fixed cycle timer.

[0010]

In the above structure, the setting control means causes the slave constant cycle timer and the monitoring timer to match the master constant cycle timer when the count value of the slave counter becomes less than a predetermined value. Reset.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an apparatus of one embodiment.

The main system a and the sub system b each have a system bus Ba, Bb, each of which includes a plurality of CPUs.
It is configured by connecting the PU boards Ma and Mb, the input boards Ea and Eb, and the output boards Oa and Ob.

In FIG. 1, a 'and b'are both MPU boards M.
A signal line connecting a and Mb, which is used when transmitting and receiving a status signal described later.

In FIG. 1, the input / output boards Ea,
Although only one Eb, Oa, Ob is connected to each system bus B1, B2, this is for simplifying the drawing, and a plurality of boards are connected.

FIG. 2 is a detailed block diagram of the MPU boards Ma and Mb. Both boards Ma and Mb have MPUs 2a and 2b driven by basic clocks 1a and 1b, which are crystal oscillators, respectively. is doing. In addition, each MP
U2a and 2b are respectively connected to the system buses Ba and Bb via an interface (not shown).

Each MPU board Ma, Mb has a fixed period timer 3a, 3b for generating a status signal of a predetermined time at each predetermined time, and output buffers 6a, 6b for outputting the status signal to another system. And an input buffer 7a for inputting a status signal from another system,
7b and a monitor timer 4 having basic clocks 4a 'and 4b' for monitoring the fixed period timers 3a and 3b, respectively.
a and 4b. The status signal is a signal with a duty of 50%, and when the rising edge changes, MP
The U-boards Ma and Mb are configured to generate a fixed-cycle interrupt.

The counters 5a and 5b provided on the MPU boards Ma and Mb, respectively, are their own system (here, the main system a is the own system. In addition, the following () indicates when the slave system b is the own system. The output signal of the fixed-cycle timer 3a (3b) (status signal (see () in FIG. 2))
And the output signal (status signal (see () of FIG. 2)) of the fixed cycle timer 3b (3a) of the other system.
AND circuit 8a (8b) that receives an input via b (6a)
It is configured to be driven with the output signal of. The counters 5a and 5b have their own MPU 2a (2
The count value can be written or read from b).

Next, the synchronization control operation of the apparatus of this embodiment will be described with reference to the flow chart of FIG. 3 and the time chart of FIG.

Now, the power of a dual system (not shown) is turned on, the input / output / internal auxiliary relays, etc. are cleared, and a predetermined initial process such as presetting of all timers is performed, so that the dual system is established. It is assumed that it has been started up and is in operation (step 100 in FIG. 3, hereinafter referred to as step S). During this operation, the slave system b changes from L (low) to H (high) of the status signal of the master system a, and the master system a selects the master system as the master system. Timers 3a, 3b, monitoring timers 4a, 4b,
The counters 5a and 5b are set (S102 and S in FIG. 3).
104, S106. See (a) of FIG. ). Therefore, at this time point, both systems a and b have a perfect cycle.

When the operation is continued, a deviation occurs in the synchronization state of the status signals from the constant period timers 3a and 3b of each system a and b due to the error of the basic clocks 1a and 1b of both systems a and b. come. For example, the basic clocks 1a and 1b are 10
In the case of MHz, there is usually an error of about 100 Hz, so the above-mentioned deviation occurs. In addition, this deviation is several hundred
If it is on the order of μs, there is no problem in the operation of the device, so that it is acceptable (see t0 in FIG. 4).

When this deviation becomes large, the synchronization state of the systems a and b is lost. Therefore, when the deviation becomes, for example, 100 μs or more, the fixed period timer 3b and the monitoring timer 4b of the slave system b are set to the main system a. Fixed-cycle timer 3a and monitoring timer 4
A synchronization process for matching with a is performed.

The synchronization process will be described below.

When the dual systems a and b continue to operate,
The counter 5b of the slave system b receives both the status signal (see FIG. 2) from the fixed cycle timer 3b of the self system (slave system b) and the status signal (see FIG. 2) from the other system (master system a). When H, counts. Therefore, when the status signals of the two systems completely match, the count value N
Is N = 1/2 × T (T: time of one cycle). Further, when the two status signals are deviated, the count value N becomes N = 1/2 × (T-t1) (t1: deviation time). Assuming that the time allowed for deviation between the two status signals is t0, the count value N is now N = 1/2.
If × (T-t1) ≧ (1/2) × T-t0, the deviation is within the allowable time, so the subordinate system does not reset the fixed cycle timer 3b and the monitoring timer 4b of its own system, and operates as it is. Is continued (S110, S112 affirmative, S114 affirmative, S120 in FIG. 3; see (B) in FIG. 4).

However, the count value of the counter 5b is N
= 1/2 x (T-t1) <1/2 x (T-t0) (No in S114; see (c) in Fig. 4), it is determined that a deviation exceeding the allowable time has occurred. Because it means the main system a
Status signal of the fixed cycle timer 3a (see FIG. 2)
Is changed from H to L, the subordinate system resets the fixed period timer 3b and the monitoring timer 4b of its own system. As a result, the fixed-cycle timer interrupts of both systems a and b are synchronized (S116 and S118 in FIG. 3; see (D) in FIG. 4).

As described above, the apparatus of this embodiment is compatible with both systems a,
When the status signal of b has deviated more than a predetermined amount,
The fixed cycle timer 3b and the monitoring timer 4b of the slave system b are connected to the master system a.
Since the constant period timer 3a and the monitoring timer 4a are matched with each other, both systems a and b can always maintain the synchronized state.

[0026]

The dual system synchronizer according to the present invention has a fixed cycle timer provided in each system for sending a status signal for a predetermined time at a predetermined fixed time and a fixed cycle timer of its own system. When the count value of each of the counters provided in each of the above-mentioned systems that counts when the status signal from the above and the status signal from the fixed cycle timer of the other system are input, and the count value of the above-mentioned counter of the slave system are below a predetermined Further, since it comprises the setting control means for resetting the fixed cycle timer of the slave system so as to match the fixed cycle timer of the main system, each system can be kept in a synchronized state at all times.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing details of an MPU board.

FIG. 3 is a flowchart showing a synchronization control operation.

FIG. 4 is a time chart showing a synchronization control operation.

[Explanation of symbols]

a main system device (main system) b slave device (slave system) Ma, Mb MPU board Ba, Bb system bus 1a, 1b, 4a ', 4b' basic clock 2a, 2b MPU (microprocessor unit) 3a, 3b fixed Periodic timer 4a, 4b Monitoring timer 5a, 5b Counter

Claims (1)

[Claims] 1. A synchronization device for a dual system device, comprising a microprocessor unit that operates according to a predetermined program common to both a master device and a slave device, and a status signal of a predetermined time is sent every predetermined constant time. A fixed cycle timer provided for each of the system devices to be sent out, and each system for counting when a status signal from the fixed cycle timer of the own system device and a status signal from the fixed cycle timer of another system device are input When the count value of the counter provided in each of the devices and the count value of the counter of the slave device becomes less than or equal to a predetermined value, the constant cycle timer of the slave device is made to match the constant cycle timer of the master device. And a setting control means for resetting the setting of the above.