JPH0724017B2 - Multivalued logic function circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION SUMMARY OF THE INVENTION It consists of a multilevel signal source, a memory array, an addressed switch, and an output line.

From the multi-valued signal source, signals representing respective logic values of multi-valued logic are generated.

The memory array has a number of address lines on which any multi-valued logic signal will appear due to a program based on a given truth table.

Any one of the address lines is selected by the addressed switch to which the input signal is applied, and the logical value signal of that line is led to the output line.

Table of contents (1) Background of the invention (2) Outline of the invention (2.1) Purpose of the invention (2.2) Structure and effect of the invention (3) Description of embodiments (3.1) Definition of multivalued logic function (3.2) Field programmable multi Value logic function circuit (3.3) Decoder (3.4) Other examples of addressed switches (3.5) Mask programmable multivalue logic function circuit (3.6) Multifunction circuit (3.7) CMOS multivalue logic function circuit (1) Invention BACKGROUND The present invention relates to a multi-valued logic function circuit which is a basis for constructing a multi-valued logic system and is suitable for IC implementation.

2. Description of the Related Art Multi-valued logic and its arithmetic circuit have been actively researched as a means for complementing or overcoming some limitations of binary logic which is the basis of many digital circuit systems including computers. The binary logic handles two values of 0 and 1, and the signal used in the binary logic circuit system takes two levels corresponding to these two values, whereas the multivalued logic has three or more values. The signal used in the multi-valued logic circuit system has three or more levels.

Multilevel logic (circuit system) is binary logic (circuit system)
It is said that it has the following advantages compared with.

1) It is possible to describe an indeterminate state between 0 and 1 (for example, in the case of 3 values).

2) The wiring area and the number of pins on the IC substrate can be reduced, and the effective integration level can be increased. For example, in the case of 64 levels, 1/6 wiring area of a binary logic circuit is sufficient.

3) The realization of a 10-value machine enables the use of the same logic as humans, so the encoder and decoder required in a 2-value machine are unnecessary.

A multi-valued arithmetic logic unit (multi-valued ALU) is the most basic for constructing a multi-valued logic system having such features, especially a system replacing the conventional binary computer. This multivalued ALU must be capable of performing arbitrary multivalued logical operations. There are more than a dozen types of well-known operations such as MAX, MIN, addition, subtraction, multiplication, and division in multivalued logical operations. Execution of a multi-valued logical operation is equivalent to the generation of a multi-valued logic function that represents the result of the operation. It is necessary to realize it. According to a simple combination, the multi-valued logical function exists in the n-th power of n-th power when there are n-valued r-inputs. For example, in a three-value two-input multi-valued system, the kind of multi-valued logic function is 3
That is to say, 19683, which is about 4.3 billion ways with 4 levels and 2 inputs. It is almost impossible to design such a huge number of multivalued logic function circuits.

(2) Outline of the invention (2.1) Object of the invention The object of the present invention is to provide a multivalued logic function circuit which, when given a truth table of a multivalued logic function, performs an operation according to the truth table. It will be realized.

(2.2) Structure and effect of the invention The multi-valued logic function circuit according to the present invention includes a plurality of multi-valued signal sources that generate signals respectively representing a plurality of logic values of the applied multi-valued logic, and are connected to these signal sources, respectively. Memory array including a plurality of signal lines and a plurality of address lines connected to any one of the signal lines at a node by being programmed according to a given truth table, multi-valued It is provided with an addressed switch for selectively conducting any one of the above address lines by an input signal, and an output line connected to all of the addressed lines at the output side of the addressed switch. Characterize.

Memory in the case of field programmable circuits
Only the array is programmed according to the truth table.
In the case of mask programmable circuits, the memory array and addressed switches will often be programmed.

In any case, the program may be performed according to the truth table, and the program can be easily programmed as long as the truth table is given. In this way, a circuit for calculating an arbitrary multivalued logic function is realized.

(3) Description of Embodiments (3.1) Definition of Multivalued Logic Function There are two types of methods for defining a multivalued logic function.

One of them is a method of defining with a formula expressing a function. For example, a multi-valued logical function MAX having x and y as variables is expressed by the following equation.

The multivalued logic function MIN is defined by the following equation.

Another way to define a multivalued logic function is to use a truth table. Fig. 1 shows an example of a truth table of a multi-valued logical function (which also has four values) that has three variables x, y and z and each variable has four values 0, 1, 2 and 3. Is shown in. Since any value can be written in the truth table, it is possible to easily define any multivalued logical function by using the truth table. While the types of functions that can be defined are limited according to the definition method using function expressions, any function can be defined using a truth table.
This is a great advantage of the definition method using the truth table. Moreover, since the function defined by using the formula can also be replaced with the truth table, it can be said that the method using the truth table includes the method using the formula.

Therefore, in the following description, a multi-valued logic function is defined in principle using a truth table.

A multi-valued logical function defined by a truth table can be expressed by a mathematical expression as follows using the values in the truth table. That is, the multi-valued logical function f (x, y, z) with variables x, y and z is given by the truth table value Clmn,
It is expressed as follows.

f (x, y, z) = ΣΣΣClmn * {kl (x) ・ km (y) ・ kn (z)} ……
(3) where And for r values, x, y, z, l, m, n are 0, 1, ..., (r
-1).

In the equation (3), the symbols * and · both represent multiplication.

When considering a multi-valued logic function circuit that outputs a multi-valued signal representing the function f (x, y, z) of the equation (3), the variables x, y, z are multi-valued inputs representing those values. Given by signal. Also,
The symbol * is realized by AND logic operation, and * is realized by switching.

In order to obtain an output signal representing an arbitrary multi-valued value function by such a multi-valued logic function circuit, the circuit must be programmable. Any multi-valued logic function will be obtained by programming the value Clmn of the truth table above on the circuit, ie by programming the circuit which produces the value Clmn.

To program the circuit that generates the value Clmn in the truth table, the method of programming the circuit in the process of manufacturing the circuit in the IC manufacturing process (mask programmable), and the unprogrammed circuit can be programmed by the user using a PROM writer. There is a method of programming (field programmable).

(3.2) Field programmable multivalued logic function circuit FIG. 2 shows a circuit for realizing the operation represented by the above-mentioned expression (3) to obtain an output signal representing the function f (x, y, z). The value Clmn in the truth table shows an example of a field programmable circuit. This circuit is a multi-valued logic function circuit with four values and three inputs (three variables).

The circuit shown in FIG. 2 can operate in either the current mode or the voltage mode. First, the current mode will be described as a premise, and then the case of switching to the voltage mode will be described.

In FIG. 2, the multivalued logic function circuit includes four signal sources 10 to 10
13, a node memory array 21 connected to these signal sources 10 to 13, and an address memory array 21 connected to this array 21.
It is composed of a switch 23 and an output line 5 connected to the output side of the addressed switch 23.

The signal sources 10 to 13 are current sources, and the detailed configuration thereof will be described later. Since this embodiment is a four-valued logic function circuit, these four values 0, 1, 2 are obtained from these signal sources 10 to 13.
Currents representing 3 and 3 are output respectively. The current source 10 for the current representing the value 0 is not absolutely necessary.

In the node memory array 21, these current sources 10 to
The lines (signal lines) connected to 13 respectively form rows, and these lines are called the 0th to 3rd lines. Lines (address lines) forming 64 columns are arranged with respect to the lines forming these rows.
From the left side of FIG.
Columns, ..., Let's call these lines in the 64th column. Each line that forms a row and each line that forms a column are connected to each other only at one location to form a node.

This memory array is field programmable, and generally, rows and columns of lines are arranged in a three-dimensional manner on a silicon chip. Normal programmable RO
Similar to M, the type that forms a node by the destruction of the pn junction or the breakdown of the insulating layer due to the application of a large current or a large voltage, and the necessary node is left by melting the fuse of the unnecessary node There are some types, but all are applicable.

In any case, this memory array 21 is programmed with the truth table values representing the desired multi-valued logic function as shown in FIG. The line in the first column is x = 0, y = 0, z
= 0, the line in the second column corresponds to x = 1, y = 0, z = 0, the line in the third column corresponds to x = 2, y = 0, z = 0, and, for example, All columns have a one-to-one correspondence with all combinations of variables x, y, z, such as corresponding to the ninth column line x = 0, y = 2, z = 0. Then, the line of each column has a function f (x, x, y, z whose value is a variable
y, z), that is, the value of the truth table, Clmn (= Cxyz), is connected by a node to the line of the row derived from the current source.

The combination circuit of the current sources 10 to 13 and the memory array 21 is 64
It can be said that it is equivalent to individual current sources.

Since the memory array 21 is programmable, it is possible to program the values of any truth table so that a circuit for outputting a signal representing any multivalued logic function f (x, y, z) can be programmed. Will be realized.

The address switch 23 selectively selects the current representing the function f (x, y, z) set in the memory array 21 according to the inputs x, y, z given to the input terminals 1,2,3, respectively. It is to be taken out or read out (switched on). The addressed switch 23 is composed of decoders (1 of 4 decoders) 31, 32 and 33 having inputs x, y and z as inputs, and an AND array 22 connected to the output side of these decoders. Has been done. When the input x (current mode or voltage mode) represents a logical value 0, the decoder 31 outputs an H level signal to the output terminal of = 0 and outputs the output of the other output terminals to the L level. To Similarly, when the input x has logical values of 1, 2, and 3, H level signals are output to the output terminals of = 1, 2, and 3, and the output of the other output terminals is set to L level. The other decoders 32, 33 work similarly.

From each decoder 31, 32, 33 extend four control lines in rows, which intersect with column lines extending from or connected to the memory array 21. At this intersection, a switching element composed of an n-channel MOS FET represented by a circle indicated by A is provided (see FIG. 3). Three of these switching elements A are connected in series to each column line, and each switching element is controlled by a line forming a row extending from each decoder 31, 32, 33. The control lines for controlling the three switching elements in each column are different in each column. For example, the three switching elements in the first column are x = 0, y = 0, z =
When it is 0, all of them are turned on and this line becomes conductive.
Similarly, the line in the second column is x = 1, y = 0, z = 0, and the line in the third column is x = 2, y = 0, z = 0.
The lines in the columns are conductive when x = 1, y = 2, and z = 0.

That is, the addressed switch 23 conducts only the one of the 64 column lines addressed by the combination of inputs x, y, z. It goes without saying that the addressed switch 23 or at least the AND array 22 is also integrated into an IC.

At the output side of the address switch 23, these 64
One column line is connected to one output line 5.
The output line 5 is provided with the output terminal 4 of the function f (x, y, z).

Therefore, the column line designated by the inputs x, y, z is made conductive by the addressed switch 23, and a current of a preprogrammed value from the corresponding node of the memory array 21 is applied to the designated column. The corresponding function f through the line, output line 5, and output terminal 4
It is output as a current representing (x, y, z).

FIG. 4 shows an example of a specific configuration of the current sources 11-13.

In FIG. 4 (A), the current I ₀ corresponding to the value 1 in the multi-valued logic is given to the input terminal 9, and this current I ₀ is nMOS.
It is input to the 6-output current mirror 14 composed of a FET. The direction of one output current of this current mirror 14 is inverted by the current mirror 15 consisting of a pMOS FET, and the output voltage I ₀ is output to the output terminal.
Appears in 11a. This output current I ₀ corresponds to the output current of the current source 11 in FIG. By connecting the two output drains of the current mirror 14 to each other, a current having a value of 2I ₀ is produced, and this current 2I ₀ is inverted by the current mirror 16 and appears at the output terminal 12a. Further, the three output drains of the current mirror 14 are connected to each other to generate a current having a value of 3I ₀ , which is inverted by the current mirror 17 and appears at the output terminal 13a. Output current of output terminals 12a, 13a 2I ₀ , 3I
₀ corresponds to the output current of the current sources 12 and 13 in FIG.

In FIG. 4 (B), three currents having the value of I ₀ are output from the three-output current mirror 14B, and these three currents are input to the current mirrors 15B, 16B, and 17B, respectively. Current mirror 15B
Is a one-output current mirror, it outputs a current having a value equal to the input current I ₀ . The current mirrors 16B and 17B are two-output current mirrors and three-output current mirrors, respectively, and their output drains are connected to each other, so that currents of 2I ₀ and 3I ₀ are obtained from these current mirrors. To be

In FIG. 2, a series circuit of a switching element 34 composed of an nMOS FET and a resistor 35 is connected in parallel to the output line 5. The resistor 35 is connected. Switching element 34
Is ON / OFF controlled by a voltage signal applied to the mode select terminal 7.

When the circuit of FIG. 2 is operated in the current mode as described above, the L level voltage is applied to the terminal 7 to turn off the switching element 34.

When operating in the voltage mode, an H level voltage signal is applied to the terminal 7 to turn on the switching element 34. Then, the current representing the function f (x, y, z) flows through the switching element 34 to the resistor 35, so that the voltage drop appears at the output terminal 4. However, the input impedance of the circuit at the next stage connected to the output terminal 4 is assumed to be large. In this way, the current sources 10 to 13 are left as they are (the line of the 0th row connected to the current source 10 is preferably grounded), and only the mode select signal applied to the terminal 7 is switched. This makes it possible to switch between current mode and voltage mode.

Instead of connecting the switching element 34 and the resistor 35 to the output line 5, they may be connected to each row line of the memory array 21.

Needless to say, the circuit of FIG. 2 can be changed to a voltage mode circuit by using a voltage source instead of the current sources 10 to 13.

Also provided in FIG. 2 are circuits for programming the memory array 21. This circuit includes switching elements 40 to 43 each having one terminal connected to each row line of the memory array 21, and the switching elements 40 to 43.
6 connected to the other terminal of the switching element, and a switching element
It is composed of a decoder 44 for generating a signal for controlling ON / OFF of 40 to 43. Decoder 44 has terminal 8
A line select signal is given from. This select signal is also preferably a four-valued signal.

Programming is performed as follows. By the line select signal applied to terminal 8, the memory array
Select any of the four 21 row lines. The switching element (any one of 40 to 43) corresponding to the selected row line is turned on. Further, a signal for selecting a column line is applied to the input terminals 1, 2, and 3 as inputs x, y, z, and a desired column line is made conductive. After the above operation, a large current or a large voltage is applied between the output terminals 4 and 6. Then, at the intersection of the selected row line and column line,
Depending on the type, nodules are formed or even nodules are cut.

This operation is repeated for all nodes to be formed or cut to complete programming of the memory array.

It is possible to replace the current sources 11 to 13 with the circuit of FIG. 4 to form the entire circuit of FIG. 2 into an IC, and in this case, the number of input terminals can be extremely reduced. That is, input terminals 1, 2, 3 output terminals 4, voltage or current application terminal 6 for programming, mode select terminal 7, line
The select terminal 8, the input terminal 9 for the unit current I ₀ , and the necessary operating current V _DD and the ground terminal may all be provided on a single chip as 10 pins.

(3.3) Decoder Next, specific examples of the decoders 31, 32, 33 and 44 shown in FIG. 2 will be described. Since these decoders can have exactly the same configuration, the decoder 31 will be described as an example.

FIG. 5 is an example of a decoder applied when the input x is a voltage signal. 4 output terminals = 0 to 4 outputs
It is shown from x _{0 to} x ₄ . Since the circuit of FIG. 5 is formed by sequentially connecting basic circuits, the basic circuit will be described first with reference to FIG.

In FIG. 6, two pMOS FETs Qa and Qb are connected in series. A power supply voltage, that is, an H level voltage Vj _{+ 1} is applied to the drain of one FET Qa, and the source of the other FET Qb is connected to the gate and grounded. The output terminal is provided at the connection point of the two FETs Qa and Qb (output voltage Ej). In this basic circuit, the output voltage Ej is H level only when the H level voltage is applied to the source of one FET Qa and the L level input voltage Vj is applied to the gate of the FET Qa.
Become a level.

Now, returning to FIG. 5, this circuit is the same as the basic circuit described above.
They are connected in sequence. A power supply voltage V _DD (for example, 5V) is applied to FETs Q ₁ , Q ₂ , and Q ₃ of one of the three basic circuits, and those FETs Q ₁ , Q ₂ and Q ₃ are controlled by an input voltage signal x. . FETQ ₅ and Q ₆ of the other two basic circuits are FETQ ₁ and
It is connected to the drain side of Q _2, the other _one of the basic circuits FETQ
_The power supply voltage V _DD is applied to ₄ . If the right side of the circuit of FIG. 5 is taken as the front stage side, the gates of the FETs Q ₄ , Q ₅ , and Q ₆ are controlled by the output voltage (corresponding to Ej of FIG. 5) of the basic circuit of the front stage.

Further, as shown in FIG. 7, the rising threshold values V _TH of the drain currents of the FETs Q ₁ , Q ₂ and Q ₃ are different from each other −θ ₁ , −
θ ₂ , −θ ₃ , for example, θ ₁ = 0.83V, θ ₂ = 2.50V, θ ₃ = 4.
Each is set to 17V. V _DD −θ ₃ , V _DD −θ ₂ , V _DD
-Θ ₁ is the threshold value Th for discriminating the level of the input voltage x.
It becomes ₁ , Th ₂ , Th ₃ . The threshold V _TH of the other FETs Q _{4 to} Q ₁₂ may be about 1V or more.

When the input voltage x is less than or equal to the threshold value Th ₁ , an L level voltage is applied to the gate of the FET Q ₃ of the basic circuit at the front stage, so the output voltage x ₀ of this basic circuit is H.
It becomes a level. Of the basic circuit that produces the other outputs x ₁ , x ₂ , x ₃
Since the gates of FETQ ₆ , Q ₅ and Q ₄ are at H level, their outputs x ₁ , x ₂ and x ₃ are at L level.

When the input voltage x is Th ₂ >x> Th ₁ , the voltage at each point changes as shown in (). In other words, the gate of the FETs Q ₃ because the H level, the output x ₀ becomes L level.
As a result, the gate of the FET Q ₆ becomes L level, and the output x ₁ becomes H level. The other outputs x ₂ and x ₃ remain L level.

Thus, when Th ₃ >x> Th ₂ , only output x ₂ is H
When Th ₃ <x, only the output x ₃ becomes H level.

The circuit in Fig. 5 is composed of pMOS FETs,
It goes without saying that the decoder can be configured in the same way even if MOS FETs are used. Next, an example of the decoder when the input signal x is a current will be described. This can be constructed using multiple literal circuits operating in current mode. The current mode literal circuit is described in detail in the applicant's earlier application, Japanese Patent Application No. 60-16897, which will be briefly described here.

An example of a 1-of-4 decoder utilizing four literal circuits is shown in FIG. Input current x is a multi-output current mirror
To the literal circuit 50, which produces six currents of the same value as the input current x, one of which produces the output of x ₀ , and the other two each produce x ₁ , The remaining one is sent to the literal circuits 51 and 52 that generate the x ₂ output, and the other one is sent to the literal circuit 53 that generates the x ₃ output.

The operation of the literal circuit 51 that generates the output signal ^ab _x ▼ (a = 0.5, b = 1.5) will be described.
PMOS is connected between the current source 59 representing the value of -1) and the output terminal.
FETQ _S1 and nMOS FETQ _S2 are connected in series. Further, current sources 55 and 56 for currents representing the values of a and b are provided, and the output sides of the multi-output current mirror 54 are connected to the output sides of these current sources 55 and 56 at nodes 57 and 58, respectively. FETs Q _S1 and Q _S2 are controlled by the voltages at the nodes 57 and 58, respectively.

When x> a, the potential of node 57 becomes L level, and FETQ
_S1 turns on. When x <b, the potential at the node 58 becomes H level and the FET Q _S2 is turned on. Therefore, as shown in FIG. 9 (B), only during a <x <b,
A current of (r-1) is obtained at the output terminal.

Similarly, in the literal circuit 52, since a = 1.5 and b = 2.5 are set, the output current is obtained from the output terminal when 1.5 <x <2.5.

In the literal circuit 50, those corresponding to the current source 55 and the FET Q _S1 are omitted. Also, b is set to 0.5. Therefore, the output current is obtained when x <0.5.

In the literal circuit 53, the parts corresponding to the current source 56 and the node Q _S2 are omitted, and a = 2.5 is set, so that the output current is obtained at 2.5 <x.

These output currents are shown in FIG. Therefore, from the circuit shown in FIG. 8, the output current can be obtained from any one of the four output terminals according to the value of the input current x. This output current is made to flow to the ground side through the resistance as shown by the chain line, and the voltage drop in this resistance causes
The switch A of the AND array 22 may be controlled.

When the circuit of FIG. 8 is used as a decoder, the value of (r-1) of the current source 59 may be any value.

(3.4) Another example of the addressed switch In the multivalued logic function circuit shown in FIG.
The switch 23 can be replaced by other circuits, for example some bilateral T-gates as shown in FIG.

For simplification, the circuit shown in FIG. 10 shows the case of two inputs x and y. Further, voltage sources 11A to 13A are used instead of the current sources 11 to 13 in FIG. Of course, a current source can be provided, and in that case, a current, voltage changeover switch and resistance can be provided.

The bilateral T gate is a gate which outputs one of the input signals as an output signal by selecting a plurality of input signals with a select signal. In FIG. 10, the addressed switch has four bilateral T's each having an input x as a select signal and each having four input terminals.
It is composed of gates 61 to 64 and one bilateral T gate 65 which receives the outputs of these bilateral T gates and uses the input y as a select signal. Four lines from the first column to the sixteenth column are input to the bilateral T gates 61 to 64, respectively. In addition, bilateral T gate
The output of 65 represents the output signal f (x, y).

(3.5) Mask programmable multi-valued logic function circuit Field programmable and mask programmable are, in principle, the nodes of the memory array as shown by reference numeral 21 in FIG. The only difference is in which process to program,
(Although the IC structure also differs), there is no difference in the circuit. However, in the case of mask programmable, since the circuit pattern is determined at the design stage, there is no flexibility, but there is an advantage that the circuit pattern can be simplified.

FIG. 2 is an example of a field programmable circuit, and FIG. 11 is an example of a circuit obtained as a result of simplifying the circuit of FIG. 2 by using a mask programmable circuit.
The simplification of the circuit pattern will be described in comparison with the figure. 11, the same parts as those shown in FIG. 2 are designated by the same reference numerals. Further, the decoder 44 and the switching elements 40 to 43 controlled by the output thereof are unnecessary.

As can be seen from the truth table of FIG. 1, at z = 0 and y = 2, f (x, y, z) = 1 regardless of the value of x.
This portion is realized as lines in columns 9 to 12 in the circuit of FIG. Since the nodes of the four columns are all in the first row on the memory array 21, it is possible to omit the lines for three columns and to represent the four columns by one line. . This new line is shown as the new ninth column line in FIG. Since the output f (x, y, z) has the same value regardless of the value of the input x, the AND array 2
2, the switching element controlled by the input x is not provided on the new ninth column line. Only switching elements A1 and A2 controlled by inputs y (= 2) and z (= 0) are provided on the new ninth column line.

Similarly, in the truth table of FIG. 1, when z = 2, f (x, y, z) = 2 regardless of the values of x, y. Therefore, the corresponding lines in columns 33 to 48 in FIG. 2 can be represented by the new line in column 30 as shown in FIG. Z = 2 regardless of input x, y
Since f (x, y, z) takes a value of 2 when,
Only the switching element A3 controlled by the input z is provided on the column line.

Further, as shown in FIG.
It is also possible to omit the row lines, ie the column lines connected to the extension lines of the signal source 10 of zero.

In this way, the multiple logic function circuit of FIG. 2 becomes extremely simplified in the end as shown in FIG. 12 if the above-mentioned idea of omission is adopted.

In the mask programmable circuit, the memory array 21
It should be noted that the AND array 22 must be programmed as well.

(3.6) Multi-function circuit A multi-function circuit is a circuit that generates multiple function outputs for a certain combination of inputs. FIG. 13 shows an example of a truth table of a 2-input 4-value multi-function, and FIG. 14 shows an example of a multi-function circuit for executing the function operation of the truth table.

In FIG. 13 (A), four function values are shown in Matrices for the combination of the input variables x and y. These function values show the values of the functions f ₁ , f ₂ , f ₃ and f ₄ shown in FIG. 13 (B).

In FIG. 14, four lines (output lines) connected to the output terminals 35 to 38 for outputting the _four functions f _{1 to} f ₄ are provided, and these row lines are connected to the memory array 21. It intersects the column line. The output lines of the first row corresponding to the function f ₁ are the lines of the first to fourth columns, and the output lines of the second row corresponding to f ₂ are the lines of the fifth to 14th columns, f ₃
The output line of the 3rd row corresponding to is the line of the 15th to 28th columns, and the output line of the 4th row corresponding to f ₄ is the 29th column ~
It is connected to the 42nd line and forms a knot. These four lines and nodes are sum arrays 24
Are configured.

On the four column lines connected in the sum array 24 to the output row lines corresponding to the function f ₁ , the switching elements controlled by the outputs of the decoders 31 and 32 in the AND array 22 are provided in the memory array 21. Voltage signal source 11A-13A
The connections with the three row lines extending from each are preprogrammed in the optional manner described above.

The same applies to the column lines that generate the other functions f _{2 to} f ₄ .

According to the circuit of FIG. 14, when a certain combination of inputs x and y is given, four different functions f ₁ showing the results of calculating the inputs x and y according to the truth table of FIG. 13 (A). ~ F ₄
It will be easy to understand that a signal representative of is obtained. In such a multi-function circuit, the memory array 21, the AND array 22
In addition to the above programming, the thumb array 24 also needs to be pre-programmed.

In the circuit of FIG. 14, the number of column lines can be further omitted. For example, the second line and the 40th line
Both of the lines in the column are for generating output signals having a value of 3 when x = 2 and y = 1, and these signals appear at output terminals 35 and 36, respectively. Therefore, change the line in the second column and the line in the 40th row connected to the output terminal 38 to B
Even if the line in the 40th column is removed, the same output signal as that described above can be obtained at the output terminals 35 and 38 by connecting with the node shown by. In this way, among the different functions, it becomes possible to leave only one line and omit the other lines for the column lines that generate the function output of the same value when the combination of inputs is the same.

(3.7) CMOS multi-valued logic function circuit In the above embodiment, the nMOS FET is mainly used as the switching element in the AND array 22.
It is also possible to replace with FET. However, CM
Using an OS FET can improve speed and prevent errors. The circuit using CMOS will be described below.

Figure 15 shows the switching operation using nMOS.
(A) is a circuit diagram and (B) is a waveform diagram.

In FIG. 15, a switching element composed of an nMOS FETQ _N is connected between a voltage source E and an output terminal (output voltage Vo), and the output terminal is grounded via a resistor _RL having a large resistance value. FETQ _N is on / off controlled by a control signal Vc.

When the control voltage Vc becomes H level (for example, 5V), the FET Q _N is turned on and the H level output voltage Vo appears. Control voltage
When Vc becomes L level (OV), FETQ _N turns off and the output voltage Vo also becomes L level (OV).

In this switching operation, as shown in FIG. 15 (B), the output voltage Vo rises very quickly when the FET Q _N is turned on. However, the power supply voltage E is
The voltage is divided by the resistance of TQ _N and the resistance R _L, and the output voltage Vo becomes lower than the voltage E. This causes an error, and even if there are no problems in a circuit with 3 or 4 values, it becomes an important problem with, for example, about 10 values. Further, when the FETQ _N is turned off, the charge stored in the substrate-source capacitance C _SB of the FETQ _N is discharged through the resistor R _L , which causes a problem of extremely slow response.

FIG. 16 shows a solution of the above problems using a CMOS FET. (A) is a circuit diagram and (B) is a waveform diagram. The pMOS FETQp is connected between the voltage source E and the output terminal, and the nMOS FETQ _N is connected between the output terminal and the ground. Both of these FETs Qp and Q _N are controlled by the control voltage Vc. The control voltage Vc has both polarities (for example, + 5V to -5V) as shown in FIG. 16 (B).

When the control voltage Vc is H level (+ 5V), FETQp is off,
Since FETQ _N is turned on, the output voltage V _O changes to L level (O
V). Conversely, when the control voltage Vc becomes L level (-5V), the FET Qp is turned on and the FET Q _N is turned off, so that the power supply voltage E appears at the output terminal as it is, and the output voltage Vo becomes H level (E).

In this way, the switching circuit shown in FIG. 16 (A) has a fast response speed in both rising and falling (for example, about several n seconds), and since there is no error, the circuit configuration for a high radix such as ten values is obtained. Is also possible, and one of FET Qp and Q _N is always on, so the output resistance is small.

In Fig. 16 (A), although the voltage relationship changes,
It goes without saying that Q _N may be exchanged.

FIG. 17 shows a multi-valued theory function circuit constructed by using the switching circuit by the CMOS FET shown in FIG. 16 (A), and only a part thereof is shown.

Instead of the AND array 22 described above, pMOS AND arrays 22A and nM
An OS AND array 22B is provided. In each column line, three pMOS FETs (eg Qpx, Qpy, Qpz) are connected in series in the pMOS AND array 22A, and these FETs are derived from the programmed connection of the outputs of the decoders 31, 32, 33. Controlled by the output being burned. Similarly, nMOS
Also in the AND array 22B, three nMOS FETs (eg, Q _N x, Q _N y, Q _N z) are connected in series in each column line, and these are connected to the corresponding pMOS FET of the pMOS AND array 22A.
Respectively controlled by the decoder output applied to the. One end of each column line of the nMOS AND array 22B is grounded, and the other end is connected to the output line 5. pMOS
One end of each column line of the AND array 22A has an output line 5
, And the other end is programmatically connected to any row line of memory array 21. The decoders 31 to 33 output the bipolar control signals described above. For example, when the input x is x = 0, the output terminal of 0 of the decoder 31 is -5V, all other output terminals (1,
2,3) is + 5V. In addition, voltage sources 11A to 13 are used as signal sources.
A (for example, 1V, 2V, 3V) is adopted.

The circuit part shown in Fig. 17 shows that when x = 0, y = 2, z = 3,
It is configured to generate a voltage signal (2V) representing a function value of logical 2 at the output terminal.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a truth table of a four-value three-input multivalued logic function. FIG. 2 is a circuit diagram showing a multivalued logic function circuit that outputs a multivalued function represented by the truth table shown in FIG. 1, and FIG. 3 explains the symbols in FIG. FIGS. 4A and 4B are circuit diagrams showing examples of specific circuit configurations of the current signal source shown in FIG. FIG. 5 is a circuit diagram showing a concrete example of the decoder shown in FIG. 2 which operates in the voltage mode, and FIG. 6 shows a basic circuit for explaining the circuit of FIG. , FIG. 7 shows the relationship between the rising threshold value of the drain current of the FET shown in FIG. 5 and the threshold level of the circuit. FIG. 8 is a circuit diagram showing a specific example of the decoder operating in the current mode, and FIGS. 9A to 9D are graphs showing output signals of the circuit of FIG. FIG. 10 is a circuit diagram showing another example of the addressed switch. 11 and 12 are circuit diagrams showing a multivalued logic function circuit obtained by simplifying the circuit of FIG. 2 by making the circuit of FIG. 2 mask-programmable. FIG. 13 (A) is a diagram showing an example of a multi-function truth table, and FIG. 13 (B) is a diagram showing a correspondence relationship between four functions and values in the truth table. FIG. 14 is a circuit diagram showing an example of a multi-function circuit that realizes the truth table of FIG. FIG. 15 (A) shows an nMOS FET switching circuit, and FIG. 15 (B) shows its waveform. FIG. 16 (A) shows a CMOS FET switching circuit, and FIG. 16 (B) shows its waveform. FIG. 17 is a circuit diagram showing an example of a CMOS multilevel logic function circuit. 5 ... Output line, 10,11,12,13,11A, 11B, 13B ... Signal source, 21 ... Memory array, 22 ... AND array, 22A ... pMOS AND array, 22B ... nMOS AND array , 23 ... Addressed switch, 24 ... Sum array, 31,32, 33 ... Decoder, 61, 62, 63, 64, 65 ... Bilateral T gate.

Claims (3)

[Claims] 1. A plurality of multi-valued signal sources that generate signals respectively representing a plurality of logic values of an applied multi-valued logic, a plurality of signal lines connected to these signal sources, and a given truth. A memory array including a plurality of address lines connected to any one of the signal lines at a node by being programmed according to a value table, and any one of the above address lines by a multilevel input signal A multi-valued logic function circuit having an addressed switch for selectively turning on and off, and an output line connected to all of the address lines on the output side of the addressed switch. 2. The memory array is field programmable and the addressed switches include switching elements corresponding to all combinations of input signals. Multi-valued logic function circuit. 3. A multivalued logic function circuit according to claim 1, wherein the memory array and the addressed switches are mask programmable.