JPH0723384U - LCD panel drive circuit - Google Patents

Abstract

(57) [Summary] [Structure] In a display system such as an STN liquid crystal panel, a power supply circuit for a scan electrode drive circuit is composed of a switching block, a level shifter, and a Cockcroft block. The switching block obtains a clock from the display controller and creates a high DC voltage. The level shifter converts the clock amplitude into this high voltage and outputs it with low impedance. From this output, a pair of Cockcroft circuits creates a high voltage with the same absolute value on the + and-sides of the ground level. [Effect] Chip components can be used under the condition that the current consumption of the scan electrode driving circuit is small.
The power supply circuit for the scan electrode drive circuit is downsized. Further, since the circuit structure is simplified, the component accuracy may be low.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a power supply circuit for a scan electrode drive circuit, in particular, for a drive circuit for a liquid crystal panel.

[0002]

[Prior art]

 In the passive type liquid crystal panel, transparent scan electrode groups and signal electrode groups are arranged facing each other on the matrix with a liquid crystal layer in between, and a scan electrode drive circuit and a signal electrode drive circuit are connected to each electrode group. . A voltage averaging method is generally used for display control of a passive liquid crystal panel. In this voltage averaging method, the voltage waveform applied to the pixel has a selection period and a non-selection period, and the transmittance (on / off or intermediate gradation) is controlled by the pulse shape of the selection period.

In the voltage averaging method, when the number of divisions of the liquid crystal panel increases, the pulse crest value in the selection period also rises, and since the AC drive is required, the maximum value of the amplitude of the voltage waveform applied to the pixel is this wave. Double the high price. As a result, this voltage reaches 40 to 60 V in an STN (Super Twisted Nematic) liquid crystal panel with about 200 divisions. Since this voltage exceeds the withstand voltage of a general C-MOS IC, it is necessary to devise a driving method. As a typical method, the scan electrode driving IC and the signal electrode driving IC output a square wave that is approximately equal to the pulse peak value during the selected period, and the maximum value of the amplitude of the voltage waveform applied to the pixel is selected as the difference between these voltages. It is approximately twice the pulse peak value of the period. With this method, the withstand voltage of the IC required for driving the electrodes is halved. In addition, a pulse of-(or +) polarity can be created only by creating a high-voltage power supply on the + (or-) side with respect to the ground level VM for driving the liquid crystal panel. However, since the high withstand voltage IC has a drawback that the size becomes large and the cost becomes high, it is an obstacle to cost reduction to drive both the scanning and signal electrode driving ICs at a high voltage. In particular, since the number of signal electrodes is larger than that of the scanning electrodes, the cost reduction effect becomes great if the IC for driving the signal electrodes can be driven at a low voltage. At this time, the selection pulse is applied to the scan electrode and the display data (square wave converted into pulse width) is applied to the signal electrode, but the voltage must be applied to the scan electrode within the withstand voltage of the IC for driving the scan electrode.

The STN liquid crystal panel has a high contrast and is used not only for OA (office automation) devices mainly for still images but also for displaying moving images on televisions and the like. This STN liquid crystal panel has a severe waveform response (a phenomenon in which the optical characteristics respond to a selected waveform of a high voltage to lower the contrast), so the optimum bias method (a driving method that can obtain the maximum contrast among the voltage averaging methods) is used. The pulse crest value during the selection period may be smaller than that given in, and the crest value during the non-display period may be increased. In our experiment of driving the IC for driving the signal electrodes at a low voltage, the square wave for display data was raised to ± 2 to 3V, and the pulse peak value during the selection period was lowered to about ± 15 to 20V, but 120 divisions. The STN liquid crystal panel of the above obtained a contrast of 40 or more. Under such conditions, the operating voltage of the IC for driving the scan electrodes is 30 to 40 V, so that the IC can be realized by the C-MOS in a practical range.

In a device capable of displaying an image by simply inputting a power supply and a video signal (handled as a part; hereinafter referred to as a display unit), when a power supply that can be easily obtained is a single low voltage of about 5V. There are many. At this time, since a high voltage is used for the scan electrode driving circuit in the display unit, boosting is required. Therefore, FIG. 5 shows a typical booster circuit that has been conventionally used. Transformer system, b. Switching method, c. The Cockcroft method is illustrated.

In the transformer method of a, the transformer TR1 voltage-amplifies the clock 50 input to the primary side on the secondary side, and smoothes this with diodes D51 and D52 and capacitors C51 and C52. A DC high voltage ± Vd having the same absolute value is generated at the center of the ground level VM when driving the liquid crystal panel.

In the switching method of b, the AND A51 controls the passage of the clock 51 based on the output of the comparator CM51 and switches the transistor T51. The diode D53 and the capacitor C53 smooth the current flowing out of the coil L51 and create a direct current high voltage + Vd. The comparator CM51 compares the voltage obtained by dividing the high voltage + Vd by the resistors R51 and R52 with the intermediate terminal voltage of the brightness adjusting volume VR51. This feedback loop stabilizes the output of the high voltage + Vd. A high voltage -Vd on the negative side can be obtained by reversing the polarity of transistors, diodes, coils, etc. and the grounding direction in this circuit.

In the Cockcroft method of c, boosting is performed by a capacitor (capacitors C54 to 59) and a rectifier (diode D54 to 59). The unit block (one stage) for boosting is, for example, a portion in which capacitors C54 and C55 and diodes D54 and D55 are combined. At the cathode of the diode D55, a DC voltage obtained by adding the amplitude of the clock 52 to the ground level VM is obtained. Since there are three unit blocks in the figure, the high DC voltage + Vd is a value obtained by adding three times the amplitude of the clock to the ground level VM. A high voltage -Vd on the negative side can be obtained by reversing the polarity of the diode and the grounding direction with respect to this circuit. In this circuit, when the amplitude of the clock 42 is changed, the DC voltage + Vd also changes, so bright adjustment is performed by this method. The diodes D54 to 59 are assumed to be ideal, and voltage drop is ignored. Since capacitors and diodes can be built into ICs, they are often used as boost circuits for systems with low current consumption. In addition, if the smoothing capacitors C55, C57, and C59 are commonly grounded, it may be called a Schenkel method.

[0009]

[Problems to be solved by the device]

 Since the transformer has coils on the primary and secondary sides and a core for magnetic coupling, the transformer system has problems of larger size and heavier weight. Moreover, since the display system of the liquid crystal panel is a digital control system, it is difficult to obtain SIN waves with good conversion efficiency.

The switching method requires two sets of booster circuits to obtain a symmetrical power source on the + and − sides. Therefore, there is a problem that the number of parts increases. Further, in order to match the high voltage ± Vd of the direct current for the power source, there is a problem that high precision parts such as resistors are required.

Since the scan electrode drive circuit consumes about several mA, the clock used in the Cockcroft system must have low impedance. Therefore, there is a problem in that it is necessary to add an amplifier that changes impedance. Another problem is that the number of capacitors and diodes increases when trying to obtain a high voltage.

As described above, it is not common to display a liquid crystal panel by creating a high-voltage power supply whose absolute value is equal to the ground level VM, so that the digital control system for display should be used effectively. There is a problem that it has not been improved.

Based on the above problems, an object of the present invention is to provide a small size scan electrode in a display system of a liquid crystal panel such as STN, in which a high voltage having an equal absolute value around a ground level VM can be easily obtained. A power supply circuit for a drive circuit is provided.

[0014]

[Means for Solving the Problems]

 To achieve the above object, the present invention provides a liquid crystal panel driving liquid crystal panel, which generates a driving signal of positive and negative potentials with respect to a reference potential in a scan electrode driving circuit based on a signal of a display controller. In the panel drive circuit, the scan electrode drive circuit is provided with a switching circuit as the power supply section, and a boosting clock signal generated from the display controller is input to generate a DC voltage higher than the amplitude of the clock signal. A switching block to generate, a level shifter that uses the DC voltage as a power supply voltage, inputs a level shift clock from the display controller, and outputs a clock whose amplitude is the voltage value of the DC voltage, and outputs the level shifter. The clock is input to the Cockfloft circuit provided on the positive and negative sides of the reference level, and the voltage value of the amplitude of the clock is approximately positive. Characterized by being composed of a Cockcroft block for outputting a fine negative DC voltage.

[0015]

First Embodiment FIG. 1 is a circuit diagram of a first embodiment of the present invention, which is divided into a switching block 1, a level shifter 2 and a Cockcroft block 3. The switching block 1 is composed of an AND gate A1 for a gate, an inverter I1 for a comparator, resistors R1-3, capacitors C1-2, a volume VR1 for brightness adjustment, a coil L1, a transistor T1, and a diode D1. The power source of the AND A1 and the inverter I1 is 5V, which is common to the power source side of the coil L1. The level shifter 2 is composed of a resistor R4, capacitors C3 and C4, and transistors T2 and T3. The Cockcroft block is composed of capacitors C5-8 and diodes D2-5. The operation of each block will be described below.

[Operation of Switching Block] The AND A1 controls the passage of the clock 5 output from the display controller 17 based on the logic level of the inverter I1 (in the figure, the AND controller A1 and the inverter I1 are connected to the display controller 17). The internal elements are shown). The capacitor C 1 is called a speed-up capacitor, and quickly transfers the output change of the AND A 1 to the base of the transistor T 1. The resistor R1 limits the base current of the transistor T1. The transistor T1 is switched by the clock that has passed through the AND A1 via the capacitor C1 and the resistor R1. The coil L1 generates a high voltage pulse when the collector current is cut off, and is smoothed by a diode D1 and a capacitor C2 to obtain a DC high voltage 4. The resistors R2 and R3 determine the voltage variable range of the intermediate terminal of the volume VR1. When the DC high voltage 4 rises and the intermediate terminal voltage of the volume VR1 exceeds the change voltage of the inverter I1, the output of the inverter I1 is inverted to the low level and the switching operation of the transistor T1 is stopped. On the contrary, when the intermediate terminal voltage is equal to or lower than the change voltage of the inverter I1, the output of the inverter I1 becomes high level, the switching operation continues, and the high DC voltage 4 rises. By this negative feedback circuit, the stabilized high DC voltage 4 corresponding to the intermediate terminal voltage of the brightness adjusting volume VR1 is obtained. To prevent the transistor T1 from running out of control, a protective resistor is inserted in the emitter.

[Operation of Level Shifter] The capacitors C3 and C4 are for blocking direct current. The resistor R4 creates a path for the base current to flow. When the time constant of the capacitor C3 (or C4) and the resistor R4 is longer than the clock period, the transistors T2 and T3 operate as almost complementary switches, and when the transistor T2 is on (off), T3 is off. (On). As a result, the level-shifting clock 5 input with an amplitude of 5V is converted into the amplitude of the above-described DC high voltage 4 (hereinafter referred to as VA) (the phase is inverted). When the current load of the circuit in the subsequent stage is large, the resistance R4 is reduced to increase the collector current to cope with it. Further, in this embodiment, the clock 5 is used for both the boosting clock and the level shifting clock.

[Operation of Cockcroft Block] The output of the level shifter 2 is input to the cathode side of the diode D2 via the capacitor C5. The cathode voltage of the diode D2 has a value that is only a diode drop Vdrop (voltage drop generated when a current flows through the diode D2) from the ground level VM. As a result, the lowest potential of the cathode of the diode D2 becomes (VM-Vdrop) and the highest potential thereof becomes (VM-Vdrop + VA). When this is smoothed by the diode D3 and the capacitor C6, the + side power source of the scan electrode drive circuit 26 + Vd = VM-2Vdrop + VA is obtained. Similarly, the − side power source −Vd = VM + 2Vdrop−VA is obtained. The capacitors C6 and C8 in the figure are connected to the liquid crystal ground level. This may be grounded to the system ground, and in this case it is sometimes called the Schenkel method, but no particular distinction is made. Since the circuit voltage is 30 V and the current consumption is about 1 mA, considering the scan electrode drive circuit 26 as an equivalent resistance of about 30 KΩ, when the capacitance of each of the capacitors C5 to C8 is set to 1 μF, the time constant becomes 30 ms. If the clock cycle is set to several tens KHz or more, the ripple of high voltage ± Vd becomes small.

FIG. 2 shows a display unit of a liquid crystal panel 28 to which the power supply circuit of FIG. 1 is applied. Components and signals common to those in FIG. 1 are indicated by the same numbers and alphabets. A power supply of 5V and 0V and a video signal 10 are input to this display system. The video signal 10 is converted into the RGB signal 12 by the chroma circuit 11, and the sync signal 14 is separated by the sync separation circuit 13. The display controller 17 surrounded by a thick line is provided with a clock 5 for boosting and level shifting, in addition to the A / D converter 18, the display control block 19 and the oscillator 20 which are built in a general liquid crystal television controller. The frequency divider 21 to be created, the anode A1 and the inverter I1 are built in. The resistors R5 to R8 and the capacitors C9 to C11 create the voltages VS +, VM, and VS-. In the signal electrode drive circuit 27, the logic circuit operates from 0 to 5 V, and the voltages above and below the square wave for display data correspond to VS + and VS-. In the control signal group 23, signals used in the scan electrode driving circuit 26, such as a scanning clock, a start signal, and drive polarity control, are converted by the level shifter 24 into high-voltage power source ± Vd amplitudes.

Second Embodiment FIG. 3 shows a circuit in which the polarity is inverted from that of the first embodiment. Parts corresponding to those in the first embodiment are indicated by adding 1 after the numbers following the alphabet. The gate is a negative logic AND 11 (OR in positive logic) and controls the passage of the clock B. The transistor T11 is changed to PNP, and the direction of the diode D11 is reversed. The capacitor C21 and the coil L11 are grounded to 0V. As a result, a negative high voltage VB is obtained. This is divided between 5V and bright adjustment is performed. The emitters of the level shift transistors T21 and T31 are connected to 5V and VB, respectively. The Cockcroft block is the same as that in the first embodiment.

Third Embodiment FIG. 4 shows a level shifter having a circuit configuration different from those of the first and second embodiments. The level shift clock 41 is input to the bases of the transistors T41, 42 via capacitors C41, C42 and resistors R41, 42. This is level-shifted to a high DC voltage 42 by transistors T41 and T42, and an output 43 with the polarity reversed is obtained. The capacitor C42 is just for speeding up. On the other hand, the capacitor C41 also has a function of holding the transistor T41 base bias voltage, and clamps the level shift clock 41 near the high voltage 42.

Although any type of diode may be used, a Schottky type diode having a small voltage drop is preferable in consideration of utilization efficiency of a power supply. In the first and second embodiments, the collector current always flows through the level shifter when the clock stops. To avoid this, add a resistor to the base so that either transistor turns off when the clock is stopped. Further, when temperature compensation of the drive voltage is performed, a thermistor may be used for one of the dividing resistors in the switching block.

[0023]

[Effect of device]

 In the present invention, as a countermeasure against the waveform response of the STN liquid crystal panel, the method of shifting the drive voltage from the optimum bias condition and lowering the drive voltage of the scan electrode drive circuit is actively used. As a result, the scan electrode driving circuit can be used within the rated range of the normal high breakdown voltage C-MOS, even though there are two power sources of ± with respect to the ground level VM. In the present invention, three known circuit blocks are combined for boosting. Even if this method is adopted as a general power supply circuit, the voltage drop of the level shift block and the cockcroft block is not fed back, so the accuracy of the output voltage deteriorates, and when trying to draw a large current, it is necessary to increase the capacity of the capacitor. Therefore, there is little merit in the circuit. In addition to this reason, a system using two power supplies of ground level VM and ± is not common due to the IC withstand voltage, so an example of applying the circuit system of the present invention to the display system of the STN liquid crystal panel. There is no. However, in the display system of the STN liquid crystal panel, since the current consumption of the scan electrode drive circuit is several mA or less, it is not necessary to consider the voltage drop. Moreover, since the ± 2 power supply voltage only needs to have the same absolute value with respect to the ground level, the precision of components such as resistors can be low. As described above, the power supply circuit of the present invention can be made almost fixed parts, and fine adjustment is not required, so that manufacturing and maintenance are significantly simplified.

In addition to the above effects, the present invention further has the following effects. Since the current consumption of the scan electrode drive circuit is several mA or less, the capacity of the capacitor is 0.1 to 1.0 μF or less. As a result, chip components can be used for transistors, diodes, resistors and capacitors. Clocks for switching and level shifting are created in the display controller. The gate of the switching clock and the comparator for determining the voltage value can be built into the display controller. Since the switching circuit is single, only one coil is needed as a large component. The level shifter is also used for current amplification. The Cockcroft circuit may have one stage on the + and-sides. For these reasons, the circuit becomes smaller.

It should be noted that the scan electrode driving IC can be used within the withstand voltage range and can be applied to an active type liquid crystal panel such as a TN liquid crystal panel, MIM, TFT or the like as long as it has low power dissipation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram showing an application example of the first embodiment of the present invention to a display unit.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of Embodiment 3 of the present invention.

FIG. 5 is a circuit diagram of a booster circuit of a conventional example, in which (a) is a transformer system, (b) is a switching system, and (c) is a Cockcroft system.

[Explanation of symbols]

A1, A2, A51 & I11, I12 Inverters used as comparators C1 to C8 Capacitors R1 to R4 Resistances VR1 Volume L1 Coils D1 to D5 Diodes T1 to T3 Transistors + Vd Power supply voltage on the + side of the scan electrode drive circuit VM For liquid crystal display Ground level -Vd Power supply voltage on negative side of scan electrode drive circuit 1 Switching block 2 Level shifter 3 Cockcroft block 4 DC high voltage 17 Display controller 26 Scan electrode drive circuit 29 Liquid crystal panel

Claims (2)

[Scope of utility model registration request] 1. A drive circuit of a liquid crystal panel, which drives a liquid crystal panel by generating drive signals of positive and negative potentials with respect to a reference potential in a scan electrode drive circuit based on a signal of a display controller, The power supply part of the scan electrode drive circuit
A switching block that includes a switching circuit and that receives a boosting clock signal generated from a display controller to generate a DC voltage having a voltage higher than the amplitude of the clock signal; and a level shift from the display controller that uses the DC voltage as a power supply voltage. For inputting a clock for input, a level shifter for outputting a clock whose amplitude is the voltage value of the DC voltage, and a clock output from the level shifter are input to a Cockfloft circuit provided on the positive and negative sides of the reference level. And a Cockcroft block that outputs a positive and a negative DC voltage of a voltage value of the amplitude of the clock, and a driving circuit for a liquid crystal panel. 2. The switching block includes a comparator for detecting an output DC voltage, a gate for controlling passage of a clock based on the output of the comparator, a transistor switched by the output of the gate, and a collector of the transistor. A coil that is connected and that generates a high voltage pulse by switching current, a circuit that includes a diode and a capacitor that smoothes the high voltage pulse and generates a high DC voltage, and divides the high DC voltage by the comparator. 2. The drive circuit for a liquid crystal panel according to claim 1, further comprising a resistor that generates a voltage to be output to.