JPH07227086A - Failure detection system of inverter - Google Patents

Abstract

PURPOSE:To achieve a system for detecting the failure of an inverter by extremely reducing the possibility of erroneous detection. CONSTITUTION:The title system is provided with a comparator 30 for outputting 'H' level when the deviation output between a current command value and a current feedback value is equal to or more than a set value, a saturation detector 32 for outputting 'H' level when the operating point of a limiter circuit 27 is at a saturation region, and an AND circuit 33 for detecting a current control system failure when the output is at 'H' level by the comparator 30 and the saturation detector 32, thus preventing an erroneous detection of failure on transition where the current command value drastically rises.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter failure detection system for driving and controlling an induction motor or the like.

[0002]

2. Description of the Related Art Various types of inverter failure detection methods have been conventionally developed. For example, in Japanese Unexamined Patent Publication No. 62-290362, a difference between a reference sine wave signal which is a control command and an output voltage signal is calculated, and the level of the difference signal is compared with an abnormal voltage set value to detect a failure. By doing so, a technology that enables high speed detection is disclosed. Further, Japanese Patent Laid-Open No. 2-299421 discloses a detection method similar to the above-mentioned publicly known material, mainly for the purpose of overload detection.

Further, for example, in Japanese Unexamined Patent Publication No. 2-65668, a sensor system is included by comparing a current reference signal with an output current feedback signal and generating a failure signal when the comparison result exceeds a predetermined value. Also disclosed is a technique capable of detecting a wide range of failures.

[0004]

However, the above-described inverter failure detection method known in the related art as described above is more difficult to detect than the prior method in which failure detection is performed only from the detected values of output voltage and output current. The sensitivity is increased, and as a result, it is possible to realize fault detection in a wide range of high speed, but when applied to a specific control device adopted in this kind of inverter, there is a problem in relation to its control operation characteristics and the like. Occur. That is, although it is related to the control response characteristic, for example, when the voltage command value changes rapidly due to some request, it is erroneously determined that an abnormality has occurred even though there is no abnormality in the device operation in the target range. Alarm display, load shedding, device stoppage, etc., which are executed based on this, are actually performed, resulting in unnecessary damage.

The present invention has been made to solve the above problems, and an object thereof is to provide an inverter failure detection system capable of reducing the possibility of false detection as much as possible. Further, the present invention realizes the prevention of the above-mentioned erroneous detection by the current control system and the voltage control system of the inverter control circuit,
Furthermore, the range of failure occurrence at the time of failure detection is limited. Further, the present invention is intended to realize the above-mentioned erroneous detection in a circulating current control system adopted in a control circuit of a multiplex system inverter in which output sides of a plurality of inverters are connected in parallel with each other. Further, the present invention is intended to realize, with high reliability, failure detection of a current control system and a voltage control system in a control circuit of an inverter that outputs a three-phase AC voltage and current. Another object of the present invention is to detect a DC voltage balance abnormality in a so-called three-level inverter with high reliability.

[0006]

According to a first aspect of the present invention, there is provided an inverter failure detecting method, which is a comparing means for determining whether or not a deviation output between a current command value and a current feedback value is a predetermined set value or more, Saturation detecting means for determining whether or not the operating point of the limiter circuit is in a saturation region, and outputs from the comparing means and the saturation detecting means, the deviation output is equal to or more than the predetermined set value, and the limiter circuit is input. When the operating point is in the saturation region, the failure detecting means for detecting an abnormality in the current control system is provided.

The inverter failure detection method according to a second aspect of the present invention is the inverter detection method according to the first aspect, which is further inserted between the comparison means and the failure detection means, and the output from the comparison means is equal to or longer than a predetermined set time. It is equipped with a timer setting device that outputs when it continues.

According to a third aspect of the present invention, there is provided an inverter failure detection method, wherein an adder for calculating a deviation between a voltage command value from a limiter circuit and a voltage feedback value, and a deviation output from the adder is a predetermined set value or more. Comparing means for determining whether or not the operating point of the limiter circuit is in a saturation region, saturation detection means for determining whether or not the operating point of the limiter circuit is in a saturation region, and outputs of the comparing means and the saturation detecting means are input to obtain the deviation output. There is provided failure detection means for detecting as an abnormality of the voltage control system when the operating point of the limiter circuit is not within the saturation region above a predetermined set value.

Further, the inverter failure detecting method according to claim 4 is the same as in claim 3, wherein the inverter detecting method is further inserted between the comparing means and the failure detecting means, and the output from the comparing means is equal to or longer than a predetermined set time. It is equipped with a timer setting device that outputs when it continues.

According to a fifth aspect of the present invention, there is provided an inverter failure detection system in which current control is performed by inputting outputs from the failure detection means according to claim 1 or 2 and the failure detection means according to claim 3 or 4. It is provided with failure detection means for detecting an abnormality of the feedback current detector when a system abnormality is detected and no voltage control system abnormality is detected.

According to a sixth aspect of the present invention, there is provided an inverter failure detection method, wherein a first output calculating means for calculating an input of the electric motor from an output voltage and an output current, and a speed of the electric motor detected by a torque and a speed detector. A second output calculation means for calculating the output of the electric motor from the feedback value and a deviation of the outputs of the first and second output calculation means, and when the deviation is a predetermined set value or more, the speed detector It has a failure detection means for detecting it as an abnormality.

According to a seventh aspect of the present invention, there is provided an inverter failure detection method, wherein a first output computing means for computing an input of the electric motor from an output voltage and an output current, and a speed of the electric motor detected by a torque and a speed detector. The deviation of the outputs of the second output calculating means for calculating the output of the electric motor from the feedback value and the output of the first and second output calculating means is calculated, and the deviation of a predetermined set value or more continues for a predetermined set time or more. In this case, failure detection means for detecting an abnormality of the speed detector is provided.

According to an eighth aspect of the present invention, there is provided an inverter failure detection system, wherein neither the failure detection means of claim 1 or 2 nor the failure detection means of claim 3 or 4 detects a failure, and When the failure detecting means according to claim 6 or 7 detects a failure, it is provided with failure detecting means for detecting an abnormality of the speed detector.

According to a ninth aspect of the present invention, there is provided an inverter failure detection method in which an operating point of a comparison means and a limiter circuit for determining whether or not a feedback value of a circulating current flowing in a parallel circuit of a multi-system inverter is equal to or more than a predetermined set value. The saturation detection means for determining whether or not it is in the saturation region, and the outputs from the comparison means and the saturation detection means are input, and the circulating current feedback value is equal to or more than the predetermined set value and the operating point of the limiter circuit is A failure detecting means for detecting an abnormality of the circulating current control system when in the saturation region is provided.

Further, the inverter failure detecting method according to claim 10 is further inserted in the claim 9 between the comparing means and the failure detecting means, and the output from the comparing means continues for a predetermined set time or longer. It is equipped with a timer setting device that outputs when it does.

According to the eleventh aspect of the inverter failure detection method of the present invention, the deviation between the current command value and the current feedback value of each phase of the inverter that outputs a three-phase AC voltage and current or the current feedback value of each phase is added. Then, there is provided a failure detecting means for detecting a zero-phase current and detecting an abnormality of the current control system or an inverter ground fault when the zero-phase current is equal to or more than a predetermined set value.

According to a twelfth aspect of the present invention, the inverter failure detection method detects a zero-phase current by adding the deviation between the current command value of each phase and the current feedback value or the current feedback value of each phase to detect a zero-phase current. The present invention is provided with a failure detecting means for detecting an abnormality of the current control system or an inverter ground fault when the zero-phase current of a set value or more continues for a predetermined set time or more.

According to a thirteenth aspect of the present invention, there is provided a fault detection method for an inverter, which further comprises a ground fault detector for detecting a ground fault of the inverter output circuit, and the fault detection means according to the eleventh or twelfth aspect detects an abnormality. Moreover, when the ground fault detector does not detect a ground fault, it is provided with a failure detecting means for detecting an abnormality in the current control system.

According to a fourteenth aspect of the present invention, there is provided an inverter failure detection method in which a deviation between a voltage command value and a voltage feedback value of each phase of an inverter which outputs a three-phase AC voltage or current or a voltage feedback value of each phase is added. Then, there is provided a failure detecting means for detecting the zero-phase voltage and detecting an abnormal voltage control system or an inverter ground fault when the zero-phase voltage is equal to or higher than a predetermined set value.

According to a fifteenth aspect of the present invention, in the inverter failure detection method, the deviation between the voltage command value and the voltage feedback value of each phase or the voltage feedback value of each phase is added to detect a zero-phase voltage and a predetermined value is detected. It is provided with a failure detecting means for detecting an abnormality of the voltage control system or an inverter ground fault when the zero-phase voltage above the set value continues for a predetermined set time or longer.

According to a sixteenth aspect of the present invention, there is provided an inverter failure detection method, wherein a voltage detector for detecting a voltage between electrodes of each capacitor on the DC power supply side of a three-level inverter and an addition for calculating a deviation of outputs from these voltage detectors. And a failure detecting means for detecting a DC voltage balance abnormality when the deviation output from the adder is equal to or greater than a predetermined set value.

According to a seventeenth aspect of the present invention, there is provided an inverter failure detection system in which a voltage detector for detecting a voltage between electrodes of each of the capacitors, an adder for calculating a deviation between outputs of these voltage detectors, and an adder A failure detection means is provided for detecting a DC voltage balance abnormality when a deviation output of a predetermined set value or more is continuously output for a predetermined set time or more.

[0023]

In the inverter failure detection method according to the first aspect of the present invention, the operating point of the limiter circuit is not in the saturation range even if the deviation output between the current command value and the current feedback value exceeds the set value. As long as there is no failure detection. Therefore, the possibility of an erroneous detection operation due to a sudden change in the control command value is reduced.

Further, in the inverter failure detection method according to the second aspect of the present invention, the failure is detected when the deviation output of the set value or more continues for the set time or more. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

In the inverter failure detection method according to the third aspect of the present invention, even if the deviation output between the voltage command value and the voltage feedback value exceeds the set value, if the operating point of the limiter circuit is in the saturation region. No fault is detected. Therefore, the possibility of an erroneous detection operation that may occur when the limiter circuit enters the saturation region and the output voltage command value becomes nonlinear is reduced.

Further, in the inverter failure detection method according to the fourth aspect of the present invention, when the deviation output of the set value or more continues for the set time or more, the failure is detected. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

Further, in the inverter failure detection method according to the fifth aspect, the failure is detected when the current control system abnormality is detected while the voltage control system abnormality is not detected. The target can be limited to the feedback current detector.

Further, in the inverter failure detection method according to the sixth aspect, the speed feedback value is obtained when the deviation between the motor input obtained from the voltage and current and the motor output obtained from the speed feedback value is equal to or more than a set value. It is judged as abnormal.

Further, in the inverter failure detection method according to the seventh aspect of the present invention, when the deviation output of the set value or more continues for the set time or more, the failure is detected. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

Further, in the inverter failure detection method according to the present invention, when the speed detector abnormality is detected in a state where neither the current control system abnormality nor the voltage control system abnormality is detected, it is judged that the speed detector abnormality is present. Therefore, in this case, the failure occurrence target can be surely limited to only the speed detector.

Further, in the inverter failure detection method according to the ninth aspect, even if the circulating current feedback value exceeds the set value, failure detection is not performed unless the operating point of the limiter circuit is in the saturation region.

Further, in the inverter failure detection method according to the tenth aspect of the present invention, when the feedback value output of the set value or more continues for the set time or more, the failure is detected. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

Further, in the inverter failure detection method according to the eleventh aspect, when the zero-phase current is equal to or more than the set value, it is detected as an abnormality of the current control system or an inverter ground fault.

Further, in the inverter failure detection method according to the twelfth aspect of the present invention, when the zero-phase current detection output of a set value or more continues for a set time or more, it is detected as a failure. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

Further, in the inverter failure detection method according to the thirteenth aspect, when the ground fault detector detects the zero-phase current abnormality without detecting the ground fault, it is determined that the fault occurs. The failure target can be limited to the current control system.

Further, in the inverter failure detecting method according to the fourteenth aspect, when the zero-phase voltage is equal to or higher than the set value, it is detected as an abnormality of the voltage control system or an inverter ground fault.

Further, in the inverter failure detection method according to the fifteenth aspect, the failure is detected when the zero-phase voltage detection output of the set value or more continues for the set time or more. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

Further, in the inverter failure detecting method according to the sixteenth aspect, when the deviation output of the capacitor voltage is equal to or more than the set value, it is detected as the DC voltage balance abnormality.

Further, in the inverter failure detection method according to the seventeenth aspect, it is further detected as a failure when the deviation output of the set value or more continues for the set time or more. Therefore, for example, erroneous detection due to a harmonic component or the like generated by control is prevented.

[0040]

【Example】

Example 1. First Embodiment FIG. 1 shows an inverter failure detection system according to a first embodiment of the present invention and is an overall configuration diagram of an inverter device for driving a three-phase induction motor. In the figure, 1
Is a smoothing capacitor connected between both pole terminals of a DC power supply (not shown), 2 is a power transistor 2T and a diode 2D connected in antiparallel to this are arms and U,
This is an inverter main circuit configured to connect V and W three-phase bridges and outputting variable voltage / variable frequency AC power. Note that the V-phase and W-phase arm elements are similar to the U-phase and are not shown. Reference numeral 3 is a three-phase induction motor driven by receiving the output voltage and the output current from the inverter main circuit 2.

Reference numeral 10 is a speed detector for detecting the rotation speed of the induction motor 3, and 11 is a current detector for detecting the output current of each phase of the inverter main circuit 2 and outputting it as a current feedback value. Reference numeral 20 is an inverter control circuit that finally sends out a gate signal for on / off controlling the power transistor 2T of each arm of each phase of the inverter main circuit 2 based on the speed command value. Here, PWM control adopting a so-called vector control method is used. The circuit will be described below as an example. In addition, the internal configuration is related to the description of the failure detection means of each embodiment,
As necessary, necessary components are extracted and specifically illustrated, and the rest are displayed in the form of a black box.

Therefore, first, the entire inverter control circuit 20 not including the failure detecting means will be described in detail with reference to FIG. In the figure, first, the adder 21 calculates the deviation between the speed command value and the speed feedback value, and the deviation output is amplified by the speed controller 22 and output as the torque current command value (I _q ). Reference numeral 23 is a limiter circuit having saturation characteristics above a certain value in order to keep the torque current command value within a certain range from the current rating of the inverter main circuit 2. The torque current command value (I _q ) from the limiter circuit 23 and the exciting current command value (I _d ) created by a field setting device (not shown) are converted by the 2-phase / 3-phase converter 24 and the U phase, V Is output as the phase and W-phase current command values.

The expression shown in the lower part of the figure is an arithmetic expression processed by the 2-phase / 3-phase converter 24, where ω is an angular velocity synchronized with the output power supply frequency.

In the following, taking the U phase as an example, the adder 25 takes the deviation between the U phase current command value and the U phase current feedback value and inputs it to the current controller 26 for current control (for example, PI operation, PID operation control) and output as a U-phase voltage command value. Further, with respect to this output, a limiter circuit 27 is provided in order to keep the voltage command value within a certain range so that a voltage higher than the rating of the inverter main circuit 2 is not output, and this output is converted into a gate signal by the PWM control circuit 28. It is sent to the inverter main circuit 2.

Next, returning to FIG. 1, the failure detecting means, which is an essential part of the first embodiment of the present invention, will be described. In the figure,
Reference numeral 30 is a comparator as a comparison means for setting the output to the "H" level when the deviation output from the adder 25 is equal to or more than the set value from the level setter 31 (usually set to about 10% of the rating),
Reference numeral 32 designates the output when the operating point of the limiter circuit 27 which limits the output from the current controller 26 is in the saturation region.
Saturation detector as saturation detection means for setting to H "level, 3
Reference numeral 3 is an AND circuit as a failure detecting means which operates by receiving output signals from the comparator 30 and the saturation detector 32.

Next, the failure detection operation will be described. If the deviation output from the adder 25, that is, the deviation between the current command value and the current feedback value exceeds the set value from the level setter 31 even at an instant, the comparator 30 outputs a signal that can be estimated to be a failure. It is the same as before. However, in the present invention, the output of the comparator 30 alone is not used to determine that a failure has occurred, but the output from the saturation detector 32 is also used to determine that a failure has occurred. That is, when the output level of the current controller 26 which inputs the deviation output and performs the PID operation or the like is equal to or higher than the saturation region setting level of the limiter circuit 27, it is determined that a failure has occurred on the AND condition.

By adding the output of the saturation detector 32 to the AND condition as described above, it is possible to avoid an erroneous detection operation which is likely to occur at the transition of the rising of the apparatus. That is, when the current command value sharply rises from zero at the start, the deviation output from the adder 25 naturally increases sharply, and the comparator 30
Output becomes "H" level. However, the output of the current controller 26 is normally suppressed below the saturation region setting level of the limiter circuit 27 by the integral element. Therefore,
The output of the saturation detector 32 maintains the "L" level, and the output of the AND circuit 33 also maintains the "L" level.

After that, when the induction motor 3 normally increases its speed, the current feedback value also gradually rises, and the adder 2
The deviation output from 5 gradually decreases and the current controller 2
The output of 6 is also maintained within a level within the unsaturated region of limiter circuit 27. That is, even if the temporary comparator 30 operates, the AND circuit 33 does not operate and erroneous detection is prevented.

However, for example, if a defect occurs in the current detector 11 and the current feedback value continues to be abnormal, the comparator 30 will of course continue to operate, but the output of the current controller 26 will also gradually increase, and eventually the limiter circuit. The saturation detector 32 operates beyond the saturation level setting level of 27 and the AND circuit 3
3 performs failure detection. In this case, the current control system is output as an abnormality, but specifically, an abnormality of the current detector 11 and an abnormality of the inverter main circuit 2 can be considered. Although the U phase shown in the figure has been described above, the same applies to the V phase and the W phase.

Example 2. FIG. 3 shows an inverter failure detection system according to a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that a timer setting device 34 is inserted between a comparator 30 and an AND circuit 33. Only. That is,
In the second embodiment, the output from the comparator 30 is the time set by the timer setter 34 (for example, about 10 mS).
The output is sent to the AND circuit 33 for the first time continuously. With this, the following effects can be expected.

That is, the voltage output from the inverter main circuit 2 has a pulse-like waveform, and the current flowing by this also contains many harmonic components. Therefore, the comparator 30, which operates based on the current deviation output from the adder 25, is also likely to malfunction due to this harmonic component. Therefore, by additionally providing the timer setter 34 that operates under the condition that the output is continued for a certain period of time or more, it is possible to avoid the fault erroneous detection operation particularly due to the harmonic component of the detection signal.

Example 3. 4 is an overall configuration diagram showing an inverter failure detection system according to a third embodiment of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions, but this embodiment detects an abnormality in the voltage control system. In the figure, 12 is a voltage detector that detects the output voltage of each phase of the inverter main circuit 2 and outputs it as a voltage feedback value. Reference numeral 35 is an adder for calculating the deviation between the U-phase voltage command value from the limiter circuit 27 and the U-phase voltage feedback value from the voltage detector 12, and 36 is the deviation output from the adder 35 set by the level setter 37. A comparator serving as a comparing means for setting the output to the "H" level when the value is equal to or more than a value, a saturation detector 38 serving as a saturation detecting means for setting the output to the "H" level when the operating point of the limiter circuit 27 is in the saturation region, Reference numeral 39 is a knot circuit that inverts and outputs the input signal level, and 40 is a comparator as a failure detecting means that operates by receiving the output signals from the comparator 36 and the knot circuit 39.

Next, the operation of failure detection will be described. The deviation output from the adder 35, that is, when the deviation between the voltage command value and the voltage feedback value becomes equal to or more than the set value from the level setter 37 even at an instant, the comparator 36 outputs a signal that can be estimated to be a failure occurrence. Is the same as the conventional one. However, in the present invention, the output of the comparator 36 alone is not used as the final determination that a failure has occurred, but the output from the knot circuit 39 is also used as a condition (comparator 40) to determine that a failure has occurred. That is, the operating point of the limiter circuit 27 that keeps the voltage command value within a certain range is not in the saturation region, and therefore, when it is not in the saturation region, it is determined that a failure has occurred by the AND condition.

The reason why the operating point of the limiter circuit 27 is not in the saturation region is added to the AND condition as described above. That is, when the voltage limiter is not applied, the relationship between the voltage command value and the voltage feedback value becomes linear, and a normal control operation is performed in which the voltage feedback value follows the voltage command value, but when the voltage limiter is applied. In the case of PWM voltage control, the signal wave that is the voltage command value becomes equal to or higher than the peak value of the triangular wave of the modulation wave, and the relationship between the voltage command value and the voltage feedback value becomes non-linear, and the voltage output that matches the voltage command value cannot be obtained. A considerable amount of deviation is output from the adder 35. Therefore, in order to prevent such a case from being detected as a failure, the output of the saturation detector 38 is inverted by the knot circuit 39 and input to the comparator 40.
Is to be inoperative.

On the other hand, if the deviation output from the adder 35 exceeds the set value without being applied to the voltage limiter, it is assumed that the voltage detector 12 or the inverter main circuit 2 is abnormal. Is detected by the comparator 40.

Example 4. FIG. 5 shows an inverter failure detection system according to a fourth embodiment of the present invention. The difference from the third embodiment shown in FIG. 4 is that a timer setter 41 is inserted between the comparator 36 and the comparator 40. Only. In this case as well, as in the case of the second embodiment, there is an effect that the fault erroneous detection operation due to the harmonic component of the detection signal can be avoided.

Example 5. FIG. 6 shows a main part of an inverter failure detection system according to a fifth embodiment in which the targets of failure occurrence at the time of detection are limited by combining the above embodiments.
That is, a knot circuit 42 and an AND circuit 43 are added,
The outputs of the current control system abnormality of the first or second embodiment and the voltage control system abnormality of the third or fourth embodiment are directly output for the former.
The latter is input to the AND circuit 43 via the knot circuit 42, and failure is detected as an abnormality in the current detector when the AND condition is satisfied.

As described above, when the abnormality of the current control system is detected, the abnormality of the inverter main circuit 2 or the current detector 11 is assumed, but when the former inverter main circuit 2 is abnormal, the voltage control system is also abnormal. It is output and the condition of the AND circuit 43 is not satisfied. Therefore, what is detected by the AND circuit 43 is limited to the latter case where the current detector 11 is abnormal.

Although not shown in the drawing, the same idea is applied.
By connecting the output of the voltage control system abnormality directly and the output of the current control system abnormality to the AND circuit 43 via the knot circuit 42, it is possible to separately detect the abnormality of the voltage detector 12. Is.

Example 6. FIG. 7 shows an overall configuration of an inverter failure detection system according to a sixth embodiment of the present invention.
In particular, it detects an abnormality of the speed detector 10. In the figure, an output calculator 44 as a first output calculator
Is the output of the inverter from the phase output currents I _U , _IV , I _W and the phase output voltages V _U , V _V , V _W detected by the current detector 11 and the voltage detector 12, respectively, and the output of the inverter = the input of the induction motor. = P1 is calculated. The calculation formula is shown below. P1 = I _U × V _U + I _V × V _V + I _W × V _{W Further} , the output calculator 45 as the second output calculating means is
The output of the induction motor = P2 is calculated from the speed feedback value ω _r of the induction motor 3 detected by the speed detector 10 and the torque T calculated by the inverter control circuit 20. The calculation formula is shown below. P2 = T × ω _r where the torque T is obtained from the torque current I _q , the magnetic flux Φ, and the torque coefficient KI determined by the induction motor by the following equation. T = KI × Φ × I _q

Since P1 shown in the above equation is the input of the induction motor 3 and P2 is the shaft output of the induction motor 3, there is a copper loss (loss due to the internal resistance of the motor) P of the induction motor 3 between them. There is a difference of _r . That is, P1 = P2 + P _r However, P _r is as small as about 1% with respect to P2 at the time of rating,
In the failure detection described below, it can be practically ignored by considering the value of P _{r in} the set value at the time of detection.

That is, the fault detection is performed by the dual output computing units 44, 4
The deviation of the output of 5 is calculated by the adder 46, and the comparator 47
Then, it is determined whether or not the deviation output is equal to or more than the set value from the level setter 48. This setting value is 5 of the rating.
10% is selected, and a fault is detected when the deviation output exceeds the set value even for an instant. Then, this failure detection is performed in P1, P
Since the inputs required for the calculation of 2 are variables that can be obtained from the voltage and current of the inverter output except for the speed of the induction motor, the increase in the deviation output is judged to be due to the abnormality of the speed detector 10. is there.

Example 7. FIG. 8 is an overall configuration diagram showing an inverter failure detection method according to a seventh embodiment of the present invention. The only difference from the seventh embodiment shown in FIG. 7 is that a timer setting device 49 is inserted on the output side of the comparator 47. . That is, the comparator 47
When the detection output of No. 2 continues for the time set by the timer setting unit 49 or more, it is determined that the speed detector is abnormal. As a result, as described in the second embodiment and the like, it is possible to avoid the fault erroneous detection operation due to the harmonic component of the detection signal.

Example 8. [Embodiment 8] FIG. 9 is an overall configuration diagram showing an inverter failure detection method according to Embodiment 8 of the present invention.
Here, the AND circuit 50 is inserted on the output side of the timer setter 49 at the final stage in FIG. Then, the AND circuit 50 receives the inverted signals of the output of the current control system abnormality of the first or second embodiment and the output of the voltage control system abnormality of the third or fourth embodiment. If there is an abnormality in the current control system or the voltage control system in the previous Example 7, the value of the motor input / output calculated from the output voltage and current becomes unreliable. In this case, the deviation output is large. Even if the error occurs, the failure detection is not performed, and only when both the current control system and the voltage control system are normal, it is output as an abnormality of the speed detector.

As a result, it is possible to surely limit the failure occurrence target at the time of failure detection to only the speed detector. In addition,
Although the AND circuit 50 is added to the circuit of FIG. 8 here, the AND circuit 50 may be added to the circuit of FIG. 7 not using the timer setter 49.

Example 9. FIG. 10 is an overall configuration diagram showing an inverter failure detection system according to a ninth embodiment of the present invention. Here, two inverter main circuits 2A and 2B
Are connected in parallel through the reactor 4 via a reactor 4 to form a multi-system inverter that supplies electric power to the common induction motor 3. Hereinafter, a description will be given focusing on the circulating current of the multiplex system inverter (the output current difference between the two main inverter circuits 2A and 2B is equivalent). This circulating current control system is also configured in the inverter control circuit 20.

In the figure, 51 is the deviation between the current feedback value on the inverter main circuit 2A side composed of the current detector 11A and the current feedback value on the inverter main circuit 2B side detected by the current detector 11B, that is, the circulating current. An adder for calculating a feedback value, 52 is a circulating current controller for amplifying the circulating current feedback value to control the circulating current and create a circulating current control output,
Reference numeral 53 is a limiter circuit having a saturation characteristic at a certain value or more in order to keep the circulating current control output within a certain range.

Next, the failure detecting means for detecting an abnormality in the circulating current control system will be described. In the figure, 54 is an adder 5
When the deviation output from 1 is equal to or more than the set value from the level setter 55, a comparator as a comparing means for setting the output to the "H" level, and 56 is an operation of the limiter circuit 53 for limiting the output from the circulating current controller 52. When a point is in the saturation region, a saturation detector as a saturation detecting means for bringing the output to the "H" level, and 57 is an AND detecting means for operating by receiving the outputs from the comparator 54 and the saturation detector 56. Circuit.

Next, the failure detection operation will be described. It is the same as the prior art that the comparator 54 outputs a signal which can be presumed to be a failure occurrence when the circulating current feedback value from the adder 51 exceeds the set value from the level setter 55 even for an instant.
However, in this embodiment, the output of the comparator 54 alone does not finally determine that a failure has occurred, but the output of the saturation detector 56 at the same time determines that a failure has occurred. That is, when the output level of the circulating current controller 52 is equal to or higher than the saturation region setting level of the limiter circuit 53, it is determined that a failure has occurred on the AND condition.

In this way, the failure detection is performed only when the output of the circulating current controller 52 is at the saturation level. The reason why the controller 52 works normally when the output of the circulating current controller 52 is not at the saturation level. This is because there is a possibility of returning to the state, so it was decided not to judge it as a failure. Further, even with such a determination method, as long as there is no abnormality in the control system of each of the inverter main circuits 2A and 2B, there is no particular problem as a circulating current control system, and with this method, the original control operation is performed. It will not be unnecessarily disturbed. Although the U phase shown in the figure has been described above, the same applies to the V phase and the W phase.

Example 10. FIG. 11 is a first embodiment of the present invention.
10 is an overall configuration diagram showing an inverter failure detection system according to 0. The only difference from FIG. 10 of the ninth embodiment is that a timer setting device 58 is inserted between a comparator 54 and an AND circuit 57. That is, when the detected output of the comparator 54 continues for the set time of the timer setter 58 or more, the output is sent to the AND circuit 57. As a result, as described in the second embodiment and the like, it is possible to avoid the fault erroneous detection operation due to the harmonic component of the detection signal.

Example 11. FIG. 12 is a first embodiment of the present invention.
1 is an overall configuration diagram showing an inverter failure detection method according to the first embodiment. Here, the adders 59U, 59V and 59W calculate the deviation between the current command value and the current feedback value for each phase, and the adder 60 further calculates the deviations of the adders 59U, 59V and 5W.
The relaxation of the deviation output from 9 W is calculated and the zero-phase current is output. When the zero-phase current output from the adder 60 exceeds the set value from the level setter 61 even for an instant, the comparator 62 as a failure detecting means detects this and fails as a current control system abnormality or an inverter ground fault. Detect.

It is possible to limit the failure occurrence target by combining with the various failure detection means already described. For example, in combination with failure detection means of current control system,
When the comparator 62 according to the eleventh embodiment detects a failure when the current control system abnormality is not detected, the failure occurrence target can be limited to the inverter ground fault.

Example 12 FIG. 13 is a first embodiment of the present invention.
12 is an overall configuration diagram showing an inverter failure detection method according to No. 2 and is different from FIG. 12 of the eleventh embodiment only in that a timer setter 63 is inserted on the output side of the comparator 62. That is, when the detection output of the comparator 62 continues for the set time of the timer setter 63 or more, failure detection is performed as a current control system abnormality or an inverter ground fault. As a result, as described in the second embodiment and the like, it is possible to avoid the fault erroneous detection operation due to the harmonic component of the detection signal.

Example 13 FIG. 14 is a first embodiment of the present invention.
3 is an overall configuration diagram showing an inverter failure detection method according to No. 3 and is different from the previous embodiment 11 (FIG. 12) in that a comparator 6
The only difference is that the AND circuit 64 is inserted on the output side of the second circuit. Then, an inverted signal of the output of the inverter ground fault abnormality from a ground fault detector (not shown) is input to the AND circuit 64. As a result, the AND circuit 64 outputs a failure detection signal when the inverter ground fault abnormality is not detected and when the comparator 62 outputs. Therefore, the failure detection is to detect the current control system abnormality, and the range of the failure occurrence target can be limited as compared with the case of the eleventh embodiment. Of course, by properly combining with the failure detecting means according to the other embodiments described above, it is possible to further limit the range of the failure occurrence target and detect the failure as an abnormality in the current detector, for example.

Example 14 Incidentally, Examples 11 to 13
Then, the deviation between the current command value and the current feedback value of each phase was taken, and the zero-phase current was obtained by taking the sum of the deviation output of each phase, but using only the current feedback value of each phase, Even if the zero-phase current is obtained by taking the sum, the same effect can be obtained.

Example 15. 15 is an overall configuration diagram showing an inverter failure detection system according to a fifteenth embodiment of the present invention. Here, the adder 65 calculates the relaxation of each phase voltage feedback value and outputs a zero phase voltage. When the zero-phase voltage output from the adder 65 becomes equal to or higher than the set value from the level setter 66 even for an instant, the comparator 6 as failure detecting means.
7 detects this and performs failure detection as a voltage control system abnormality or an inverter ground fault.

The target of failure can be limited by combining with the various failure detection means already described. For example, when the comparator 67 according to the fifteenth embodiment detects a failure in combination with the failure detection means of the voltage control system and the abnormality of the voltage control system is not detected, the failure occurrence target is limited to the inverter ground fault. can do.

Example 16. 16 shows a first embodiment of the present invention.
15 is an overall configuration diagram showing an inverter failure detection system according to No. 6 and is different from FIG. 15 of the fifteenth embodiment only in that a timer setter 68 is inserted on the output side of the comparator 67. That is, when the detection output of the comparator 67 continues for the set time of the timer setter 68 or more, a failure is detected as a voltage control system abnormality or an inverter ground fault. As a result, as described in the second embodiment and the like, it is possible to avoid the fault erroneous detection operation due to the harmonic component of the detection signal.

Example 17 In the fifteenth and sixteenth embodiments, the zero-phase voltage is obtained by summing the voltage feedback values of the respective phases, but the deviation between the voltage command value and the voltage feedback value of each phase is calculated and the deviation output of each phase is obtained. Even if the zero phase voltage is obtained by taking the sum of the above, the same effect can be obtained.

Example 18 FIG. 17 is a first embodiment of the present invention.
9 is an overall configuration diagram showing an inverter failure detection method according to FIG. Here, a so-called three-level inverter capable of outputting three types of voltage levels is dealt with, and in particular, a DC voltage balance abnormality on the input side thereof is detected. In the figure, 5A and 5B are capacitors connected in series between both pole terminals P and N of the DC power supply, and the input side of the three-level inverter main circuit 6 is both pole terminals P and N of the DC power supply and both capacitors 5A. , 5B is connected to the intermediate connection terminal C, and the induction motor 3 is driven by outputting a three-phase AC voltage having a variable voltage and a variable frequency and a current.

13A and 13B are DC voltage detectors for detecting the voltages of the capacitors 5A and 5B, respectively.
Is an adder for calculating a deviation between the voltage feedback value from the DC voltage detector 13A and the voltage feedback value from the DC voltage detector 13B, and 70 is the level output from the deviation output from the adder 69.
It is a comparator as a failure detection means that outputs a DC voltage balance abnormality when the value is equal to or more than the set value from 1.

Next, the operation will be described. The inverter control circuit 20 supplies a necessary gate signal to the transistor 6T of each arm of the inverter main circuit 6 based on the input speed command value. As a result, the inverter main circuit 6 supplies a predetermined voltage and current output to the induction motor 3. Here, the details of this control operation are well known, and the description thereof will be omitted. However, as a part of the control operation, the capacitors 5A and 5B will be described.
The ignition widths of the transistors 6T of the respective phases are controlled so that the voltages of and are balanced within a certain range. That is, DC voltage balance control is performed.

If the balance is lost and the deviation output from the adder 69 exceeds the set value from the level setter 71 even for an instant, the comparator 70 detects it and outputs it as an abnormal DC voltage balance.

Example 19 FIG. 18 shows a first embodiment of the present invention.
FIG. 17 is an overall configuration diagram showing an inverter failure detection method according to No. 9, which is different from FIG. 17 of the eighteenth embodiment only in that a timer setter 72 is inserted on the output side of the comparator 70. That is, when the detection output of the comparator 70 continues for the set time of the timer setter 72 or more, the failure is detected as the DC voltage balance abnormality. As a result, as described in the second embodiment and the like, it is possible to avoid the fault erroneous detection operation due to the harmonic component of the detection signal.

Example 20. In each of the above-described embodiments, a comparator whose output becomes "H" level when various deviation outputs become equal to or more than a set value is used as the comparison means, but the invention is not limited to the one that operates in such an output form. It does not mean that Further, in each of the above embodiments, the AND circuit is used to determine whether or not a plurality of conditions are satisfied, but it is possible to determine whether or not the conditions required for failure detection are substantially simultaneously satisfied in consideration of the output form of the preceding stage. If so, another type of logic circuit or the like may be used.

Further, the switching element forming the inverter main circuit is not limited to the power transistor, but may be another type of element such as a thyristor, and the load is not limited to the induction motor. Also, the control method is not limited to vector control and PWM control.

[0088]

As described above, in the inverter failure detection method according to the first aspect of the present invention, the current control system abnormality is such that the deviation between the current command value and the current feedback value is the set value or more and the limiter circuit. Since the detection is performed under the condition that the operating point is in the saturation region, an erroneous detection operation due to a sudden change in the control command value can be prevented.

Further, in the inverter failure detection method according to the second aspect, since the failure detection is performed by adding the condition that the deviation output of the set value or more continues for the set time or more, the harmonic of the detection signal is detected. It is possible to avoid a malfunction erroneous detection operation due to a wave component or the like.

In the inverter failure detection method according to the third aspect of the present invention, the voltage control system abnormality is such that the deviation between the voltage command value and the voltage feedback value is the set value or more and the operating point of the limiter circuit is not in the saturation region. Since the detection is performed under this condition, an erroneous detection operation that may occur due to the voltage command value becoming non-linear due to the presence of the limiter circuit is prevented.

Further, in the inverter failure detection method according to the fourth aspect, since the failure detection is performed by adding the condition that the deviation output of the set value or more continues for the set time or more, the harmonics of the detection signal are detected. It is possible to avoid a malfunction erroneous detection operation due to a wave component or the like.

Further, in the inverter failure detection method according to the fifth aspect, the failure is detected when the current control system abnormality is detected while the voltage control system abnormality is not detected. The target can be limited to the feedback current detector.

Further, in the inverter failure detection method according to the sixth aspect of the invention, the failure is detected on the condition that the deviation between the motor input obtained from the voltage and current and the motor output obtained from the speed feedback value is equal to or more than the set value. Since it is configured to detect,
An abnormality of the speed detector can be detected.

Further, in the inverter failure detection method according to the seventh aspect, since the failure detection is performed by adding the condition that the deviation output of the set value or more continues for the set time or more, the harmonic of the detection signal is detected. It is possible to avoid a malfunction erroneous detection operation due to a wave component or the like.

Further, in the inverter failure detection method according to the present invention, the speed detector abnormality is detected by adding a condition that neither the current control system abnormality nor the voltage control system abnormality is detected. Therefore, the failure occurrence target at the time of failure detection is surely limited to only the speed detector.

In the inverter failure detection method according to the ninth aspect, the circulating current control system abnormality is detected on condition that the circulating current feedback value is equal to or greater than the set value and the operating point of the limiter circuit is in the saturation region. With this configuration, only when there is no possibility of returning to the normal state is detected as an abnormality, the original control operation is not unnecessarily disturbed.

Further, in the inverter failure detection method according to the tenth aspect, since the failure detection is performed by adding the condition that the deviation output of the set value or more continues for the set time or more, the harmonic of the detection signal is detected. It is possible to avoid a malfunction erroneous detection operation due to a wave component or the like.

According to the eleventh aspect of the inverter failure detecting method of the present invention, the deviation between the current command value and the current feedback value of each phase or the current feedback value of each phase is added to obtain a zero phase current. Since the configuration is such that the failure is detected on condition that the phase current is equal to or more than the set value, it is possible to detect the current control system abnormality or the inverter ground fault.

Further, in the inverter failure detection system according to the twelfth aspect, since the failure detection is performed by adding the condition that the zero-phase current of the set value or more continues for the set time or more, the detection signal of the detection signal is added. It is possible to avoid an erroneous failure detection operation due to a harmonic component or the like.

Further, in the inverter failure detection method according to the thirteenth aspect, since the zero-phase current abnormality is detected by adding the condition that the ground fault is not detected by the ground fault detector, the fault is detected. The fault occurrence target at the time of detection is surely limited to the current control system.

Further, in the inverter failure detection method according to the fourteenth aspect, the deviation between the voltage command value and the voltage feedback value of each phase or the voltage feedback value of each phase is added to obtain a zero phase voltage, and the zero phase voltage is obtained. Since the failure detection is performed on condition that the phase voltage is equal to or higher than the set value, the voltage control system abnormality or the inverter ground fault can be detected.

Further, in the inverter failure detection method according to the fifteenth aspect, since the failure detection is performed by adding the condition that the zero-phase voltage of the set value or more continues for the set time or more, the detection signal of the detection signal is detected. It is possible to avoid an erroneous failure detection operation due to a harmonic component or the like.

Further, in the inverter failure detecting method according to the sixteenth aspect, since the failure is detected on condition that the deviation of the detected voltage value of each capacitor is equal to or more than the set value, the DC voltage in the three-level inverter is A balance abnormality can be detected.

Further, in the inverter failure detection method according to the seventeenth aspect, since the failure detection is performed by adding the condition that the deviation output of the set value or more continues for the set time or more, the harmonic of the detection signal is detected. It is possible to avoid a malfunction erroneous detection operation due to a wave component or the like.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an inverter failure detection system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of an inverter control circuit 20 of FIG.

FIG. 3 is an overall configuration diagram showing an inverter failure detection method according to a second embodiment of the present invention.

FIG. 4 is an overall configuration diagram showing an inverter failure detection system according to a third embodiment of the present invention.

FIG. 5 is an overall configuration diagram showing an inverter failure detection system according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing an essential part of an inverter failure detection system according to a fifth embodiment of the present invention.

FIG. 7 is an overall configuration diagram showing an inverter failure detection system according to a sixth embodiment of the present invention.

FIG. 8 is an overall configuration diagram showing an inverter failure detection system according to a seventh embodiment of the present invention.

FIG. 9 is an overall configuration diagram showing an inverter failure detection system according to an eighth embodiment of the present invention.

FIG. 10 is an overall configuration diagram showing an inverter failure detection system according to a ninth embodiment of the present invention.

FIG. 11 is an overall configuration diagram showing an inverter failure detection system according to a tenth embodiment of the present invention.

FIG. 12 is an overall configuration diagram showing an inverter failure detection system according to an eleventh embodiment of the present invention.

FIG. 13 is an overall configuration diagram showing an inverter failure detection system according to a twelfth embodiment of the present invention.

FIG. 14 is an overall configuration diagram showing an inverter failure detection system according to a thirteenth embodiment of the present invention.

FIG. 15 is an overall configuration diagram showing an inverter failure detection system according to a fifteenth embodiment of the present invention.

FIG. 16 is an overall configuration diagram showing an inverter failure detection system according to a sixteenth embodiment of the present invention.

FIG. 17 is an overall configuration diagram showing an inverter failure detection method according to embodiment 18 of the present invention.

FIG. 18 is an overall configuration diagram showing an inverter failure detection system according to a nineteenth embodiment of the present invention.

[Explanation of symbols]

2 Inverter main circuit 3 Induction motor 5 Capacitor 6 3-level inverter main circuit 10 Speed detector 11 Current detector 12 Voltage detector 13 DC voltage detector 20 Inverter control circuit 25, 35, 46, 51, 59, 60, 65, 69 Adder 26 Current controller 27,53 Limiter circuit 30,36,47,54,62,67,70 Comparator 31,37,48,55,61,66,71 Level setting device 32,38,56 Saturation detector 33, 40, 43, 50, 57, 64 AND circuit 34, 41, 49, 58, 63, 68, 72 Timer setter 39, 42 Not circuit 44, 45 Output calculator 52 Circulating current controller

Claims (17)

[Claims] 1. An adder for calculating a deviation between a current command value and a current feedback value, a current controller for amplifying a deviation output from the adder and outputting it as a voltage command value, and an adder inserted on the output side of the current controller. In a fault detection method for an inverter that constitutes a current control system by providing a limiter circuit having a saturation characteristic at a certain value or more and controlling the output voltage based on the voltage command value from this limiter circuit, the deviation output is set to a predetermined value. Comparison means for judging whether or not it is equal to or more than a set value, saturation detection means for judging whether the operating point of the limiter circuit is in the saturation region, and the deviation by inputting the outputs from the comparison means and the saturation detection means. A failure detection means for detecting an abnormality of the current control system when the output is equal to or higher than the predetermined set value and the operating point of the limiter circuit is in the saturation region Inverter failure detecting method, characterized in that. 2. A timer setting device, which is inserted between the comparing means and the failure detecting means, and which outputs when the output from the comparing means continues for a predetermined set time or more. Inverter failure detection method. 3. A voltage control system is configured by including a limiter circuit that inputs a voltage command value and outputs it with a saturation characteristic at a certain value or more, and by controlling the output voltage based on the voltage command value from this limiter circuit. In an inverter failure detection method, an adder that calculates the deviation between the voltage command value and the voltage feedback value from the limiter circuit, a comparison means that determines whether the deviation output from this adder is greater than or equal to a predetermined set value, Saturation detecting means for determining whether or not the operating point of the limiter circuit is in a saturation region, and outputs from the comparing means and the saturation detecting means are inputted, and the deviation output is equal to or more than the predetermined set value, and the limiter. A failure detection system for an inverter, comprising failure detection means for detecting an abnormality in the voltage control system when the operating point of the circuit is not in the saturation range. 4. A timer setting device, which is inserted between the comparing means and the failure detecting means, and which outputs when the output from the comparing means continues for a predetermined set time or more. Inverter failure detection method. 5. An output from the failure detecting means according to claim 1 or 2 and an output from the failure detecting means according to claim 3 or 4 is input to detect an abnormality in a current control system and not an abnormality in a voltage control system. A failure detection method for an inverter, characterized by comprising failure detection means for detecting an abnormality of the feedback current detector. 6. A failure detection method for an inverter that supplies an output voltage and an output current to an electric motor to drive the electric motor. First output arithmetic means for calculating an input of the electric motor from the output voltage and the output current, torque and speed. Second output calculation means for calculating the output of the motor and the output deviation of the first and second output calculation means from the speed feedback value of the electric motor detected by the detector, and the deviation is predetermined. A failure detection method for an inverter, comprising failure detection means for detecting an abnormality in the speed detector when the value is equal to or more than the set value. 7. In an inverter failure detection method for supplying an output voltage and an output current to an electric motor for driving, a first output arithmetic means for arithmetically operating an input of the electric motor from the output voltage and the output current, torque and speed. Second output calculating means for calculating the output of the electric motor from the speed feedback value of the electric motor detected by the detector, and deviation of the outputs of the first and second output calculating means, and a predetermined set value A failure detection system for an inverter, comprising: failure detection means for detecting an abnormality of the speed detector when the above deviation continues for a predetermined set time or longer. 8. The failure detecting means according to claim 1 or 2 and the failure detecting means according to claim 3 or 4 do not detect a failure, and the failure detecting means according to claim 6 or 7 fails. A failure detection system for an inverter, characterized by comprising failure detection means for detecting as an abnormality of the speed detector when detected. 9. A circulating current controller that amplifies a circulating current feedback value flowing in the parallel circuit of a multiplex system inverter in which output sides of a plurality of inverters are connected in parallel to each other and outputs the amplified value as a voltage command value, and the circulating current controller. Of the inverter constituting the circulating current control system by controlling the output voltage of each inverter based on the voltage command value from this limiter circuit In the failure detection method, a comparison unit that determines whether the circulating current feedback value is a predetermined set value or more, a saturation detection unit that determines whether the operating point of the limiter circuit is in a saturation region, and the comparison unit. And the output from the saturation detection means are input, the circulating current feedback value is equal to or more than the predetermined set value, and the operating point of the limiter circuit is Inverter failure detecting method characterized by comprising a failure detection means for detecting an abnormality of the circulating current control system when in a serial saturation region. 10. A timer setting device, which is inserted between the comparison means and the failure detection means, and which outputs when the output from the comparison means continues for a predetermined set time or more. Inverter failure detection method. 11. A zero-phase current is detected by adding a deviation between a current command value and a current feedback value of each phase or a current feedback value of each phase in a failure detection method of an inverter that outputs a three-phase AC voltage and current. An inverter failure detection system characterized by comprising failure detection means for detecting an abnormality in the current control system or an inverter ground fault when the zero-phase current is equal to or greater than a predetermined set value. 12. A zero-phase current is detected by adding a deviation between a current command value of each phase and a current feedback value or a current feedback value of each phase in a failure detection method for an inverter that outputs a three-phase AC voltage and current. A failure detection method for an inverter, comprising: failure detection means for detecting an abnormal current control system or an inverter ground fault when a zero-phase current of a predetermined set value or more continues for a predetermined set time or longer. 13. A ground fault detector for separately detecting a ground fault of the inverter output circuit is provided, the failure detecting means according to claim 11 or 12 detects an abnormality, and the ground fault detector detects a ground fault. A failure detection method for an inverter, characterized by comprising failure detection means for detecting an abnormality in the current control system when the failure occurs. 14. A zero-phase voltage is detected by adding a deviation between a voltage command value of each phase and a voltage feedback value or a voltage feedback value of each phase in a failure detection method for an inverter that outputs a three-phase AC voltage and current. An inverter failure detection system characterized by comprising failure detection means for detecting an abnormal voltage control system or an inverter ground fault when the zero-phase voltage is equal to or higher than a predetermined set value. 15. A zero-phase voltage is detected by adding a deviation between a voltage command value and a voltage feedback value of each phase or a voltage feedback value of each phase in a failure detection method of an inverter that outputs a three-phase AC voltage and current. A failure detection method for an inverter, comprising: failure detection means for detecting an abnormal voltage control system or an inverter ground fault when a zero-phase voltage of a predetermined value or more continues for a predetermined time or more. 16. A fault detection method for a three-level inverter, which is connected to both pole terminals of a DC power source and an intermediate connection point of capacitors connected in series between the both pole terminals and is capable of outputting three kinds of voltage levels, A voltage detector that detects the voltage between the capacitors, an adder that calculates the deviation of the output of these voltage detectors, and a DC voltage balance abnormality when the deviation output from this adder is greater than or equal to a predetermined set value. A failure detection method for an inverter, characterized by comprising failure detection means. 17. A failure detection method for a three-level inverter capable of outputting three types of voltage levels, which is connected to both pole terminals of a DC power source and an intermediate connection point of capacitors connected in series between the both pole terminals, A voltage detector that detects the voltage between the capacitors, an adder that calculates the deviation of the output of these voltage detectors, and a deviation output from this adder that is equal to or greater than a predetermined set value continues for a predetermined set time or longer. A failure detection method for an inverter, comprising failure detection means for detecting a DC voltage balance abnormality when output.