JPH07226778A - Data reception system - Google Patents

Abstract

PURPOSE:To improve the normal reception rate of data by selecting a sampling timing in the vicinity of a zero cross point of a commercial power supply voltage where a transmission signal level is high so as to allow a sampled signal to hardly receive a noise. CONSTITUTION:A start bit ST of a bit serial signal shown in figure (d) is detected and timing of a generated sampling pulse shown in (1),(2) in figure (i) is determined based on a time interval tsm between a power supply zero cross signal and a falling of the start bit ST. When the frequency of the commercial power supply voltage is, e.g. 60Hz, a wait time till generation of a sampling pulse is selected to be 16ms shown in (2) of the figure (i) in the case of tsm>4 ms, selected to be 7ms shown in (1) of the figure (i) in the case of tsm<=4ms, and then sampling is implemented in the same timing for the plural number of times for one sampling as to one bit in the vicinity of the zero cross point of the commercial power supply voltage where the signal level is high to read and store a data signal. Upon the receipt of a specified length of a text after checking of one word, the reception processing is finished and a correct reception signal is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applicable to data transmission in which bit serial data is superimposed on a commercial frequency electric quantity such as a commercial power supply voltage using a distribution line and transmitted, and noise is mixed in the bit serial signal. The present invention relates to a data receiving method capable of maintaining a high normal data reception rate.

[0002]

2. Description of the Related Art As a method for reading data relatively accurately even when noise is mixed in a bit serial signal and bit cracking occurs, a plurality of sampling points are provided in one bit and one bit is read many times. Well-known is a method of determining bits by majority decision.

FIG. 5 is a diagram showing a conventional majority decision bit decision circuit disclosed in, for example, Japanese Patent Laid-Open No. 4-329721. In the figure, reference numeral 1 is an input terminal to which a delivery signal superimposed on a power supply is input. 2 is a capacitor connected to the input terminal 1, 3 is a coil connected to the capacitor 2,
Reference numeral 4 is a bandpass filter connected to the coil 3, 5 is a portable demodulation circuit connected to the bandpass filter 4, 6 is a sampling pulse generation circuit connected to the portable demodulation circuit 5, and 7 is a portable demodulation circuit 5. And a first shift register connected to the sampling pulse generating circuit 6, 8 is a frequency dividing circuit connected to the sampling pulse generating circuit 6, and 9 is a first
, A second shift register connected to the frequency dividing circuit 8 and the majority decision circuit 9, and 11 is an output terminal for outputting the signal of the shift register 10 in parallel.

FIG. 7 is a diagram showing a general signal waveform in a communication system using a distribution line. (A) is a superimposed signal of a commercial power supply voltage and a high frequency transmission signal, and (b) is a signal bit of the high frequency transmission signal. As an example, (c) is a high frequency FS signal (delivery signal) separated by a bandpass filter, and (d) is a high frequency FS signal.
Bit-serial logic waveform obtained by demodulating the signal,
(E) is a commercial power supply clock obtained from the commercial power supply voltage.

Next, the operation of the circuit device shown in FIG.
Will be described with reference to the timing chart of FIG. In FIG. 6, (a) is a superimposed signal of a commercial power supply voltage and a high frequency signal transmitted from the transmitter, (d) is demodulated bit-serial received data, (f) is a sampling pulse, and (g) is It is a received signal. The reception data (d) demodulated by the portable demodulation circuit 5 and input to the first shift register 7 contains negative noises 12a and 12b and positive noises 13a, 13b and 13c. In the waveform of the commercial power supply voltage, these noises are more likely to be mixed in the vicinity of the peaks 15a and 15b having a low signal level than in the vicinity of the zero crosses 14a and 14b where the communication signal level is high.

In the circuit shown in FIG. 5, the transport demodulation circuit 5 sends a start signal to the sampling pulse generation circuit 6 at the trailing edge of the leading edge of the start bit ST shown in FIG. 6 (d), and this start signal generates a sampling pulse. Circuit 6
When it is input to, a sampling pulse (f) is generated.
FIG. 6 shows an example in which nine sampling pulses are generated at equal intervals during one bit.

In the circuit of FIG. 5, since the output terminals Q1 to Q9 of the first shift register 7 are connected to the majority decision circuit 9, as shown in FIG. 6D, the negative noise 12a in one bit, 12b and positive noise 13a, 13b, 1
Even if 3c is mixed, if the number of noise detections at the time of sampling in one bit is smaller than the number of normal signal detections, the majority decision circuit 9 makes a majority decision and the noises are ignored, and the correct received signal (g) is output. can get.

[0008]

By the way, in the conventional receiving method based on bit determination, since sampling pulses are continuously generated at equal intervals during one bit, sampling is performed regardless of whether the transmission signal level is high or low. Therefore, when a large amount of noise is mixed, there is a possibility that signal reading may be erroneously performed.

The present invention has been made in order to solve the above-mentioned problems, and provides a data reception system which provides a reception system in which the normal reception rate of data is extremely high even when noise is mixed in a transmission signal. The purpose is to get a scheme.

[0010]

In the data receiving system according to the present invention, each bit of bit serial data transmitted by being superimposed on the commercial frequency electricity quantity of the commercial distribution line is received by sampling. In this case, the sampling is performed near the zero cross of the commercial frequency electric quantity having a large transmission signal level.

Further, the start bit in the bit serial data is detected, the time interval between the zero-cross signal of the commercial frequency electric quantity and the start bit is measured based on this, and the sampling timing is used to determine the sampling timing from the commercial frequency electric quantity. It is set near the zero cross of and sampling is performed at the set timing.

The number of bits per second (Bit) of the transmission signal
When Per Second (hereinafter referred to as BPS) is the same as the commercial frequency, one bit of the transmission signal has two zero-crosses of the commercial frequency electricity amount, and therefore the sampling timing is set at these two locations.

Further, the sampling is performed a plurality of times near the zero cross of the commercial frequency electricity quantity.

[0014]

In general, when the transmission signal is superimposed on the commercial frequency electricity quantity, the transmission signal level becomes small near the peak of the power supply voltage and becomes large near the zero cross, so that noise is easily mixed near the peak. Based on the fact that noise is less likely to be mixed in the vicinity of the zero cross, the zero cross signal of the commercial frequency electricity quantity was used and the sampling timing was set near the zero cross of the commercial power supply voltage with a large transmission signal level. Noise is unlikely to be mixed in the sampling, which has the effect of improving the normal reception rate of data.

When the BPS of the transmission signal is the same as the commercial frequency, that is, when the BPS of the transmission signal is 60 when the commercial frequency is 60 Hz, sampling is performed at a plurality of timings near two zero crosses of the commercial frequency electricity quantity. As a result, the probability of noise inclusion is further reduced, and the normal data reception rate can be further improved.

[0016]

EXAMPLES Example 1. FIG. 1 shows a circuit device for carrying out the data receiving system of the present invention. Reference numeral 1 denotes an input terminal to which a delivery signal superimposed on a power supply voltage is input. The input terminal 1 is connected to the bandpass filter 4 via the capacitor 2 and the coil 3, and the output terminal of the bandpass filter 4 is connected to the CPU 16 via the portable demodulation circuit 5. Further, the input terminal 1 sends a power zero cross signal to the CPU 16 via the power zero cross signal circuit 17.

The input terminal 1 receives the signal of FIG. 2 (a) in which the distribution signal is superimposed on the commercial power source. This signal passes through the band pass filter 4 to become only a high frequency carrier signal, which is further converted by the carrier demodulation circuit 5 into the bit-serial reception data of FIG.
A power supply zero-cross signal shown in FIG. 2 (h) is also input to the CPU 16 from the power supply zero-cross signal circuit 17, and the CPU 16 performs a receiving process by generating a sampling pulse shown in FIG. 2 (i) by a program.

The CPU 16 detects a sync signal in the transmission signal demodulated by the portable demodulation circuit 5, and when the sync signal (10 bits in this example, 167 ms) is detected, the receiving operation starts. First, the start bit ST of the bit serial signal shown in FIG. 2 (d) is detected, and the start bit ST of FIG. 2 (h) and the start time ST falling time interval tsm are shown in FIG. 2 (i). Determines the timing of sampling pulse generation. In this example in which the commercial power supply voltage is 60 Hz, when tsm> 4 ms, waiting time until the sampling pulse is generated is 16 ms as shown in FIG. 2 (i), and when t _sm ≦ 4 ms, waiting time is shown in FIG. 2 (i).
7 ms as shown in FIG. 2 and sampling is performed a plurality of times at the same timing as shown in FIG.
ms)) is performed at one place for each bit in the vicinity of the zero cross of the commercial power supply voltage having a large signal level, and the data signal is read and stored. Further, a test (majority decision) is performed for each word, and when a prescribed message length is received after the one-word test, the reception process ends and a correct reception signal is obtained.

The operation of the CPU 16 will be described below with reference to the flowchart of FIG. First, the synchronization signal in the bit serial transmission signal is detected (step S
t1). When the sync signal is detected, the reception operation starts, the start bit ST is detected (step St2), and the timing of sampling pulse generation is determined by the magnitude of the time interval tsm between the power supply zero-cross signal and the start bit falling (step St3). ). In this example, tsm> 4
When ms (step St4), the waiting time until the sampling pulse is generated is 16 ms, and when tsm ≦ 4 ms (step St5), the waiting time is 7 ms, and sampling is performed a plurality of times as shown in FIG. Is performed three times) in the vicinity of the zero cross of the commercial power supply signal having a large signal level, and sampling processing for reading and storing the signal is performed (step St6). Further, the verification (majority decision) is performed for each word (step St7), and then steps St2 to 7 are repeated again after the start bit is detected. After the one-word test, when the specified message length is received, the reception process ends (step St8).

In this example, the number of samplings in the majority decision is 3 and the time interval is 1 ms. However, by increasing the number of samplings near the zero cross of the commercial power supply voltage and decreasing the time interval, the normal data reception rate is further improved. improves. Although the present embodiment shows the case where the bit serial data to be transmitted is 60 BPS and is the same as that of a commercial power source of 60 Hz, it can be similarly implemented at another commercial frequency of 50 Hz.

Example 2. In the first embodiment, sampling of bit serial data is performed near the zero cross of the commercial power supply voltage 1
Although the example was performed at the location, BPS of bit serial signal
If the frequency is the same as the frequency of the commercial power supply voltage, one bit contains two zero-cross points of the commercial power supply voltage.
As shown in (i), sampling is performed a plurality of times at these two locations where the transmission signal level is high (in the case of FIG. 4, sampling is performed three times at two locations), thereby further improving the normal data reception rate. be able to. In the case of FIG. 4, for 1 bit, 7 ms from the power supply zero cross signal
And 16 ms are sampled at the same timing.

[0022]

As described above, the data receiving system according to the present invention uses the zero-cross signal of the commercial frequency electric quantity and sets the sampling timing to near the zero-cross of the commercial power supply voltage having a large transmission signal level. Noise is less likely to be mixed in, and there is an effect that the normal reception rate of data can be significantly improved.

When the BPS of the transmission signal is the same as the frequency of the superimposed commercial power supply voltage, the normal data reception rate is further improved by sampling at a plurality of timings near the zero crossings of the commercial power supply voltage for each bit. Can be achieved. Moreover, since the sampling is performed a plurality of times, the normal data reception rate is further improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit that implements a data receiving system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing signals for explaining the operation of the first embodiment.

FIG. 3 is a flowchart illustrating the operation of the first embodiment.

FIG. 4 is a diagram showing signals for explaining the operation of the data receiving system according to the second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional data receiving device.

FIG. 6 is a diagram showing signals for explaining the operation of the conventional data receiving apparatus.

FIG. 7 is a diagram showing a general signal waveform in a communication system using a distribution line.

[Explanation of symbols]

 1 Input Terminal 4 Band Pass Filter 5 Portable Demodulator 16 CPU 17 Power Zero Cross Signal Circuit

Claims (4)

[Claims] 1. In a data receiving system in which each bit of bit serial data transmitted by being superimposed on the commercial frequency electricity quantity of a distribution line is received by sampling, the sampling is performed by the commercial frequency electricity quantity. The data reception method is characterized in that it is performed near the zero cross. 2. A data receiving system in which each bit of bit serial data transmitted by being superimposed on a commercial frequency electricity quantity of a distribution line is received by sampling, and a start bit in the bit serial data is received. Detecting, measuring the time interval between the zero-cross signal of the commercial frequency electricity and the start bit based on this, set the sampling timing from the time interval near the zero cross of the commercial frequency electricity,
A data receiving method characterized in that sampling is performed at the set timing. 3. In a data receiving system in which each bit of bit serial data transmitted by being superimposed on the commercial frequency electricity amount of a distribution line is transmitted by reading by sampling, a bit per second of transmitted bit serial data is received. The number is set equal to the frequency of the commercial frequency electricity quantity to be superimposed, the start bit in the bit serial data is detected, and based on this, the time interval between the zero cross signal of the commercial frequency electricity quantity and the start bit. From this time interval, the sampling timing is set for each bit of the bit serial data in the vicinity of two zero-crosses of the commercial frequency electricity quantity,
A data receiving method characterized in that sampling is performed at the set timing. 4. The data receiving system according to claim 1, wherein sampling is performed a plurality of times near the zero cross of the commercial frequency electricity quantity.