JPH07226661A - Hazard removal circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A hazard elimination circuit that eliminates unnecessary hazards generated in the necessary data on the input side of a 2-input 1-output switch, etc. on the output side of the switch, and various forms on the input side. It is an object of the present invention to realize a hazard removal circuit that can reliably remove the hazard on the output side from the data including the hazard generated in 1. [Structure] Data containing hazards that do not require input (AL
M) is input as D input and the clock of simultaneous input (CL
The flip-flop FF (3) for obtaining the output data (ALM 1) as the Q output by K), the output data (ALM 1) and the output data (ALM 1) are input and the input clock (CLK) is input.
And a hazard removing unit (6) that takes a logical product (AND) with the output of the n-stage flip-flop FF (17) that delays and outputs one clock by n clocks.
Configure the output of (ALM 4) as its output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an input system such as an active system,
When switching the data and clock of the two systems of the standby system with a switch, alarm AL will be issued if the input working clock is cut
It relates to the operation of a switch, etc., which selects 2-input and 1-output, such as selecting and sending MM and sending and selecting alarm ALM P when the standby clock is cut off, especially the data and clock on the input side. This is caused by interference with the device or pulling out of the device panel, and the output side data (ALM M or
The so-called hazard, which is an unnecessary error pulse (commonly called beard) that occurs in an unspecified part of ALM P, which is represented by ALM, is removed from the output side data (ALM) to obtain output data without a hazard. The present invention relates to a hazard elimination circuit.

As a hazard elimination circuit, it is desired that unnecessary hazards generated in various forms in necessary data on the input side of the switch can be surely and easily eliminated from the data on the output side. There is.

[0003]

2. Description of the Related Art As shown in FIG. 7, a conventional hazard elimination circuit inputs an alarm ALM, which is data including a hazard generated on the input side of the switch having two inputs and one output, and inputs the input ALM in series. A low-pass filter (31) having a time constant CR consisting of a resistor R and a capacitor C whose negative side is grounded
The high-frequency component generated at the rise and fall of the hazard is removed by the capacitor C to the ground to remove the hazard and use it as the output data. However, this conventional hazard elimination method uses the hazard generated at the input side. When the time width of is short, the low-pass filter (3
It can be removed efficiently by using 1), but when the hazard time width is long, a low-pass filter with a long time constant (31)
However, since the output waveform of that hazard is blunted, the actual situation is that the hazard cannot be sufficiently removed on the output side.

[0004]

As described above, the conventional method of removing a hazard by the pass capacitor C of the low pass filter (31) which is a hazard removing circuit is effective in eliminating hazards generated in various forms on the input side. There was a problem in removing it. An object of the present invention is to provide an input side, such as a switch with two inputs and one output, when a hazard occurs randomly, when a hazard occurs regularly, or when a hazard occurs in a burst for a certain time. An object of the present invention is to provide a hazard elimination circuit capable of eliminating unnecessary hazards from data (ALM) including such hazards on the output side with a reliable and simple configuration.

[0005]

To solve this problem, in the hazard elimination circuit of the present invention, for output side data (ALM) in the case where a hazard is randomly generated at the input side such as a 2-input 1-output switch. The basic configuration of the hazard elimination circuit according to claim 1 is that, as shown in the principle diagram of FIG. 1, data (ALM) including a hazard that does not need to be input is input as D input, and Q output is performed by the clock (CLK) of simultaneous input. Flip-flop FF to get output data (ALM 1) as
(3), the output data (ALM 1), and the output data (ALM 1)
And a hazard remover (6) for taking a logical product (AND) with the output of the n-stage flip-flop FF (17), which is delayed by n clocks by 1 clock by the input clock (CLK) and is output, Output of the hazard removal unit (6) (ALM
Configure the hazard elimination circuit so that 4) is used as its output data. Next, as shown in the principle diagram of FIG. 1, the basic configuration of the hazard elimination circuit of claim 2 for data (ALM) containing an output hazard when an input-side hazard regularly occurs is Data (ALM)
, And the PN pattern clock (CLK ₁ ) of the output of the PN generator (1) that changes the clock (CLK) of simultaneous input at random is output data as Q output.
A flip-flop FF (4) for obtaining (ALM 2), the output data (ALM 2) and the output data (ALM 2) are input, and output by delaying one clock by n clocks by the clock (CLK). And a hazard removal unit (6) that takes the logical product (AND, 18) with the output of the stage flip-flop FF (17), and uses the output (ALM 4) of the hazard removal unit (6) as its output data To configure. Next, the output data (AL
The basic configuration of the hazard elimination circuit of claim 3 for M) is as shown in the principle diagram of FIG. 1, in which data (ALM) including the hazard is input and the output clock (CLK ₁ ) of the PN generator (1) is input. N division generator that further divides the frequency of 1 / n
Flip-flop FF (5) that obtains output data (ALM 3) as Q output by the output clock (CLK ₂ ) of ( ₂ ), input the output data (ALM 3) and the output data (ALM 3), and input the clock And a hazard removal unit (6) that takes a logical product (AND, 18) with the output of the n-stage flip-flop FF (17), which is delayed by n clocks for each clock by (CLK),
The output (ALM 4) of the hazard removing unit (6) is used as its output data. Next, claim 4 is intended for a hazard removal circuit having a reliable and extremely simple structure, and as shown in the principle diagram of FIG.
M) is input and the constant sampling clock (SC) of the input
The counter (8) that counts the number of bits in the high level "H" portion of the ALM between them and the number of bits in the low level "L" portion of the input ALM of the output of the inverter (INV) that inverts the input The counter (7) for counting and the count value ALM _{L of} both counters (7), (8)
A comparison unit (9) for comparing ALM _H is provided, and as the output ALM 5 of the comparison unit (9), the count value ALM _L of the low level "L" counter (7) of the input ALM is high level " H "counter
When it is smaller than the count value ALM _{H in} (8), ALM _L <ALM _H only sends high level "H" as data, and other ALM _L ≥
Configure to output low level "L" at ALM _H. Claim 5 is also directed to a hazard removal circuit having a reliable and simple configuration. As shown in the principle diagram of FIG. 3, data (ALM) including the hazard is input, and constant sampling of the input is performed. An edge detection unit (10) that detects rising and falling edges between clocks (SC) and an even-odd determination unit (11) that determines whether the number of edges of the input is even or odd. Output of the even / odd judgment section (11) ALM
As 6, the configuration is such that when the number of edges between constant sampling clocks (SC) is odd, high level "H" is output as data, and when it is even, low level "L" is output as data. .

[0006]

With reference to the principle diagram of FIG. 1, in claim 1 of the present invention, the input data ALM including a hazard is used as the clock of the flip-flop FF (3) without changing the input clock CLK as it is. The flip-flop FF (3) in bit units
Latch and output data ALM 1 as Q output. In claim 2, the input clock CLK is PN by the PN generator (1).
Flip-flop FF (4) for patterned clock CLK ₁
The input data ALM is latched in the flip-flop FF (4) by using this clock as the clock and the output data ALM 2 is obtained as the Q output. According to claim 3, the clock CLK ₁ of the PN pattern of the output of the PN generator (1) is further divided into 1 / n by the frequency divider n (2), and the clock CLK ₂ is the clock of the flip-flop FF (5). The input data ALM as the flip-flop FF
Latch at (5) and obtain output data ALM 3 as Q output. Then, input each output data ALM 1, ALM 2, ALM 3 to the hazard removal unit (6) in the lower stage, and
Each output data ALM 1, ALM 2, ALM 3 by n-stage flip-flop FF (17) with K, CLK _1, CLK ₂ as sampling clock.
AND circuit (18) that samples and samples the output and ANDs each data ALM 1, ALM 2, ALM 3 of the input
This prevents the output data ALM 4 from being affected by the hazard contained in the input data ALM.

According to claim 4 of the present invention, referring to the principle diagram of FIG. 2, the bit of the state "L" of the input data ALM containing the hazard in a certain period of the cycle of the sampling clock SC of the external input. Number ALM _L and number of bits in state "H" ALM _H
Input clock CLK by counter (7), counter (8)
It is obtained by counting. Then, the lower comparison section (9) compares the count values ALM _L and ALM _H. The output data ALM depends on the large / small of the count values ALM _L and ALM _H.
Outputs "L" / "H" data as 5.

According to the fifth aspect of the present invention, referring to the principle diagram of FIG. 3, the rising and falling edges of the input data ALM including a hazard in a certain period of the cycle of the sampling clock SC of the external input are detected. The edge detection unit (10) detects it. The lower even-numbered odd number judging section (11) judges whether the number of edges of the input data ALM is even or odd. Then, if the judgment result is odd, the data in the state "H" is output, and if it is even, the data in the state "L" is output as the output data ALM 6.

[0009]

FIG. 4 is a block diagram of an embodiment of claims 1 to 3 of the present invention, and FIG. 8 is a time chart of its operation. 5 is a block diagram of the embodiment of claim 4 of the present invention, and FIG. 9 is a time chart of the operation. FIG. 6 is a block diagram of the embodiment of claim 5 of the present invention, and FIG. 10 is a time chart of the operation.

In the configuration diagram of the embodiments of claims 1 to 3 in FIG. 4, the input clock CLK as it is is used as the clock of the flip-flop FF (14) for fetching and outputting the input data ALM including a hazard, in the case of obtaining the output data ALM 1 as its Q output, the input clock CLK to PN generator clock CLK ₁ that PN patterned at (12), flip-flop outputs captures input data ALM FF (15)
Input as the clock of and output data as its Q output
When ALM 2 is obtained, output clock CL of PN generator (12)
The K _1, inputs further divided by n generator clock CLK ₂ obtained by dividing to 1 / n at (13), as the clock of the flip flop FF (16) for outputting captures input data ALM, outputted as Q output Sometimes you get the data ALM 3. The operation of these embodiments is shown in the time chart of FIG. In the time chart of FIG. 8, the frequency division ratio of the n frequency division generation unit (13) of the input clock CLK is divided by 2. Flip-flop FF above
Output data ALM 1, which is each Q output of (14), FF (15), FF (16)
ALM 2 and ALM 3 are the lower N-stage flip-flops
The shift output data input to the hazard removal unit (6) consisting of the FF (17) and the AND circuit (18) and shifted by N stages by the N-stage flip-flop FF (17) and the flip-flop FF.
Input data from (14), FF (15), and FF (16) without any modification. AND circuit (18) ANDs ALM 1, ALM 2, and ALM 3 with each other. Input data ALM 1, ALM 2, ALM 3 to N
Although the number N of N-stage flip-flops FF (17) to be shifted is arbitrary, it is set to one in the time chart of FIG. The clock CLK of the N-stage flip-flop FF (17) of the hazard removal unit (6) uses the input clock CLK as it is. Even if the input data ALM contains a short-term random hazard as shown in the figure and unnecessary pulses are generated in the output of FF (14) and the output of FF (17), the hazard removal unit (6) At the output ALM 4 of the AND circuit (18), the unnecessary pulse is removed and correct output data is obtained.

In the embodiment of claim 4 of FIG. 5, referring to the time chart of FIG. 9, the input data ALM including two hazards is flip-flopped by the input clock CLK.
Latch each bit in FF (19) and input the Q output to the enable terminal EN of the counter (21). Also, the inverted signal obtained by inverting the sign of the Q output of the flip-flop FF (19) by the inverter INV is input to the enable terminal EN of the counter (20). That is, the counter (20) counts the number of bits in the "L" portion of the input data ALM, and the counter (21) counts the input ALM.
The number of bits in the "H" part of is counted, and both count values are compared by the comparison unit (22). Let ALM _{L be} the count value of the counter (20) that counts the number of bits in the "L" part,
If the count value of the counter (21) that counts the number of bits in the "H" part is ALM _H , the comparator (22) outputs
When LM _L <ALM _H (In the example of FIG. 9, ALM _L = 3 <ALM _H = 5
In case of), input high level "H" to FF (23). And if ALM _L ≧ ALM _H (in the example of FIG. 9, ALM _L = 5> ALM
_In case of _H = 3, input low level "L" to FF (23).
The flip-flop FF (23) outputs this high-level "H" input by its own sampling clock SC.
Input to D input and output data as its Q output ALM 5
To get At that time, both counters (20) and (21) are cleared and the count values ALM _L and ALM _H are returned to zero. In the time chart of Fig. 9, two hazards are listed in the ALM of the input data, and these hazards are also captured in FF (19), but the count value ALM _L of the counter (20) and the count of the counter (21) are counted. Output data ALM 5, which is the Q output of FF (23) that samples the output of the comparison unit (22) that compares the value ALM _H with the sampling clock SC, is no longer removed.
This output data ALM 5 has a problem that the sampling clock SC is bad for the count values ALM _L and ALM _{H of} both counters (20) and (21) by making the cycle of the sampling clock SC sufficiently longer than the hazard interval. It has almost no effect.

In the embodiment of claim 5 of FIG. 6, the input data ALM including one hazard is fetched by the input clock CLK by the FF (24) which constitutes the edge detection section (10), and the FF is fetched. The rising and falling edges of the Q output of (24) are detected by the next FF (25) and EX-OR (26). Next, the EX-OR (27) and FF (28) that make up the even-odd judgment section (11)
Determines whether the number of edges between sampling clocks SC is odd or even. If it is odd, FF (28) outputs "H", and if it is even, FF (28) outputs "L". Output. FF (2
When the output of 8) is "H", FF (30) is sent via EX-OR (29).
Output ALM 6 inverts its high level "H" to low level "L". In the time chart of Fig. 10, one hazard is recorded in ALM that is input data, and it is captured by FF (24), FF (25) by the input clock CLK and output, but EX-OR ( 27) and FF (28) see the rising and falling edges between the sampling clocks SC of the output of EX-OR (26), so the ALM edge (falling edge) is one, Hazard edges (rising and falling) are recognized as two even numbers, so a total of 1 + 2 = 3 odd numbers. Therefore, "H" is output from FF (28), and "L" is output as output data ALM 6 from FF (30) in the next stage. Even if the edges of the input data ALM are mixed with the edges of the hazard within a certain period of the sampling clock SC as in this example, the edges of the ALM are recognized as odd numbers, and there is no problem.

[0013]

According to the present invention, since the hazard can be reliably removed from the input data ALM containing unnecessary hazards generated in various forms, there is an effect that high quality output data can be obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a hazard removal circuit according to claims 1 to 3 of the present invention.

FIG. 2 is a principle diagram showing a basic configuration of a hazard elimination circuit according to claim 4 of the present invention.

FIG. 3 is a principle diagram showing a basic configuration of a hazard elimination circuit according to claim 5 of the present invention.

FIG. 4 is a configuration diagram of a hazard removal circuit according to an embodiment of claims 1 to 3 of the present invention.

FIG. 5 is a configuration diagram of a hazard elimination circuit according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a hazard removal circuit according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional hazard removal circuit.

FIG. 8 is a time chart of the operation of the hazard removal circuit according to the first to third embodiments of the present invention.

FIG. 9 is a time chart of the operation of the hazard removal circuit according to the fourth embodiment of the present invention.

FIG. 10 is a time chart of the operation of the hazard removal circuit according to the fifth embodiment of the present invention.

[Explanation of symbols]

(1) and (12) are PN generators, (2) and (13) are n divider generators, and (3)
(14), (4) (15), (5) (16) is a flip-flop FF, (6) is a hazard removal unit, (7) (20), (8) (21) is a counter, and (9) ( twenty two)
Is a comparison unit, (10) is an edge detection unit, (11) is an even-odd judgment unit, (17) is an N-stage flip-flop that is a constituent element of the hazard removal unit (6), and (18) is a configuration of the hazard removal unit 6. Element AND
A circuit, (19) is an input flip-flop FF, (23) is a sample output flip-flop FF by the sampling clock SC, (24) is an input flip-flop FF of a component of the edge detection unit 10, and (25) is The next stage flip-flop FF of the component of the edge detection unit 10, (26) is an exclusive OR circuit EX-OR for the output of the component of the edge detection unit 10, and (27) is a component of the even-odd determination unit 11. The exclusive OR circuit EX-OR of (28) is the middle-stage flip-flop F of the constituent elements of the even-odd determination unit 11.
F, (29) is an exclusive OR circuit EX-OR for the output of the components of the even / odd determination section 11, (30) is a flip-flop FF for the output of the components of the even / odd determination section 11, and ALM is a hazard. Included input data, ALM 1, ALM 2, ALM 3 are Q output data of flip-flops (3) (14), (4) (15), (5) (16), ALM
4, ALM 5 and ALM 6 are the output data of the hazard elimination circuit of the present invention, CLK is the input clock, and CLK ₁ is the input clock CLK.
The PN-patterned clock CLK ₂ is a clock obtained by further dividing the PN-patterned clock CLK ₁ by n.

Claims (5)

[Claims] 1. A hazard elimination circuit for eliminating unnecessary hazards generated in necessary data on the input side at the output side, the data (ALM) including the hazards not requiring input.
Flip-flop FF (3) which receives as D input and obtains output data (ALM 1) as Q output by simultaneous input clock (CLK), this output data (ALM 1) and this output data (ALM 1) A hazard removing unit (6) for taking a logical product (AND) with the output of an n-stage flip-flop FF (17) which is input and delayed by 1 clock by n clocks according to the input clock (CLK), and outputs the hazard. Output of remover (6)
Hazard removal circuit characterized by using (ALM 4) as its output data. 2. Data including a hazard that does not require input (A
LM) is input as D input, and the clock (C
Flip-flop FF that obtains output data (ALM 2) as Q output by PN patterned clock (CLK ₁ ) of PN generator (1) output that randomly changes LK)
(4), the output data (ALM 2), and the output data (ALM 2)
And a hazard remover (6) for taking a logical product (AND) with the output of the n-stage flip-flop FF (17) which delays and outputs one clock by n clocks by the input clock (CLK). A hazard elimination circuit characterized in that the output (ALM 4) of the hazard elimination unit (6) is used as its output data. 3. Data (A including an unnecessary hazard)
LM) as a D input and further divides the PN-patterned clock (CLK ₁ ) of the output of the PN generator (1) into 1 / n, the output clock (CLK of the n-divider generator (2) ₂ )
A flip-flop FF (5) that obtains the output data (ALM 3) as the Q output, the output data (ALM 3), and the output data (A
A hazard removing unit (6) for taking a logical product (AND) with the output of the n-stage flip-flop FF (17) which inputs the LM3) and delays by 1 clock by 1 clock by the input clock (CLK), Output of the hazard removal unit (6) (ALM
Hazard elimination circuit characterized by using 4) as its output data. 4. Data (A including an unnecessary hazard)
High level during constant sampling clock (SC) of LM "
A counter (8) for counting the number of bits in the H "part and the input data
The input data with the sign of the data (ALM) inverted (INV)
(ALM) Low level between the sampling clocks (SC)
Counter (7) that counts the number of bits in the "L" part and both
Unta (7_,8) Count value (ALM_L, ALM_H) Comparing part
(9) and the output (ALM 5) of the comparison unit (9) is input.
Counter (7) for low level "L" of force data (ALM)
Numerical value (ALM_L) Is high level "H" counter (8) count value (AL
M _H) Is smaller than (ALM_L <ALM_H) As data
Send high level "H", otherwise (ALM_L≧ ALM_H)
Hazard characterized by outputting low level "L"
Removal circuit. 5. Data (A including an unnecessary hazard)
LM) edge detection unit (10) for detecting rising and falling edges, and whether the number of edges between the constant sampling clock (SC) of the input data (ALM) is an even number or an odd number If the number of said edges is odd, the high level "H" is output as the output (ALM 6) of the even / odd judgment section (11) A hazard removal circuit characterized by outputting a low level "L".