JPH07226565A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce leak current and improve luminous efficiency, in TTG structure wherein two electrodes different in polarity are arranged on the upper surface. CONSTITUTION:A first semiconductor layer 34a of first conductivity type is formed on the upper side of an active layer 36 of a ridge waveguide M1. A second semiconductor layer 37 of second conductivity type is formed on the lower side of the active layer 36. A third semiconductor layer 37a of second conductivity type is formed on the side part of the second semiconductor layer 37. A first electrode 40 is formed on the first semiconductor layer 34a. A second electrode 41 is formed on the third semiconductor layer 37a. A current constriction part 33 of inverse hetero structure is formed in a part between the first semiconductor layer 34a and the third semiconductor layer 37a. Trenches 45 for preventing parasitic capacitance are formed on the side part of the current constriction part 33. The generation of a leak path is prevented by the current constriction part 33 and the trenches 45 for preventing parasitic capacitance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device as a wavelength tunable laser used as a light source of an optical frequency division multiplexing system or a local light source for reception in coherent optical communication, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional wavelength tunable semiconductor device (laser device) has been researched and developed mainly for increasing the wavelength tunable width. Figure 25 shows IEEE PHOTO in March 1993.
NICS TECHNOLOGY LETTERS, Vol.5, NO.3 Page 273 to 273
This is a conventional example of a tunable laser shown on page 275. This structure is called a double waveguide (Tunable Twin-Guide: TTG) structure, and it is a structure that currently provides the maximum continuous wavelength tunable width in principle. The structure and operating principle of such a conventional example will be briefly described.

On the p-type InP substrate 1, the p-type InP buffer layer 2, the undoped tuning layer 8, the n-type InP spacer layer 7, the undoped active layer 6, the diffraction grating layer 5, and the lower part of the p-type InP buffer layer 4. Are sequentially formed, and both side portions are removed by etching so that the width of the active layer becomes 1 to 2 μm to form the ridge waveguide R1. Then, both sides of the ridge waveguide R1 are filled with the n-type InP layer 3 (buried layer), and then the upper portion of the p-type InP buffer layer 4 and the p-type InGaAsP contact layer 13 are sequentially formed on the upper surface side of these. Then, the p-type InGaAsP contact layer 13 and the p-type InP buffer layer 4 are partially removed to remove the n-type In.
A part of the upper surface of the P layer 3 is exposed, and a part of the exposed upper surface of the n-type InP layer 3 and the p-type I corresponding to above the active layer 6 are exposed.
The insulating film 9 is patterned in a region other than the upper surface of the nGaAsP contact layer 13. Next exposed n-type InP layer 3
Of the p-type InGa corresponding to the upper part of the active layer 6 while patterning the n-side electrode 11 in a region including a part of the upper surface of
The p-side electrode 10 is patterned on the upper surface of the AsP contact layer 13, and the p-side electrode 12 is further formed on the back surface.

Reference numeral 20 in FIG. 25 is a current path for generating a laser beam. The current flowing into the tuning layer 8 is indicated by 22. That is, the active layer 6 and the tuning layer 8 can be electrically controlled independently with the n-type InP spacer layer 7 interposed therebetween. The electric field distribution of the generated laser light is distributed over the diffraction grating layer 5, the active layer 6, the n-type InP spacer layer 7, and the tuning layer 8. Therefore, the current flowing through the tuning layer is changed while keeping the gain of the laser light constant while keeping the current flowing through the active layer 6 constant, and the refractive index of the tuning layer is changed by the plasma effect to change the equivalent refractive index felt by the light. Then, the oscillation wavelength of the laser light is changed. The oscillation wavelength λ of the laser light and the equivalent refractive index n _eff have the following relationship.

Λ = 2n _eff Λ, where Λ is the period of the diffraction grating.

When the change in the equivalent refractive index due to the injection of a current into the tuning layer is Δn _eff , the obtained wavelength change amount Δλ is Δλ = 2Δn _eff Λ. Specifically, by injecting a current of 50 mA into the tuning layer 8, Δλ = 4.7 nm, which is a large wavelength tunable width as compared with wavelength tunable semiconductor laser devices having other structures. In this way, the structure in which the active layer 6 and the tuning layer 8 are double waveguides is effective for increasing the wavelength tunable width.

[0007]

[Problems to be Solved by the Invention]
In the structure, since the n-type InP spacer layer 7 has to be electrically taken out to the outside, it is necessary to fill both sides of the ridge waveguide R1 with the n-type InP layer 3. Therefore, as shown in FIG. 25, the leakage current 21 flowing through the n-type InP layer 3 without flowing through the active layer 6 from the p-type InP buffer layer 4 is increased, and the laser characteristics are deteriorated. ,
Problems such as insufficient light output occur.

In view of the above problems, the present embodiment has an object to provide a semiconductor device with reduced leakage current and high luminous efficiency, and a manufacturing method thereof.

[0009]

According to a first aspect of the present invention, there is provided a ridge waveguide having an active layer, and a first conductive type first semiconductor layer formed above the active layer. And a second conductive type second layer formed under the active layer.
Semiconductor layer, a third semiconductor layer of a second conductivity type that is adjacent to the side of the ridge waveguide and is connected to the second semiconductor layer, and is formed on the upper side of the first semiconductor layer. Leakage current including a first electrode and a second electrode formed on the upper side of the third semiconductor layer, and preventing a leakage current between the first semiconductor layer and the third semiconductor layer. A preventive means is provided.

According to a second aspect of the present invention, a current constriction portion having a thyristor structure is provided in a part between the first semiconductor layer and the third semiconductor layer.

According to a third aspect of the present invention, a parasitic capacitance prevention groove for preventing parasitic capacitance is formed in a part between the first semiconductor layer and the third semiconductor layer. It is something.

According to a fourth aspect of the present invention, a parasitic capacitance preventing groove for preventing parasitic capacitance is formed on the side of the current constriction portion.

According to a fifth aspect of the present invention, the substrate is set to have a first conductivity type, and a tuning layer is provided between the substrate and the second semiconductor layer in the ridge waveguide. And a third electrode is formed on the lower surface of the substrate to form a double waveguide structure.

According to a sixth aspect of the present invention, the second semiconductor layer and the third semiconductor layer are continuously formed by using the same material.

According to a seventh aspect of the present invention, the second semiconductor layer and the third semiconductor layer are continuous with each other in at least one of the front end portion and the rear end portion, and at least the front end portion and the rear end portion are formed. The current constriction portion is formed between the second semiconductor layer and the third semiconductor layer in an intermediate portion sandwiched by the rear end portions.

According to an eighth aspect of the present invention, the second semiconductor layer and the third semiconductor layer are continuous with each other in at least one of a front end portion and a rear end portion, and at least the front end portion and the rear end portion are formed. The parasitic capacitance prevention groove is formed between the second semiconductor layer and the third semiconductor layer in an intermediate portion sandwiched by the rear end portions.

According to a ninth aspect of the present invention, in the double waveguide structure, the parasitic capacitance preventing groove is formed deeper than the bottom surfaces of the tuning layer and the third semiconductor layer.

The means for solving the problem according to claim 10 of the present invention is
In the double waveguide structure, the parasitic capacitance prevention groove is formed to a depth reaching the substrate.

According to an eleventh aspect of the present invention, there is provided a semiconductor device as a wavelength tunable laser, comprising a front end portion, a rear end portion and an intermediate portion, the intermediate portion being a part of an upper surface of a substrate. A ridge waveguide having an active layer in an intermediate layer region, a first conductivity type first semiconductor layer formed above the active layer in the ridge waveguide, and a ridge waveguide in the ridge waveguide. A second semiconductor layer of a second conductivity type formed below the active layer, and a second semiconductor layer of a second conductivity type that is adjacent to the side of the ridge waveguide and is connected to the second semiconductor layer. Third semiconductor layer, a first electrode formed on the upper side of the first semiconductor layer, and a second electrode formed on the upper side of the third semiconductor layer, the first semiconductor layer And a current constriction portion having a thyristor structure is provided in a part between the third semiconductor layer and the third semiconductor layer. A parasitic capacitance preventing groove for preventing parasitic capacitance is formed on the side of the portion, and the second semiconductor layer and the third semiconductor layer are connected to each other in at least one of the front end portion and the rear end portion. The current constriction portion is formed between the second semiconductor layer and the third semiconductor layer at least in an intermediate portion sandwiched by the front end portion and the rear end portion.

The problem solving means according to claim 12 of the present invention is
The leakage current prevention means is composed of a high resistance layer formed on the upper surface of the third semiconductor layer, and an end portion of the high resistance layer in contact with the ridge waveguide is as close as possible to an end portion of the active layer. Is close to.

The means for solving the problem according to claim 13 of the present invention is
A high resistance layer for preventing leakage current is provided between the substrate and the third semiconductor layer on the lower surface of the third semiconductor layer.

The problem solving means according to claim 14 of the present invention is
A tuning layer, a second semiconductor layer having a second conductivity type, an active layer, and a first conductivity type first layer are provided on a first conductivity type substrate.
A step of sequentially stacking a plurality of layers such as the semiconductor layer and connecting the third semiconductor layer of the second conductivity type exposed above to the second semiconductor layer, and selectively forming these layers. A ridge forming step of etching and removing to form a ridge waveguide, a burying forming step of burying and forming a current narrowing portion on the side of the ridge waveguide, and an outer portion of the current narrowing portion is selectively removed by etching. A groove forming step of forming a parasitic capacitance preventing groove, a first electrode on the upper surface of the first semiconductor layer, a second electrode on the upper surface of the third semiconductor layer, and a third electrode on the lower surface of the substrate. And an electrode forming step of forming electrodes respectively.

The problem solving means according to claim 15 of the present invention is
The stacking step includes a continuous formation step in which the third semiconductor layer is continuously formed at the same time using the same material when the second semiconductor layer is formed, and the active layer and the first semiconductor layer are formed after the formation of the first semiconductor layer. And an exposing step of exposing the third semiconductor layer by etching away a side portion of the first semiconductor layer.

The problem solving means according to claim 16 of the present invention is
A first stacking step of sequentially stacking a plurality of layers such as a tuning layer, a second semiconductor layer of a second conductivity type, and an active layer on a substrate of a first conductivity type, and selectively removing these layers by etching. And a ridge forming step of forming a ridge waveguide, and a burying forming step of burying and forming a third semiconductor layer of the second conductivity type on the side of the ridge waveguide so as to connect to the second semiconductor layer. A high resistance layer forming step of forming a high resistance layer on the upper surface of the third semiconductor layer, and forming a first conductivity type first semiconductor layer on the upper surfaces of the ridge waveguide and the high resistance layer. And a second electrode on the upper surface of the first semiconductor layer, a second electrode on the upper surface of the third semiconductor layer, and a third electrode on the lower surface of the substrate. And a forming step.

The problem solving means according to claim 17 of the present invention is
In the high resistance layer forming step, the high resistance layer having a semi-insulating crystal structure is formed by doping impurities on the upper surface of the third semiconductor layer.

The problem solving means according to claim 18 of the present invention is
In the high resistance layer forming step, after forming the third semiconductor layer, predetermined ions are implanted into the upper surface of the third semiconductor layer to form the high resistance layer.

The problem solving means according to claim 19 of the present invention is
A proton is used as the predetermined ion.

The problem solving means according to claim 20 of the present invention is
Boron is used as the predetermined ion.

[0029]

In the semiconductor device according to claim 1 of the present invention, the first
A voltage is applied between the first electrode and the second electrode, and a current is passed through the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer to drive the active layer. At this time, it is possible to prevent a leakage current from being generated between the first semiconductor layer and the third semiconductor layer by the leakage current prevention means, and it is possible to efficiently pass the current to the active layer.

In the semiconductor device according to claim 2 of the present invention,
When a voltage is applied between the first electrode and the second electrode to drive the active layer, a leakage current occurs in a part between the first semiconductor layer and the third semiconductor layer in the current constriction portion. It is possible to prevent this from occurring, and it is possible to efficiently pass a current through the active layer.

In the semiconductor device according to claims 3 and 4 of the present invention, when a voltage is applied between the first electrode and the second electrode to drive the active layer, the first parasitic capacitance preventing groove is used.
The parasitic capacitance generated in a part between the semiconductor layer and the third semiconductor layer can be prevented, and the leakage current in this part can be prevented, so that the current can be efficiently supplied to the active layer.

In the semiconductor device according to claim 5 of the present invention,
Since the double waveguide structure is formed, a large wavelength tunable width can be obtained by injecting a current into the tuning layer. In such a double waveguide structure, in particular, both the first electrode and the second electrode need to be drawn to the upper side of the device, and in this case, leakage current can be prevented and current can be efficiently passed through the active layer. .

In the semiconductor device according to claim 6 of the present invention,
By simultaneously forming the second semiconductor layer and the third semiconductor layer, the time required for the stacking process can be shortened as compared with the conventional example.

In the semiconductor device according to the seventh and the eleventh aspects of the present invention, even when the second semiconductor layer is isolated from the third semiconductor layer at the current constriction portion in the intermediate portion to prevent leakage current, The second semiconductor layer and the second electrode can be electrically connected via the third semiconductor layer of at least one of the front end portion and the rear end portion, and the electrical wiring to the second semiconductor layer can be electrically connected to the second semiconductor layer. It can be pulled out to the upper surface side of the device through the two electrodes.

In the semiconductor device according to claim 8 of the present invention,
Even when the second semiconductor layer is isolated from the third semiconductor layer by the parasitic capacitance preventing groove in the intermediate portion to prevent a leakage current, the second semiconductor layer and the second electrode are separated from each other by the front end portion and the rear end portion. It is possible to electrically connect via at least one of the third semiconductor layers, and the electrical wiring to the second semiconductor layer can be drawn to the upper surface side of the device through the second electrode.

In the semiconductor device according to the ninth and tenth aspects of the present invention, the tuning layer can be completely isolated from the third semiconductor layer in the region where the parasitic capacitance preventing groove is formed, and the double waveguide structure can be obtained. The leakage current can be reduced for any of the waveguides. Especially claim 1
At 0, the junction area between the substrate and the third semiconductor layer can be significantly reduced by the parasitic capacitance preventing groove, so that the leakage current between the substrate and the third semiconductor layer can be significantly reduced.

In the semiconductor device according to claim 12 of the present invention, when a voltage is applied between the first electrode and the second electrode to drive the active layer, the high resistance layer causes the first semiconductor layer and the Three
It is possible to prevent a leakage current from being generated in a portion between the semiconductor layer and the semiconductor layer, and to efficiently pass a current to the active layer. In this case, by making the end of the high resistance layer as close as possible to the end of the active layer, the contact area between the first semiconductor layer and the third semiconductor layer can be reduced, and the leakage current can be significantly reduced. it can. In particular,
If the end of the high resistance layer is overlaid and closely adhered to the end of the active layer,
It is possible to reliably prevent contact between the first semiconductor layer and the third semiconductor layer.

In the semiconductor device according to claim 13 of the present invention, in the double waveguide structure, the leakage current between the substrate and the third semiconductor layer is significantly increased in the high resistance layer on the lower surface of the third semiconductor layer. Can be reduced to

In the method for manufacturing a semiconductor device according to claim 14 of the present invention, when it is necessary to draw both the first electrode and the second electrode above the device in the double waveguide structure, the first A current constriction portion and a parasitic capacitance prevention groove can be arranged between the semiconductor layer and the third semiconductor layer,
Leakage current that occurs between the first semiconductor layer and the third semiconductor layer can be prevented.

In the method of manufacturing a semiconductor device according to the fifteenth aspect of the present invention, by forming the second semiconductor layer and the third semiconductor layer at the same time, the time required for the stacking process can be shortened as compared with the conventional example.

In the method for manufacturing a semiconductor device according to the sixteenth aspect of the present invention, when the third semiconductor layer is formed by embedding laterally in the ridge waveguide, the high resistance layer is formed on the upper surface of the third semiconductor layer. After that, since the first semiconductor layer is formed on the upper surfaces of the ridge waveguide and the high resistance layer, the third semiconductor layer can be isolated from the first semiconductor layer, and the generation of leakage current during this can be prevented.

In the method for manufacturing a semiconductor device according to the seventeenth aspect of the present invention, since the high resistance layer is formed by doping the upper surface of the third semiconductor layer with impurities, the third semiconductor layer and the high resistance layer are formed. Can be stacked by continuous formation, which facilitates the stacking work.

In the method of manufacturing a semiconductor device according to the eighteenth aspect of the present invention, since the high resistance layer is formed by implanting predetermined ions into the upper surface of the third semiconductor layer after the formation of the third semiconductor layer, the third semiconductor layer is formed. Further, the high resistance layer can be laminated by continuous formation, which facilitates the laminating work. Moreover, since the thickness of the high resistance layer can be freely set after the step of forming the third semiconductor layer, the end of the high resistance layer is overlapped with the end of the active layer, or the end of the high resistance layer is formed with the active layer. When the edge portion is made as close as possible, even if an error occurs in the formation thickness of the third semiconductor layer, the formation position of the high resistance layer can be set as desired by adjusting the ion implantation depth later.

In the method for manufacturing a semiconductor device according to the nineteenth aspect of the present invention, by using protons as the ions to be implanted, it is possible to perform implantation to a deeper position than when other ions are used, and the high resistance layer is formed. The formation position of can be set deeply, and the work of overlapping the end of the high resistance layer with the end of the active layer or bringing the end of the high resistance layer as close as possible to the end of the active layer is performed reliably. be able to.

In the method for manufacturing a semiconductor device according to the twentieth aspect of the present invention, by using boron as the ions to be implanted, a thermally stable high resistance layer can be obtained, and the performance is improved even if heat treatment is applied. A semiconductor device that does not deteriorate can be obtained.

[0046]

【Example】

[First Embodiment] FIG. 1 is a partially sectional perspective view showing a state before a dicing cut of a semiconductor laser device as a semiconductor device of a first embodiment of the present invention, and FIG. 2 is a perspective view showing a completed state, FIG. 3 is a front view of the semiconductor device. The semiconductor device has a double waveguide structure (TTG structure) used as a light source of an optical frequency division multiplexing system for increasing the transmission capacity by multiplexing lights of different frequencies in coherent optical communication or a local light source for reception. The wavelength tunable laser oscillation wavelength can be arbitrarily changed. As shown in FIG. 3, the semiconductor device has a front end face vicinity (front end portion) P1 and a rear end face vicinity (rear end face) P formed with a depth of about 50 μm.
2 laminated structure and about 8 sandwiched between the front and rear end portions P1 and P2
The layered structure of the intermediate portion P3 formed with a depth of 00 μm is different.

The laminated structure of the intermediate portion P3 of the semiconductor device is as shown in the cross section of FIG. In FIG. 1, 31 is a p-type (first conductivity type) InP substrate and 32 is a p-type InP substrate 3.
1 is a p-type InP buffer layer, 33 is a current narrowing portion (leakage current preventing means) of a thyristor structure embedded so as to concentrate the driving current in the ridge waveguide M1 as an active region, and 33a is a current narrowing. P-type In of part 33
P layer, 33b are also n-type (second conductivity type) InP layers,
33c is a p-type InP layer, and 34 and 34a are p-type InP layers.
P buffer layer (first semiconductor layer), 35 is a diffraction grating layer,
36 is an active layer, 37 is an n-type InP spacer layer (second semiconductor layer), and 37a is an n-type In formed of the same material as the n-type InP spacer layer (second semiconductor layer) 37 at the same time.
P layer (third semiconductor layer), 38 is tuning layer, 39
Is an insulating mask, 40 is a p-side electrode (first electrode), 41 is an n-side electrode (second electrode), 42 is a p-side electrode (third electrode), 43 is a p-type InGaAsP contact layer, and 45 is Parasitic capacitance prevention groove (leakage current prevention means) for reducing the parasitic capacitance to cut off the leakage current, M2 is a mesa formed in the parasitic capacitance prevention groove 45, and Dc1 is a dicing cut line. Here, the depth of the parasitic capacitance preventing groove 45 is at least the tuning layer 38 and the n-type InP layer 37a in order to completely isolate the tuning layer 38 from the n-type InP layer (third semiconductor layer) 37a.
Must be set to be deeper than the bottom surface of the p-type InP substrate 31, for example, in this embodiment.

On the other hand, the structure of the front and rear end portions P1 and P2 of the semiconductor device is as shown in FIGS.
p-type InP buffer layer 32, tuning layer 38, n-type InP spacer layer 37, active layer 36, diffraction grating layer 35,
p-type InP buffer layers 34 and 34a and p-type InGa
Although the AsP contact layer 43 is sequentially laminated, the structure is similar to the cross-sectional structure of the intermediate portion P3 shown in FIG. 1, but the front and rear end portions P1 and P2 have parasitic capacitances on both sides as shown in FIGS. The prevention groove 45 and the current constriction portion 33 are omitted, and the n-type InP spacer layer 37 (second semiconductor layer) is provided.
Is different from the sectional structure of the intermediate portion P3 shown in FIG. 1 in that it is extended as an n-type InP layer 37a (third semiconductor layer) to the side edge of the device and is in close contact with the outer n-side electrode 41. There is.

In the semiconductor device having the above structure, the n-type InP spacer layer 37 sandwiched between the active layer 36 and the tuning layer 38 in the ridge waveguide M1 has the current constricting portion 3 on both sides.
3. Furthermore, the n-type InP spacer layer 37 is isolated from the outer n-side electrode 41 because it is sandwiched by the parasitic capacitance preventing groove 45, and therefore, the n-type In in the ridge waveguide M1 is formed.
Leakage current can be prevented from flowing between the P spacer layer 37 and the outer n-side electrode 41, and high luminous efficiency can be obtained.

However, with the above configuration, the n-type I
The connection between the nP spacer layer 37 and the outer n-side electrode 41 poses a problem, but as shown in FIGS. 2 and 3, in the regions of the front and rear end portions P1 and P2 near the dicing cut line Dc1, the current constriction portion 33 is formed. Embedded growth and formation of the parasitic capacitance preventing groove 45 are not performed, so that the n-type InP layer 37 is formed.
It is possible to form a (third semiconductor layer) up to the side end portion of the device and directly connect to the outer n-side electrode 41, so that the connection between the two can be secured.

Next, the manufacturing process of the semiconductor device of this embodiment will be described. First, as shown in FIG. 4, on the p-type InP substrate 31, the p-type InP buffer layer 32, the tuning layer 38,
The n-type InP spacer layer 37, the n-type InP layer 37a, the active layer 36, the diffraction grating layer 35, and the p-type InP buffer layer 3
4 are sequentially formed by the epitaxial growth method. here,
Since the n-type InP spacer layer 37 and the n-type InP layer 37a are substantially the same member, they are simultaneously formed by using the same material. Next, a long strip-shaped insulating mask 39a is formed from the back to the front using a SiO ₂ film or a SiN film only on the central portion of the upper surface of the p-type InP buffer layer 34 when viewed from the front. Then, the p-type InP buffer layer 34 and the diffraction grating layer 3
5 and the area of the diffraction grating layer 35 of the active layer 36 where the insulating mask 39a is not formed are removed by etching until the upper surface of the n-type InP layer 37a is exposed as shown in FIG.

Then, after removing the insulating mask 39a, as shown in FIG. 6, the exposed end of the n-type InP layer 37a in the front view, the central part of the p-type InP buffer layer 34 in the front view, and finally the device unit. An insulating mask 39b having a substantially king-shaped plan view is formed by using a SiO ₂ film, a SiN film, or the like on the dicing cut line Dc1 when separated for each. Then, as shown in FIG. 7, in the plan view region where the insulating mask 39b is not formed, the p-type InP buffer layer 32,
Tuning layer 38, n-type InP spacer layer 37, n-type InP layer 37a, active layer 36, diffraction grating layer 35 and p
The type InP buffer layer 34 is removed by etching to a substantially J type in a front view at a depth that reaches a part of the upper layer portion of the p type InP substrate 31. At this time, the width of the active layer 36 is set to 1 to 2 μm, and a ridge waveguide M1 having a raised (mesa) shape is formed in the central portion of the front view of each device from the back to the front.

Next, as shown in FIG. 8, the p-type InP layer 33a, the n-type InP layer 33b and the p-type InP of the current confinement portion 33 are formed in the regions removed by etching on both sides of the ridge waveguide M1.
The layer 33c is sequentially embedded and grown. However, the insulating mask 39b on the dicing cut line Dc1
Since the region covered with is not etched away in the etching removal step of FIG. 7, the ridge waveguide M1 is not formed, and thus the dicing cut line Dc is not formed.
The cross section at 1 is as shown in FIG.

Thereafter, the insulating mask 39b is removed with a solvent, and only the exposed end portion of the n-type InP spacer layer 37a in a front view is again exposed to the SiO ₂ film or S as shown in FIG.
An insulating mask 39c is formed using an iN film or the like, and then,
Part of the upper surface of the p-type InP layer 33c and the p-type I
The p-type InP buffer layer 34a and the p-type InGaAsP contact layer 43 are selectively formed only on the upper surface of the nP buffer layer 34.

Next, the insulating mask 39c is removed, and the exposed n-type InP spacer layer 37a is formed as shown in FIG.
Front end portion of the p-type InGaAsP contact layer 4
S in the center part of the front view of FIG. 3 and on the dicing cut line Dc1 when the devices are finally separated for each device.
An insulating mask 39d having a substantially king-shaped plan view is formed using an iO ₂ film or a SiN film. Here, the width of the portion of the insulating mask 39d formed in the central portion of the p-type InGaAsP contact layer 43 in front view is larger than the width (1 to 2 μm) of the active layer 36, that is, the width of the ridge waveguide M1. I will keep it. Then, as shown in FIG. 12, the insulating mask 39d
The planar view region where no is formed is removed by etching to form a substantially J-shaped parasitic capacitance preventing groove 45 in front view for reducing the parasitic capacitance. As a result, the ridge M2 is formed in the center of the front view of each device from the back to the front.

Thereafter, as shown in FIG. 1, a region where no electrode is formed is covered with an insulating mask 39, and a p-side electrode 40 and an n-side electrode 41 are provided on the upper surface portion where the insulating mask 39 is not formed.
P-side electrodes 42 are formed on the entire lower surface of the p-type InP substrate 31. Thereafter, dicing cutting is performed for each device unit, and the individual semiconductor devices shown in FIG. 2 are completed.

[Second Embodiment] FIG. 13 is a diagram showing a semiconductor laser device as a semiconductor device according to a second embodiment of the present invention. The semiconductor device of this embodiment is of the wavelength tunable type similar to that of the first embodiment, and 51 in FIG. 13 is p-type In.
P substrate, 52 is a p-type InP buffer layer formed on the p-type InP substrate 51, and 53 is an n-type InP layer (buried layer:
Third semiconductor layer), 54 and 54a are p-type InP buffer layers (first semiconductor layers), 55 is a diffraction grating layer, 56 is an active layer, 57 is an n-type InP spacer layer (second semiconductor layer),
58 is a tuning layer, 59 is an insulating film, 60 is a p-side electrode (first electrode), 61 is an n-side electrode (second electrode), 62
Is a p-side electrode (third electrode), 63 is a p-type InP contact layer, 65 is a high resistance layer (leakage current preventing means) of InP semi-insulating crystal structure formed by impurity doping, and 66 is the n-type InP layer 53 and the n-side electrode (second electrode) 61
M3 is a ridge waveguide in the form of a ridge (mesa) for electrically connecting and.

As impurities to be doped in the high resistance layer 65, Fe, Co, Cr, Ti, V, Mn or the like is used. Here, the p-type InP buffer layer 54
The side surface of the high resistance layer 65 is formed on the side surface of the active layer 56 so as to surely prevent a leak path from the n-type InP layer 53 to the n-type InP layer 53.
It is desirable to make contact with at least a part of the side surface of the. By providing the high resistance layer 65, p-type In
Since the leak path flowing from the P buffer layer 54 to the n-type InP layer 53 can be effectively blocked, the leak current, which has been a problem in the conventional example, can be significantly reduced.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. First, as shown in FIG. 14, on a p-type InP substrate 51, a p-type InP buffer layer 52, a tuning layer 58, an n-type InP spacer layer 57, an active layer 56, a p-type InP buffer layer 54b, and a diffraction grating layer 55. Then, a p-type InP buffer layer (diffraction grating buried layer) 54c is sequentially formed by epitaxial growth.

Here, as shown in FIG. 15, p-type InP
For example, SiN or SiO may be formed on a part of the upper surface of the buffer layer 54c.
A strip-shaped insulating mask 59e is formed using N or the like. Then, the region where the insulating mask 59e is not formed is p-type In.
The upper layer portion of the P buffer layer 52 is removed by etching, and a ridge waveguide M3 having a raised (mesa) shape is formed below the insulating mask 59e.

Next, as shown in FIG. 16, the n-type I is formed on both sides of the previously formed ridge using the insulating masks 59e as masks.
The nP layer 53 and the high resistance layer 65 are selectively grown sequentially. The high resistance layer 65 is made of, for example, Fe, C in InP.
It is formed by doping impurities such as o, Cr, Ti, V or Mn. Here, the layer thicknesses of the n-type InP layer 53 and the high resistance layer 65 are set such that the side surface of the ridge waveguide M3 is in contact with at least a part of the side surface of the active layer 56. To do.

Then, as shown in FIG. 17, the insulating mask 5
After removing 9e, a p-type InP buffer layer 54d and a p-type InP contact layer 63 are grown. Next, as shown in FIG. 18, the p-type InP buffer layer 54d and the p-type In are formed.
A part of the region of the P contact layer 63 which is separated from the ridge waveguide M3 is removed by etching to form an opening 66, and a part of the upper surface of the high resistance layer 65 is exposed upward.

Then, as shown in FIG. 19, an insulating mask 59f for current confinement made of, for example, SiO is formed on the entire upper surface except for the upper portion of the ridge waveguide M3 and the bottom portion of the opening 66. Then, as shown in FIG. 20, a part of the high resistance layer 65 is removed by etching using the insulating mask 59f formed in the opening 66 formed previously as a mask, and n
A part of the upper surface of the type InP layer 53 is exposed upward.

Finally, a p-side electrode 60 for injecting a current into the active layer 56, a p-side electrode 62 for injecting a current into the tuning layer 58, and an n-side electrode 61 are formed, as shown in FIG.
The wavelength tunable semiconductor laser device shown in 3 is completed.

[Third Embodiment] FIG. 21 is a diagram showing a semiconductor laser device as a semiconductor device according to a third embodiment of the present invention. Note that, of the reference numerals in FIG. 21, the same portions or regions as those in the second embodiment are designated by the same reference numerals. This embodiment is of the same wavelength tunable type as the second embodiment, but the high resistance layer 65 is formed by impurity doping in the second embodiment to have an InP semi-insulating crystal structure. The present embodiment is different from the second embodiment in that the high resistance layer 67 (leakage current preventing means) is formed by ion implantation. Protons, B (boron) or the like are used as the ions implanted in the high resistance layer 67. And
It is desirable that the high resistance layer 67 be in contact with the active layer 56 and its side surfaces so as to surely prevent a leak path from the p-type InP buffer layer 54 to the n-type InP layer 53. Here, as described above, by using protons in the high resistance layer 67, it is possible to perform implantation to a deeper position than in the case of using other ions, and it is possible to set the formation position of the high resistance layer deep. The work of overlapping the end of the high resistance layer 67 with the end of the active layer 56 can be easily performed.
Further, by using boron for the high resistance layer 67, a thermally stable high resistance layer can be obtained, and a semiconductor device whose performance does not deteriorate even when subjected to heat treatment can be obtained. By providing the high resistance layer 67, it is possible to effectively block the leak path flowing from the p-type InP buffer layer 54 to the n-type InP layer 53. Therefore, similar to the second embodiment.
The leakage current, which has been a problem in the conventional example, can be significantly reduced.

Next, the manufacturing method of this embodiment will be described. First, similar to the second embodiment shown in FIG. 14, a p-type InP buffer layer 52, a tuning layer 58, an n-type InP spacer layer 57, an active layer 56 and a p-type I are formed on a p-type InP substrate 51.
nP buffer layer 54b, diffraction grating layer 55, and p-type In
The P buffer layer (diffraction grating embedded layer) 54c is formed by epitaxial growth.

Here, similarly to the second embodiment shown in FIG. 15, a strip-shaped insulating mask 59e is formed on a part of the upper surface of the p-type InP buffer layer 54c by using, for example, SiN or SiON. Then, the region where the insulating mask 59e is not formed is removed by etching to the upper layer portion of the p-type InP buffer layer 52, and a ridge waveguide M3 having a raised (mesa) shape is formed in the lower direction of the insulating mask 59e.

Next, as shown in FIG. 22, the n-type InP layer 53 is selectively embedded and grown on both sides of the ridge waveguide M3 previously formed using the insulating mask 59e as a mask.
Then, as shown in FIG. 23, on the surface of the n-type InP layer 53,
The high resistance layer 67 is formed by ion implantation of protons.
At this time, the insulating mask 59e is ion-implanted with the insulating mask 59e provided on the upper surface of the ridge waveguide M3. 67 is formed. Further, the implantation depth is set such that the implantation region overlaps and contacts the active layer 56 on the side surface of the ridge waveguide M3.

After removing the insulating mask 59e,
Similar to the second embodiment, the p-type InP buffer layer 54
By forming the d, p-type InP contact layer 63, the opening 66, the p-side electrode 60, the p-side electrode 62 and the n-side electrode 61,
The wavelength tunable semiconductor laser device shown in FIG. 21 is completed.

[Fourth Embodiment] In the second and third embodiments, the side surface of the high resistance layer 65 and the side surface of the active layer 56 are in contact with each other, but this is difficult in terms of manufacturing technology. Side surfaces of the high resistance layers 65 and 67 and the active layer 56 due to
Even if it is not possible to contact the side surface of the high resistance layer 6
By providing 5, 67, the leak path is p-type In
Since the P buffer layer 54 and the n-type InP layer 53 are limited to a small region on the side surface of the ridge in which the P type buffer layer 54 and the n-type InP layer 53 are in direct contact with each other, the leakage current is significantly larger than that when the high resistance layers 65 and 67 are not provided. Will be reduced.

[Fifth Embodiment] In each of the above embodiments, the substrate is set to the first conductivity type (p type), and the tuning layer is provided between the substrate and the second semiconductor layer (spacer layer). Although the double waveguide structure is formed by using the above, the tuning layer may be omitted to form a simple single waveguide structure with the upper electrode taken out.

[Sixth Embodiment] In the second and third embodiments, the high resistance layer is formed only on the upper surface of the third semiconductor layer (n-type InP layer, that is, the buried layer). As described above, the high resistance layer 69 may be formed also on the lower surface of the third semiconductor layer to prevent leakage current between the third semiconductor layer and the electrode on the substrate side. Further, in the first embodiment, a high resistance layer may be formed on the lower surface of the third semiconductor layer (not shown). here,
The high resistance layer 69 may be formed into a semi-insulating crystal structure by impurity doping in the same manner as in the second embodiment, or a predetermined boron, proton, etc. may be formed in the same manner as in the third embodiment. It may be formed by implanting ions.

[0073]

According to claim 1 of the present invention, since the leakage current preventing means is provided, a leakage current is generated between the first semiconductor layer and the third semiconductor layer when driving the active layer. There is an effect that it is possible to prevent the electric current from flowing and the electric current can efficiently flow.

According to the second aspect of the present invention, since the current constriction portion having the thyristor structure is provided, when the active layer is driven,
The leakage current can be prevented from occurring between the first semiconductor layer and the third semiconductor layer, and the current can be efficiently flowed.

According to claims 3 and 4 of the present invention,
Since the parasitic capacitance prevention groove is provided, it is possible to prevent the parasitic capacitance generated between the first semiconductor layer and the third semiconductor layer when driving the active layer, and to prevent the leakage current in this portion. Therefore, there is an effect that the current can be efficiently passed.

According to the fifth aspect of the present invention, since the double waveguide structure is formed, a large wavelength tunable width can be obtained by injecting a current into the tuning layer. In such a double waveguide structure, in particular, both the first electrode and the second electrode need to be drawn to the upper side of the device, and in this case, leakage current can be prevented and current can be efficiently passed through the active layer. There is an effect.

According to claim 6 of the present invention, since the second semiconductor layer and the third semiconductor layer are continuously formed by using the same material, both semiconductor layers can be simultaneously formed, and compared with the conventional example. As a result, the time required for the laminating process can be shortened.

According to claims 7 and 11 of the present invention, while preventing the leakage current by isolating the second semiconductor layer from the third semiconductor layer in the current confinement portion in the intermediate portion,
Second at least one of the front end and the rear end
Since the semiconductor layer and the second electrode are electrically connected via the third semiconductor layer, the luminous efficiency is improved and at the same time, the electrical wiring to the second semiconductor layer is connected to the second electrode. There is an effect that it can be pulled out to the upper surface side of the device through.

According to claim 8 of the present invention, the second semiconductor layer is isolated from the third semiconductor layer by the parasitic capacitance preventing groove in the intermediate portion to prevent leakage current, and at the same time, in the front end portion and the rear end portion, Since the second semiconductor layer and the second electrode are electrically connected via the third semiconductor layer on at least one side, the luminous efficiency is improved and at the same time, the electrical wiring to the second semiconductor layer is achieved. Can be drawn out to the upper surface side of the device through the second electrode.

According to the ninth and tenth aspects of the present invention, the tuning layer can be completely isolated from the third semiconductor layer in the region where the parasitic capacitance preventing groove is formed. The leakage current can be reduced in any of the waveguides. In particular, according to claim 10, the junction area between the substrate and the third semiconductor layer can be significantly reduced by the parasitic capacitance preventing groove, so that the leakage current between the substrate and the third semiconductor layer can be significantly reduced. There is.

According to the twelfth aspect of the present invention, since the end portion of the high resistance layer as the leakage current preventing means is brought as close as possible to the end portion of the active layer, it is possible to reduce the first portion when driving the active layer. The contact area between the semiconductor layer and the third semiconductor layer can be reduced, and the leakage current can be significantly reduced. In particular, if the end of the high resistance layer is overlaid on and closely adhered to the end of the active layer, contact between the first semiconductor layer and the third semiconductor layer can be reliably prevented when the active layer is driven. There is an effect that the leakage current can be surely prevented from occurring.

According to claim 13 of the present invention, in the double waveguide structure, since the high resistance layer is provided also on the lower surface of the third semiconductor layer, the leakage current between the substrate and the third semiconductor layer is reduced. There is an effect that it can be reduced in the high resistance layer.

According to claim 14 of the present invention, in the double waveguide structure, when both the first electrode and the second electrode need to be drawn out to the upper side of the device, the first semiconductor layer and the third semiconductor layer are formed. A current constriction portion and a parasitic capacitance prevention groove can be arranged between the first semiconductor layer and the third semiconductor layer, and a leakage current generated between the first semiconductor layer and the third semiconductor layer can be prevented.

According to the fifteenth aspect of the present invention, since the second semiconductor layer and the third semiconductor layer are formed at the same time, there is an effect that the time required for the laminating step can be shortened as compared with the conventional example.

According to the sixteenth aspect of the present invention, when the third semiconductor layer is embedded and formed laterally of the ridge waveguide,
After the high resistance layer is formed on the upper surface of the semiconductor layer, the first semiconductor layer is formed on the upper surfaces of the ridge waveguide and the high resistance layer, so that the third semiconductor layer can be isolated from the first semiconductor layer. Therefore, there is an effect that leakage current can be prevented from occurring during this period.

According to the seventeenth aspect of the present invention, since the high resistance layer is formed by doping the upper surface of the third semiconductor layer with impurities, the third semiconductor layer and the high resistance layer can be laminated by continuous formation, This has the effect of facilitating the laminating work.

According to the eighteenth aspect of the present invention, since the high resistance layer is formed by implanting predetermined ions into the upper surface of the third semiconductor layer after the formation of the third semiconductor layer, the third semiconductor layer and the high resistance layer are continuously formed. Can be stacked, and the stacking work becomes easy. Moreover, since the thickness of the high resistance layer can be freely set after the step of forming the third semiconductor layer, the end of the high resistance layer is overlapped with the end of the active layer, or the end of the high resistance layer is formed with the active layer. When the edge portion is made as close as possible, even if an error occurs in the formation thickness of the third semiconductor layer, the formation position of the high resistance layer can be set as desired by adjusting the ion implantation depth later. effective.

According to the nineteenth aspect of the present invention, since protons are used as the ions to be implanted, it is possible to perform the implantation to a deeper position as compared with the case of using other ions, and it is possible to set the formation position of the high resistance layer deeply. There is an effect that the end of the high resistance layer can be overlapped with the end of the active layer, or the end of the high resistance layer can be brought as close as possible to the end of the active layer.

According to the twentieth aspect of the present invention, since boron is used as the ions to be implanted, a thermally stable high resistance layer can be obtained, and a semiconductor device whose performance does not deteriorate even when subjected to heat treatment can be obtained. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a front view showing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a perspective view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a perspective view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a front view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a perspective view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 24 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 31 substrate 33 current constriction portion 34a first semiconductor layer 36 active layer 37 second semiconductor layer 37a third semiconductor layer 38 tuning layer 40 first electrode 41 second electrode 42 third electrode 45 parasitic capacitance prevention groove 51 substrate 53 third semiconductor layer 54a first semiconductor layer 56 active layer 57 second semiconductor layer 58 tuning layer 60 first electrode 61 second electrode 62 third electrode 66 high resistance layer 67 high resistance layer P1 Front end P2 Rear end P3 Middle part M1 ridge waveguide M3 ridge waveguide

Claims (20)

[Claims] 1. A ridge waveguide formed on a part of an upper surface of a substrate and having an active layer in an intermediate layer region, and a first ridge waveguide formed above the active layer in the ridge waveguide.
A first semiconductor layer of a conductivity type, a second semiconductor layer of a second conductivity type formed below the active layer in the ridge waveguide, and adjacent to a side of the ridge waveguide. A third semiconductor layer of the second conductivity type connected to the second semiconductor layer, a first electrode formed on the upper side of the first semiconductor layer, and an upper side of the third semiconductor layer on the upper side of the third semiconductor layer. A semiconductor device comprising: a second electrode formed; and a leakage current prevention unit for preventing a leakage current between the first semiconductor layer and the third semiconductor layer. 2. A ridge waveguide formed on a part of an upper surface of a substrate and having an active layer in an intermediate layer region, and a first ridge waveguide formed above the active layer in the ridge waveguide.
A first semiconductor layer of conductivity type, a second semiconductor layer of a second conductivity type formed below the active layer in the ridge waveguide, and adjacent to the side of the ridge waveguide. A third semiconductor layer of a second conductivity type connected to the second semiconductor layer, a first electrode formed on the upper side of the first semiconductor layer, and an upper side of the third semiconductor layer on the upper side of the third semiconductor layer. A semiconductor device comprising a formed second electrode, wherein a current constriction portion having a thyristor structure is provided in a part between the first semiconductor layer and the third semiconductor layer. 3. A ridge waveguide formed on a part of an upper surface of a substrate and having an active layer in an intermediate layer region, and a first ridge waveguide formed above the active layer in the ridge waveguide.
A first semiconductor layer of a conductivity type, a second semiconductor layer of a second conductivity type formed below the active layer in the ridge waveguide, and adjacent to a side of the ridge waveguide. A third semiconductor layer of the second conductivity type connected to the second semiconductor layer, a first electrode formed on the upper side of the first semiconductor layer, and an upper side of the third semiconductor layer on the upper side of the third semiconductor layer. A semiconductor device comprising a formed second electrode, wherein a parasitic capacitance prevention groove for preventing parasitic capacitance is formed in a part between the first semiconductor layer and the third semiconductor layer. 4. The semiconductor device according to claim 2, wherein a parasitic capacitance preventing groove for preventing parasitic capacitance is formed on a side of the current constriction portion. 5. The substrate is set to a first conductivity type, a tuning layer is provided between the substrate and the second semiconductor layer in the ridge waveguide, and a third layer is provided on a lower surface of the substrate. An electrode is formed, claim 1,
The semiconductor device according to claim 2, claim 3, or claim 4. 6. The semiconductor device according to claim 1, claim 2, claim 3, or claim 4, wherein the second semiconductor layer and the third semiconductor layer are continuously formed using the same material. 7. The second semiconductor layer and the third semiconductor layer are continuous in at least one of a front end portion and a rear end portion, and at least an intermediate portion sandwiched between the front end portion and the rear end portion is formed. The semiconductor device according to claim 2, wherein the current constriction portion is formed between the second semiconductor layer and the third semiconductor layer. 8. The second semiconductor layer and the third semiconductor layer are continuous at at least one of a front end portion and a rear end portion, and at least an intermediate portion sandwiched between the front end portion and the rear end portion. The semiconductor device according to claim 3, wherein the parasitic capacitance prevention groove is formed between the second semiconductor layer and the third semiconductor layer. 9. The semiconductor device according to claim 5, wherein the parasitic capacitance prevention groove is formed deeper than bottom surfaces of the tuning layer and the third semiconductor layer. 10. The semiconductor device according to claim 5, wherein the parasitic capacitance prevention groove is formed to a depth reaching the substrate. 11. A semiconductor device as a wavelength tunable laser, comprising a front end portion, a rear end portion and an intermediate portion, the intermediate portion being formed on a part of an upper surface of a substrate and having an active layer in an intermediate layer region. A ridge waveguide, and a first layer formed on the active layer in the ridge waveguide
A first semiconductor layer of conductivity type, a second semiconductor layer of a second conductivity type formed below the active layer in the ridge waveguide, and adjacent to the side of the ridge waveguide. A third semiconductor layer of a second conductivity type connected to the second semiconductor layer, a first electrode formed on the upper side of the first semiconductor layer, and an upper side of the third semiconductor layer on the upper side of the third semiconductor layer. A second electrode to be formed, a current constriction portion having a thyristor structure is provided in a part between the first semiconductor layer and the third semiconductor layer, and the current confinement portion is parasitic to a side of the current confinement portion. A parasitic capacitance preventing groove for preventing capacitance is formed, and the second semiconductor layer and the third semiconductor layer are continuous in at least one of the front end portion and the rear end portion, and at least the front end portion and The second semiconductor layer and the third semiconductor layer are formed in an intermediate portion sandwiched by the rear end portions. The semiconductor device wherein the current confinement portion is formed between the semiconductor layer. 12. The leakage current prevention means is composed of a high resistance layer formed on the upper surface of the third semiconductor layer, and an end portion of the high resistance layer in contact with the ridge waveguide is an end of the active layer. The semiconductor device according to claim 1, which is as close to the section as possible. 13. The semiconductor device according to claim 5, wherein a high resistance layer for preventing a leakage current is provided between the substrate and the third semiconductor layer on the lower surface of the third semiconductor layer. 14. A plurality of layers including a tuning layer, a second semiconductor layer of a second conductivity type, an active layer, and a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type. A stacking step of sequentially stacking and forming a third semiconductor layer of the second conductivity type so as to be connected to the second semiconductor layer and exposing it upward, and a plurality of layers stacked in the stacking step, Ridge formation step of selectively removing only a part of the side part of the middle part sandwiched between the front and rear ends to form a ridge waveguide; and embedding for forming a current constriction part on the side of the ridge waveguide. A forming step, a groove forming step of selectively removing an outer portion of the current constriction portion by etching to form a parasitic capacitance preventing groove for reducing a parasitic capacitance, and a first electrode on the upper surface of the first semiconductor layer. A second electrode on the top surface of the third semiconductor layer, Third on the lower surface of the substrate
And a step of forming electrodes for forming the electrodes, respectively. 15. The stacking step includes a continuous formation step of continuously forming the third semiconductor layer using the same material at the same time when the second semiconductor layer is formed, and a step of forming the first semiconductor layer after the continuous formation step. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising an exposure step of exposing the third semiconductor layer by etching away an active layer and a side portion of the first semiconductor layer. 16. A first stacking step of sequentially stacking a plurality of layers including a tuning layer, a second semiconductor layer of a second conductivity type and an active layer on a substrate of a first conductivity type, and the stacking. A ridge forming step of selectively removing the side portions of the plurality of layers laminated in the step by etching to form a ridge waveguide; A buried forming step of forming a buried connection so as to connect to the second semiconductor layer, a high resistance layer forming step of forming a high resistance layer on the upper surface of the third semiconductor layer, and a ridge waveguide and a high resistance layer A second stacking step of forming a first semiconductor layer of the first conductivity type on the upper surface; a first electrode on the upper side of the first semiconductor layer; and a second electrode on the upper surface of the third semiconductor layer. A third electrode is provided on the lower surface of the substrate.
And a step of forming electrodes for forming the electrodes, respectively. 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the high resistance layer forming step, the high resistance layer having a semi-insulating crystal structure is formed by doping impurities on the upper surface of the third semiconductor layer. . 18. The high resistance layer is formed by implanting predetermined ions into the upper surface of the third semiconductor layer after forming the third semiconductor layer in the high resistance layer forming step.
7. The method for manufacturing a semiconductor device according to item 6. 19. The method of manufacturing a semiconductor device according to claim 18, wherein protons are used as the predetermined ions. 20. The method of manufacturing a semiconductor device according to claim 18, wherein boron is used as the predetermined ions.