JPH07226074A - Semiconductor memory device and access method thereof - Google Patents

Abstract

PURPOSE: To obtain a semiconductor memory device and its method capable of accessing to a desired address at high speed. CONSTITUTION: This semiconductor device first inputs N-bit external address signals, generates 2M-bit low decoding signal and row-addresses a memory cell block 200. In addition, the semiconductor device input a high-order N-M bit address signal among the N-bit external address signals, generates 2<(> N<-> M<)> -bit column decoding signal and simultaneously column-addresses the cell array of a consecutive 2M column in the memory cell block 200. Then at the time of column reading operation, e.g. from row-addressed 2M cells in the 2M column cell array corresponding to the remaining low-order M-bit address signal among the N-bit external address signals, accessed data is multiplexed and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a high speed access method, and more particularly to a semiconductor memory device and a high speed access method capable of high speed operation.

[0002]

2. Description of the Related Art A typical DRAM of a semiconductor memory device
Has a drawback that it requires refreshing and the interface circuit is complicated, but since it can obtain four times the degree of integration as SRAM, it is widely used mainly for systems that require a large amount of memory such as the main memory of a computer system. It is used. As the capacity of the DRAM is increased by increasing the capacity by inputting / outputting data in 1-bit units, a 4-bit unit input / output method block is dually provided and the block input / output is selected. The method (TMS44C257 of TI company) etc. is introduced.

FIG. 1 shows the internal structure of a conventional DRAM. A conventional DRAM includes a column decoder 120 that inputs a 9-bit external address signal A8 to A0 and decodes to access a column address, and a row decoder 110 that inputs an external address signal and decodes to access a row address. The row decoder 110
The memory cell block 1 in which one corresponding cell is accessed in the two-dimensional cell array by the column decoder 120
Has 00.

2A to 2D, the read operation of the conventional DRAM having the above-mentioned structure will be described. External address signals A8 to A0 (FIG. 2A) are input to the row decoder 110 and the column decoder 120, respectively. For example, on the falling edge of the row address strobe signal (FIG. 2B),
The decoded input signals of the external address signals A8 to A0 are input to the row decoder 110 for decoding the input signals to activate the corresponding row (word) line of the memory cell block 100. In addition, at the falling edge of the column address strobe signal (FIG. 2C), the decoded input signal of the external address signals A8 to A0 activates the corresponding column (bit) line of the memory cell block 100. It is input to the column decoder 120 which decodes the signal. Therefore, the cell at the intersection of the activated row line and column line is accessed, and the cell information is sense-amplified and output.

In such a read operation, a row address signal and a column address signal are supplied from the outside every access and the corresponding cell is accessed, so that the row line charge / discharge period (section a in FIG. 2) is in operation. It acts as an invalid period and lengthens the access time. Therefore, when only the column address is sequentially changed in the powering order on the same row line, as shown in FIG. 3, the row address strobe signal / R
A page mode is known in which only the column address strobe signal / CAS is repeatedly activated in the active state of AS to eliminate the charge / discharge time of the row line and accelerate the access time. In particular, the page mode is mainly used when repeatedly accessing consecutive addresses like VRAM.

However, even in the above-mentioned page mode, an invalid period (section b in FIG. 3) is necessary after the column access until the next column access. For example, when sequentially reading data from the adjacent cells at the address (0,0) (0,1) in the first row shown in FIG. 1, (0,
A predetermined waiting section is required when accessing (0) and (0, 1). This is memory cell block 1
This is because the next column address '1' must be charged after waiting until the column charged by the column address '0' is completely discharged at the time of (0,0) access with 00. That is, it is necessary to charge and discharge each column line. For example, assuming that one row has 512 columns, the time T _A for accessing one row data in page mode can be calculated by the following equation.

T _A = 512T _{ROW (set)} + 512T
_{ROW (hold)} + (512-1) T _COL where T _{ROW (set)} is the column address setup time, T _{ROW (hold)} is the column address hold time, T
_COL is the charging / discharging time before the column line. Further, there is a problem that it is difficult to control externally because a new column address signal should be input from the outside every time, even though the addresses are consecutive in the order of multiplication.

Particularly, in a dual port VRAM in which data is transmitted from the CPU through the random port and display data is transmitted through the serial port to the CRT, continuous addresses in the order of multiplication are repeated, so that the high resolution trend of the CRT results in high speed. Ease of access and external control is required.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device and a high speed access method capable of high speed access in order to solve the problems of the conventional techniques.

[0010]

In order to achieve the above object, the apparatus of the present invention comprises a cell array of continuous 2 ^M (where 2 ^M is an integer of a divisor of 2 ^N or more) columns. A column addressing N × N memory cell block and a row decoder for inputting and decoding an N-bit external address signal to generate a 2 ^N- bit row decoding signal for row addressing the memory cell block; Of the N-bit external address signals, a high-order ^NM bit column address signal is input and decoded to generate a 2 ^(NM) -bit column decoding signal to generate continuous 2 of the memory cell blocks.
And a column decoder for column addressing simultaneously cell array of ^M columns, which is a low addressing 2 ^M column cell array, which is the column addressing in response to a column address signal remaining lower M bits of the external address signal of said N-bit A multiplexer that multiplexes data accessed from 2 ^M cells and outputs multiplexed data; and a multiplexer that responds to the remaining lower M-bit column address signal of the N-bit external address signal. And input data latching means for latching external data to be written into 2 ^M row-addressed cells of the column-addressed 2 ^M column cell array.

In the method of the present invention, the cell array of consecutive 2 ^M columns is column-addressed simultaneously.
A method of high-speed access to a semiconductor memory device having × N memory cell blocks, wherein an N-bit external address signal is input and decoded to generate a 2 ^M- bit row decoding signal to perform low addressing of the memory cell block. And a column address signal of the upper ^NM bits of the N-bit external address signal is input and decoded to generate a column decoding signal of 2 ^(NM) bits to generate continuous 2 ^{M of the} memory cell block. Column addressing of the cell arrays of the columns simultaneously, and the column addressing in response to the remaining lower M-bit column address signal of the N-bit external address signals during the read operation are performed.
Outputting the multiplexed data by multiplexing the data accessed from the 2 ^M numbered cells of the ^M column cell array, and the remaining part of the N-bit external address signal during the write operation. characterized in that in response to an address signal of the low-order M bits of comprising a step of sequentially latching the external data to be written to the low the addressed 2 ^M number of cells in the column the addressed 2 ^M column cell array And

[0012]

According to the present invention, in order to write and read sequentially addressed graphic data to the DRAM and designate one column, and sequentially access cells of all columns of the designated column at high speed, for example, 9 bits are used. The column address signal of the upper 7 bits of the column address signal of is specified to specify four consecutive column cell arrays at the same time, and in response to the remaining column address signal of the lower 2 bits, input data when writing Are sequentially supplied to the designated column cell array, and at the time of reading, the data read from the four designated cells are multiplexed and sequentially output. Therefore, the access time at the time of column addressing is about three times faster than the conventional method.

[0013]

Embodiments of the present invention will now be described with reference to the accompanying drawings.
Will be described in detail. FIG. 4 shows the structure of a DRAM according to the present invention.
It is a figure. In FIG. 4, the DRAM has two consecutive ^M(This implementation
4 in the example (where 2^MIs 2 or more 2^N(N = 9)
The cell array of columns is a whole number
Addressed 512 x 512 memory cell block
Of the external address signals A8 to A0 of 9 bits
Of these, external row address signals XA8 to XA0 are input and
512-bit raw decoding signal
Is generated and the low address of the memory cell block 200 is generated.
Singing row decoder 210 and the 9-bit outside
Address of upper 7 bits of copy address signals A8 to A0
Input signal YA8 to YA2 and decodes 128
Generating a bit column decoding signal
Cell array of four consecutive columns of resell block 200
Column decoder 22 for simultaneously column addressing
0 and the 9-bit external address signals A8 to A0
The remaining lower 2 bits of the address signal YA1, YA0
In response, the four columns addressed by the column
From the four low-addressed cells of the cell array
Multiplexed and read the accessed data
The multiplexer 23 which outputs through the output line DR
0 and the 9-bit external address signals A8 to A0
In response to the remaining lower 2 bits of the address signal,
A four column cell array with ram addressing
-Attempting to write to four addressed cells
Input data latching method to latch external data D3 to D0
It includes a stage 240 and an input / output buffer 250.

The input data latch means 240 is shown in FIG.
As shown in FIG. 3, the data input line dW is commonly connected to the data input terminal d, the enable signal input terminals en are supplied with the enable signals E1 to E4, and the output terminals are connected to the data lines DA, DB, DC ,. The enable signal E is obtained by combining the four D-type latches 241 to 244 respectively connected to DD, the lower column address signals YA1 and YA0, and the write control signal / WE.
1 to E4 for generating logic means 245.

The input / output logic of the logic means is as shown in Table 1 below.

[0016]

[Table 1]

The high-speed access method of the semiconductor memory device of the present invention thus constructed is as follows. First,
9-bit external row address signals XA8 to XA0 are input and decoded to generate a 512-bit row decoding signal, and the memory cell block 200 is row-addressed.

Next, of the 9-bit external column address signal, the upper 7-bit address signals XA8 to XA2 are used.
Is input and decoded to generate a 128-bit column decoding signal, and the memory cell block 2
Column arrays of 4 consecutive cell arrays of 00 are simultaneously performed. And during the read operation,
Accessed from four row-addressed cells of the column-addressed 4-column cell array in response to the remaining lower 2-bit column address signals YA1 and YA0 of the 9-bit external address signals A8 to A0. The data is multiplexed and output.

In the write operation, in response to the remaining lower 2-bit column address signals YA1 and YA0 of the 9-bit external address signals A8 to A0, the low-addressing of the four column-addressed column cell arrays is performed. External data D3 to D0 to be written are sequentially latched to the other four cells.

[0020]

According to the present invention, when writing and reading sequentially addressed graphic data to the DRAM, one row is designated, and cells in all columns of the designated row are sequentially accessed at high speed. , A high-order (N−M) -bit column address signal of the N-bit column address signal is decoded to simultaneously specify a 2 ^M column cell array, and in response to the remaining low-order M-bit column address signal, For example, when writing, the input data is sequentially supplied to the designated column cell array, and when reading, the data read from simultaneously designated 2 ^M cells is multiplexed and sequentially read. The access time at the time of column addressing is about 3 times faster than the conventional method.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a conventional DRAM device.

FIG. 2 is a timing diagram showing a normal read operation of a conventional DRAM.

FIG. 3 is a timing diagram showing a page mode operation of a conventional DRAM.

FIG. 4 is a block diagram of a DRAM device according to the present invention.

5 is a detailed circuit diagram of the write controller of FIG.

[Explanation of symbols]

 200 memory cell block 210 row decoder 220 column decoder 230 multiplexer 240 input data latch means 250 input / output buffer A8 to A0 external address signal XA8 to XA0 row address signal YA8 to YA0 address signal

Claims (2)

[Claims] 1. Continuous 2 ^M (where 2 ^M is 2 or more 2
A N × N memory cell block in which a cell array of columns (which is an integer number of ^N ) is simultaneously column-addressed and an N-bit external address signal is input and decoded to generate a 2 ^N- bit row decoding signal. A row decoder for row addressing the memory cell block, and a column address signal of upper NM bits of the N-bit external address signal are input and decoded to obtain 2
A column decoder for generating a ^(NM) -bit column decoding signal to simultaneously perform column addressing on a cell array of consecutive 2 ^M columns of the memory cell block, and a remaining lower M bits of the N-bit external address signal during a read operation. in response to a column address signal of bits, the data accessed from low the addressed 2 ^M number of cells in the column the addressed 2 ^M column cell array and Multiplexing, and outputs the Multiplexing data and a multiplexer, in response to a column address signal remaining lower M bits of the external address signal of the N bits during a write operation, the row the addressed 2 ^M number of cells in the column the addressed 2 ^M column cell array External data to be written A semiconductor memory device having input data latching means for latching. 2. A high-speed access method of a semiconductor memory device having an N × N memory cell block in which a cell array of consecutive 2 ^M columns is simultaneously column-addressed, and an N-bit external address signal is input and decoded to 2 ^M. Generating a bit row decoding signal to perform row addressing of the memory cell block; and inputting and decoding the upper ^NM bit address signal of the N bit external address signals to perform 2 ^(NM)
Generating a bit column decoding signal to simultaneously perform column addressing on a cell array of consecutive 2 ^M columns of the memory cell block, and a remaining lower M bit address of the N bit external address signal during a column read operation. in response to the signal, and outputting the data accessed from low the addressed 2 ^M number of cells in the column the addressed 2 ^M column cell array Multiplexing to, the N bit during the column write operation stage in response to the remaining lower M bits of the address signal among the external address signals are sequentially latched external data to be written to the low the addressed 2 ^M number of cells in the column the addressed 2 ^M column cell array And high-speed operation of the semiconductor memory device including Scan method.