JPH07226033A - Optical disc player - Google Patents

Abstract

PURPOSE:To detect the data with a lower error rate by obtaining phase error from amplitude value of data change point of a regeneration signal by a maxi mum likelihood decoding result of clocks with plural phases, selecting the opti mum phase clock and constituting a waveform equalization circuit and a signal detection circuit so as to be suitable to digitization. CONSTITUTION:An oscillation frequency of a crystal oscillator 11 is counted by a counter circuit 12, and a count value is inputted to a selector 14 through a delay circuit 13, and the optimum phase clock is outputted to the circuits 15-17. The regeneration signal from an optical disk whose amplitude is shifted by a latch shift circuit 17 through an A/D conversion circuit 15 and the equalization circuit 16. A Viterbi decoding circuit 21 outputs the maximum likelihood decoding data by a difference between a sample value by a selected clock value and a predicted sample value corresponding to a possible combination with adjacent bit to a zero cross detection circuit 22. A phase detection circuit 18 outputs the phase error of the amplitude value of the signal. A control circuit 20 latches a phase selection signal by a zero cross detection signal from the circuit 22. The output is outputted as the regenerative signal through an SP conversion circuit 23, an EFM demodulation circuit 24 and a latch circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk reproducing apparatus, and in particular, applies a partial response method and maximum likelihood decoding in order to realize high density recording in a self clock modulation method for extracting a bit clock from a reproduction signal. The present invention relates to an optical disk data reproducing device for detecting a signal.

[0002]

2. Description of the Related Art Improving recording density is a major issue for recording and reproducing digital moving images on an optical disk.
As means for overcoming this problem, application of waveform equalization by the partial response method or maximum likelihood decoding by the Viterbi algorithm is considered in the signal processing unit.
For example, "Recent Development of Signal Processing Technology for Magnetic Disks", IEEJ Transactions, Vol.J75-C-II, No.11 is a data reproduction method applying partial response method or Viterbi decoding to the data reproduction from the optical disk medium. , pp. 611-623, (1992-11)) and JP-A-63-185228.

In the so-called digital video disc modulation system for recording and reproducing digital moving images, edge recording using the DC-free code, which is the same as EFM modulation of CD, is expected in terms of recording density and ease of signal processing. The operation of the reproduction circuit and the data detection circuit is C
A signal processing circuit of D will be briefly described with reference to the drawings.

FIG. 9 is a block diagram of a clock recovery and data detection circuit for a CD according to the prior art. FIG. 10 is a data detection timing chart. In FIG. 9, 1 is a reproduction signal input, 2 is a waveform equalization circuit, 3 is a data slice circuit, 4 is a slice level control circuit, 5 is a synchronous clock reproduction circuit, 6 is a latch circuit, 7 is an EFM demodulation circuit, and 8 is reproduction. It is a data output.

In FIG. 9, a reproduction signal 1 from the optical disk
Is subjected to waveform equalization in the waveform equalization circuit 2 including an analog circuit in order to remove intersymbol interference. The waveform-equalized reproduced signal is converted into a binarized signal by the slice level in the data slice circuit 3 as shown in FIG. Since the slice level of the EFM modulation is DC-free, this slice level is binarized by utilizing the fact that the slice level of the reproduction signal with the direct current cut off becomes zero level, but due to the distortion caused by the asymmetry of the pits. It may fluctuate. The slice level control circuit 4 is a circuit that automatically controls this slice level fluctuation to an accurate value. The slice-detected binarized signal is input to the synchronous clock regeneration circuit 5, and the PLL regenerates the clock signal synchronized with the edge of the binarized signal. The latch circuit 6 latches the binarized signal at the reproduced clock timing, and the EFM demodulation circuit 7
EFM demodulates the latched binarized signal and reproduces the data sequence 8
To get

[0006]

This clock recovery and data detection circuit uses a PL based on the edge timing obtained by binarizing the analog reproduced signal at the slice level.
Since the clock is reproduced by L, the waveform equalization circuit and the data detection circuit are not suitable for digitization in which signal processing is performed with the clock as a reference. Especially when it is desired to apply Viterbi decoding to signal detection in order to cope with high density recording, the clock is regenerated after slice detection, and therefore, in addition to binarization by slice detection, Viterbi decoding is performed based on the clock after slice detection. Since data detection is performed by decoding, the effect of reducing the error rate by Viterbi decoding cannot be expected so much.

An object of the present invention is to solve the above-mentioned problems of the prior art and also in a recording format of a self-clock modulation system for generating a clock from a reproduction signal.
Provided is an optical disc reproducing apparatus which has a configuration suitable for digitization of a waveform equalizing circuit and a signal detecting circuit, and applies Viterbi decoding to detect data effective in reducing an error rate in order to support high density recording. To do.

[0008]

In order to achieve the above object, according to the present invention, a phase difference clock generating means for generating a plurality of channel bit clocks having discretely different phase differences, and a plurality of clocks having different phase differences. A clock phase selection unit that selects a phase that becomes a more optimum sample clock, and a difference value between each of the sampled values of the reproduction signal by the selected clock and the plurality of predicted amplitude values corresponding to the combination of adjacent bits in the optimum phase. A maximum likelihood decoding means for selecting the decoding path with the highest likelihood and decoding the data;
Phase error detection means for detecting a phase error with the optimum phase from the amplitude value of the sample clock selected at the data change point of the maximum likelihood decoding result, and control of the selection of the clock phase so that the detected phase error is minimized. Clock phase selection control means is provided.

[0009]

In the present invention, the phase difference clock generating means delays the channel bit clock obtained by dividing the free-run original oscillation clock and outputs a plurality of clocks having different phase differences. The clock phase selection means selects the clock signal of the optimum phase from the clocks of the plurality of phases by the clock phase selection control. The maximum likelihood decoding means outputs the most probable decoding result according to the Viterbi algorithm based on the difference between the sample value and the predicted amplitude value at the selected clock phase. The phase error detection means calculates a phase error from the optimum phase from the amplitude value of the data change point based on the maximum likelihood decoding result sampled by the selected clock. The clock phase selection control means selects the clock phase corresponding to the phase error. As a result, the circuit configuration can be digitized, and the data error rate can be reduced by the data detection by the maximum likelihood decoding.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an embodiment of a data detection circuit of an optical disk reproducing apparatus according to the present invention, and FIG. 2 is a timing chart showing an operation of PLL clock reproduction due to a phase error. FIG. 3 is a block diagram showing the details of the waveform equalization circuit 16.

In FIG. 1, reference numeral 11 is a crystal oscillator, which oscillates at a frequency that is an integral multiple of the channel bit clock frequency. A counting circuit 12 counts the output from the crystal oscillator 11 and outputs a channel bit clock.
Reference numeral 13 denotes a delay circuit, which outputs a channel bit clock obtained by delaying the channel bit clock by 8 phases at regular intervals within one clock cycle. 14 is a selector circuit, 8
From the phase channel bit clock, a phase channel bit clock corresponding to a phase control signal described later is selected. Reference numeral 15 is an A / D conversion circuit, which converts a reproduction signal into a digital value at the phase timing of a clock selected from eight phases. Reference numeral 16 is a waveform equalization circuit, which performs waveform equalization of partial response class I characteristics. Reference numeral 17 is a latch shift circuit, which shifts the amplitude value after waveform equalization in channel bit units. Reference numeral 18 denotes a phase error detection circuit, which outputs a phase error from the optimum clock phase. Reference numeral 19 is a clock phase selection control circuit, which selects and controls the optimum phase from the phase error. A latch circuit 20 latches the phase selection information. Reference numeral 21 denotes a Viterbi decoding circuit, which outputs decoded data most likely from the difference between the amplitude value after waveform equalization and a plurality of predicted amplitude values composed of bit combinations that cause waveform interference, as will be described later. Reference numeral 22 is a zero-cross detection circuit, which detects a data change point from the Viterbi decoding result. A serial-parallel conversion circuit 23 converts serial Viterbi decoded data into a parallel data string of 1 byte and 17 channel bits. Reference numeral 24 is an EFM modulation circuit, which performs EFM demodulation of a parallel data string of 1 channel and 17 channel bits. A latch circuit 25 latches the EFM demodulated data to obtain reproduced data.

Further, in FIG. 3, reference numerals 31, 32 and 33 denote delay circuits which delay in units of 3 channel bits which is the minimum mark length. 34, 35 and 36 are multiplication circuits, and C0 and C1 are multiplication coefficients. 37 is an adder circuit.

In FIG. 1, a crystal oscillator 11 oscillates at a frequency that is an integral multiple of the channel bit clock, and a counter circuit
Divide by 12 to obtain the channel bit clock.
The delay circuit 13 outputs a phase-delayed clock at equal intervals divided into eight phases from the divided channel bit clock. Selector circuit 14 outputs 1 from this 8-phase clock
A clock of one phase is selected, and this clock becomes the digital signal processing operation clock of the following data detection circuit.

The reproduced signal from the optical disk is an A / D conversion circuit 1
It is sampled at the phase timing of the clock selected in 5 and converted from an analog value to a digital value. As shown in FIG. 3, the waveform equalization circuit 16 is composed of a 3-tap transversal filter, and the coefficients of C0 and C1 of the multiplication circuits 34 to 36 are set so as to have the characteristics of the partial response class I. The latch shift circuit 17 shifts the digital amplitude value of the reproduced signal after waveform equalization for each channel bit clock. Further, the Viterbi decoding circuit 21 delays and outputs the most probable decoded data from the combination of intersymbol interference in the channel bit period based on the amplitude value after waveform equalization until the decoding path is determined. The operation of the Viterbi decoding circuit 21 will be described in detail later. The number of delay stages of this Viterbi decoding matches the number of delay stages of the latch shift circuit 17, and the phase error detection circuit 18 determines the phase error from the difference between the amplitude value latched at the final stage and the intermediate amplitude value of the amplitude value at the preceding stage. Is output. The clock phase selection control circuit 19 outputs a phase selection signal to select the optimum phase from the phase error, and the latch circuit
20 latches the phase selection signal by the zero-cross detection signal from the zero-cross detection circuit 22.

FIG. 2 shows a digital PL by holding a phase error.
It is a timing diagram by L. In FIG. 2, .phi.0 to .phi.7 are 8-phase channel bit clocks having different phases at equal intervals, and it is assumed that .phi.3, which is out of phase by .phi. From the phase .phi.0, is selected by the selector circuit. The amplitude value of the final stage of the latch shift circuit 17 is A _n , 1 from the final stage
When the amplitude value before the stage is A _n-1 and the intermediate value of the reproduced signal is x, the output of the phase error circuit 18 is τ '= α (| A _n -X |-| A _n-1 -X |) And the phase p becomes

P = τ + α (| A _n -X |-| A _n-1 -X |) where α
Is a coefficient.

Assuming that the channel bit period is T, the clock phase selection control circuit 19 determines that the phase error τ'is ± T / 8.
Channel bit clock is select circuit if above
Control to select the channel bit clock of another phase by 14. Details of the clock phase selection control circuit 19 will be described later.

The zero-cross detection circuit 22 is a Viterbi decoding circuit 21.
Whether the output of the clock changes from "0" to "1" or from "1" to "0", the change is detected to be a zero cross, and the phase selection signal output of the clock phase selection control circuit 19 is latched. Works like a latch at 20. In addition, this output is directly input to the serial-parallel conversion circuit 23,
One byte is converted into parallel data in units of 17 channel bits. This parallel data is EFM-demodulated by the EFM demodulation circuit 24, and the demodulated data is latched by the latch circuit 25 at a 1-byte cycle and output as reproduction data.

FIG. 4 is a block diagram showing an outline of the Viterbi decoding circuit 21. In FIG. 4, 40 is a sample value comparison circuit that compares the amplitude value of the reproduced signal with a plurality of predicted sample values that are combinations of adjacent bits, 41 is a likelihood comparison circuit that calculates a metric for Viterbi decoding, and 42 is a decoding path based on the metric calculation. A decoding path determination circuit for determining whether or not a polarity data delay circuit 43 delays the comparison polarity data of the amplitude value of the reproduction signal and a plurality of predicted sample values, and 44 a polarity for selecting the polarity data corresponding to the result of the decoding pass. A data selection circuit, 45 is a predictive sample value control circuit that adaptively controls a predictive sample value set as an initial value from 48, 46 is a reproduction signal input, and 47 is a decoding output. FIG. 5 shows an isolated reproduction waveform of 1 channel bit of the reproduction signal. This isolated pattern is a pattern which does not actually exist due to the limitation that the mark length of EFM modulation is from 3 channel bits to 11 channel bits. It is a unit pattern for overlapping by combining bits. Further, FIG. 6 is a diagram showing predicted sample values of Viterbi decoding, and FIG. 7 is a state transition diagram and trellis diagram of Viterbi decoding, which are also shown in S3 and S4.
10 "and" 101 "are nonexistent patterns, and the predicted sample value and state transition are deleted.

In FIG. 4, six kinds of predicted sample values of the reproduced signal corresponding to the combination of adjacent three bits are inputted to 48 except S3 and S4 as shown in FIG. The sample value comparison circuit 40 compares the reproduced signal amplitude input from 46 with these six types of predicted sample values, and calculates the difference value between them.
Outputs E111 to E000 excluding E010 and E101 and comparison polarities Sgn7 to Sgn0 excluding Sgn3 and Sgn4. The likelihood comparison circuit 41 calculates difference values E010 and E101 between the reproduced signal amplitude and the predicted sample value.
The metric is calculated from E111 to E000 excluding, and the likelihood comparison result is output. Decoding path determination circuit 42, from the likelihood comparison result,
The decoding path with the highest probability is selected from the state transitions shown in FIG. 7, and the decoded data is output while waiting for the path to be established while holding the path candidates up to the previous stage. In FIG. 7, the solid line indicates the state transition of bit "1", and the broken line indicates bit "0".
Except for the state transitions that do not exist due to the limitation of Tmin of the EFM modulation, the combinations that the decoding path can take are less than all the bit combinations. The polarity data delay circuit 43 delays the comparison polarities Sgn7 to Sgn0 excluding Sgn3 and Sgn4 of the reproduced signal amplitude and the six types of predicted sample values according to the delay amount until the decoding path is determined,
The polarity data selection circuit 44 selects the comparison polarity data Sgn corresponding to the decoding path from the delayed comparison polarity. The predictive sample value control circuit 45 varies the predictive sample value corresponding to the bit combination from the decoded data string of adjacent 3 bits and the selected comparison polarity data according to the comparison polarity by a specific value. That is, the processing indicated by Tn _i = T (n-1) _i + αSgnT (nm) _i is performed. Where T is the predicted sample value, n
Is a control sample point, m is the number of Viterbi decoding delay bits, and i is the Viterbi state. This process adaptively controls the predicted sample value according to the fluctuation of the reproduced signal, and this operation enables data decoding without increasing the error due to Viterbi decoding even with respect to the level fluctuation of the reproduced signal and nonlinear distortion. It will be possible.

FIG. 8 is a schematic diagram of a clock phase selection control circuit. In FIG. 8, 81 is a reference phase difference setting circuit,
Reference numeral 82 is a phase difference comparison circuit, 83 is a continuous counting circuit, 84 is a selection signal increasing / decreasing circuit, and 20 is the latch circuit shown in FIG. Reference numeral 86 is a phase error signal, and 87 is a phase selection signal. In FIG. 8, when the phase error input from 86 exceeds the reference phase of 81, the phase difference comparison circuit 82 outputs the comparison result, and the continuous count circuit 83 counts the number of consecutive times the phase error exceeds the reference phase. When it reaches a certain value, the selection signal increasing / decreasing circuit 84 increases or decreases the current phase selection signal. The latch circuit 20 latches this output for each zero-cross detection, and uses this output as a phase selection signal.

As a result, at the zero-cross point of the Viterbi decoding result, the phase error is detected from the amplitude value of the reproduction signal corresponding to the decoding result, and the phase error is 1/8 of the reference clock.
When the cycle is continuously exceeded by a certain value, the phase selection signal is increased or decreased to perform selection control so as to select the clock of the adjacent phase that is currently selected. The clock recovery and data detection circuit Can be digitized, and maximum likelihood decoding can be applied.

According to the present embodiment described above, the configuration is such that the optimum phase clock is selected by detecting the phase error at the zero cross point of the channel bit clock of eight phases by the Viterbi decoding result. Even in the recording format, clock recovery and data detection can all be configured by digital circuits, and since Viterbi decoding, which is maximum likelihood decoding, can be applied to data detection, the error rate in data detection can be reduced and high density recording can be supported. effective. In the embodiment of the present invention, one is selected from eight-phase clocks, but this number is not specified. Further, the modulation method is not limited to EFM, but can be applied to other self-clock modulation methods that are not DC-free.

[0025]

According to the present invention, the optimum phase clock is selected by obtaining the phase error from the amplitude value of the data change point of the reproduction signal based on the maximum likelihood decoding result for the clocks of a plurality of phases.
Even in the format of the modulation method of the self-clock method, clock recovery and data detection can be configured by digital circuits, and data detection errors can be reduced by maximum likelihood decoding, and high density optical discs can be supported.

[Brief description of drawings]

FIG. 1 is a clock recovery and data detection circuit diagram according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of clock reproduction which is an embodiment according to the present invention.

FIG. 3 is a diagram showing details of a waveform equalizing circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing an outline of a Viterbi decoding circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of an isolated reproduction waveform.

FIG. 6 is a diagram illustrating an example of predicted sample values for Viterbi decoding.

FIG. 7 is a diagram showing an example of a Viterbi decoding state transition diagram and a trellis diagram.

FIG. 8 is a diagram showing an outline of a clock selection control circuit.

FIG. 9 is a diagram showing a data detection circuit in a CD.

FIG. 10 is a diagram showing a data detection timing in a CD.

[Explanation of symbols]

11 ... Crystal oscillator, 12 ... Counter circuit, 13 ... Delay circuit, 14
... selector circuit, 15 ... A / D conversion circuit, 16 ... waveform equalization circuit, 17 ... latch shift circuit, 18 ... phase error detection circuit, 19
... Phase selection control circuit, 20 ... Latch circuit, 21 ... Viterbi decoding circuit, 22 ... Zero cross detection circuit, 23 ... Serial-parallel conversion circuit, 24 ... EFM modulation circuit, 25 ... Latch circuit.

Claims (1)

[Claims] 1. A phase difference clock for generating a plurality of channel bit clocks having discretely different phase differences in an optical disk reproducing apparatus for extracting a bit clock from a reproduced signal and reading data in synchronization with the bit clock. Generating means, clock phase selecting means for selecting a phase that becomes an optimum sample clock from the plurality of clocks having different phase differences, and a reproduction signal sampled at the selected clock phase, and possible combinations of the sample value and adjacent bits Maximum likelihood decoding means for selecting the decoding path having the highest likelihood from the relationship with a plurality of predicted sample values corresponding to the above and data decoding, and the reproduced signal amplitude of the bit change point corresponding to the decoding result by the maximum likelihood decoding means. A phase error detecting means for detecting a phase error with a more optimum clock phase, and an optimal clock phase selecting means for the phase error detecting means based on the phase error. Optical disk reproducing apparatus characterized in that a clock phase selection control means for selecting the sample clock phase.