JPH0722346A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor device of a structure, where in a coverage ratio of a metal wiring in contact holes is improved. CONSTITUTION:A semiconductor device is constituted of a semiconductor substrate 1, an interlayer oxide film 4 provided on this substrate 1, contact holes 5 which penetrate this film 4 and are bored on the substrate 1, sidewalls 20, which are provided in these holes 5 and have the same conductivity type as that of diffused layers 2a and 2b to be brought into contact in the substrate 1, and a metal wiring 6A connected with the layers 2a and 2b via the holes 5, in which these sidewalls 20 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a DRAM and a method of manufacturing the same, and more particularly to a semiconductor device having an improved coverage of metal wiring in a contact hole having a large aspect ratio and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Recent semiconductor devices typified by, for example, DRAMs have been miniaturized, and accordingly, contact holes (connection holes) for connection between electrode wirings or between electrode wirings and a substrate. Or via holes) also tend to shrink. However, the size of the semiconductor device in the vertical direction has hardly been reduced for reasons such as ensuring the capacitance of the capacitor. Therefore, the aspect ratio of the above-mentioned contact hole (ratio of depth to contact hole diameter) is increasing.

FIG. 7 shows a conventional semiconductor device such as an MO.
It is sectional drawing which shows an example of the structure of SFET. In the figure, reference numeral 1 is a semiconductor substrate made of, for example, P-type silicon single crystal, 2a and 2b are, for example, N-type diffusion layers formed on the semiconductor substrate 1, and diffusion layers 2a and 2b are respectively for transistors described later. It becomes a source region and a drain region. Reference numeral 2c is a gate oxide film formed on the semiconductor substrate 1, and 2d is a gate electrode made of polysilicon or the like. The transistor 2 is constituted by the source region 2a, the drain region 2b, the gate oxide film 2c and the gate electrode 2d.

Reference numeral 3 is a field oxide film formed on the semiconductor substrate 1 for isolating the transistors 2 from each other, and 4 is an interlayer oxide formed on the transistor 2 and made of, for example, BPSG (silicate glass containing boron and phosphorus). The films 5 are formed through the interlayer oxide film 4 and are contact holes for electrically connecting the source region 2a and the drain region 2b to a metal wiring described later, and 6 is the transistor 2 via the contact hole 5. Metal wiring 7 for electrically connecting is a protective film made of, for example, a silicon nitride film or a silicon oxide film.

In recent devices, the metal wiring 6
Is composed of, for example, an aluminum alloy film 6a containing copper or silicon, and a barrier metal layer 6b made of, for example, titanium nitride (TiN) for preventing the aluminum alloy film 6a from reacting with the underlying semiconductor substrate 1. . By making the metal wiring 6 multi-layered in this way, wiring with higher reliability is realized.

Now, when the device is further downsized, the aspect ratio of the contact hole 5 becomes larger. Normally, the metal wiring 6 is formed by the sputtering method, which has the best track record in terms of reliability. However, due to the film forming principle of the sputtering method, the step coverage or the coverage rate (the film at the flat portion of the metal wiring) in the contact hole 5 is formed. The ratio of the thinnest film thickness in the contact hole 5 to the thickness) is extremely low. In particular, in the case of a contact hole having a high aspect ratio, it is not uncommon for the aluminum alloy film 6a to be broken as shown by the broken line 8 in the figure.

By the way, with the recent reduction in the size of the device, the aspect ratio of the contact hole is increased, the coverage ratio of the metal wiring is lowered, and it has been described above that the reliability of the device becomes a serious problem. One solution is to perform high-temperature heat treatment (hereinafter referred to as "aluminum reflow method") after forming an aluminum-based alloy film by a sputtering method in vacuum, or simultaneously form an aluminum-based alloy film by a sputtering method while heating at a high temperature (hereinafter , High temperature aluminum sputtering method) to improve the coverage ratio of the metal wiring in the contact hole.

FIG. 8 is a sectional view showing an example of the structure of, for example, a MOSFET as a conventional semiconductor device using the aluminum reflow method. In the figure, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure,
Reference numeral 9 is a metal wiring using the aluminum reflow method. The metal wiring 9 is, for example, a reflowed (high temperature heat treated) aluminum alloy film 9a, a barrier metal layer made of titanium nitride or the like and a wet layer made of titanium (Ti). And a barrier metal film 9b having a double structure. Reference numeral 10 is a so-called void (void) generated in the contact hole 5 filled with the aluminum alloy film 9a.

In this case, unlike the barrier metal layer formed by the usual sputtering method, the semiconductor substrate 1 and the aluminum alloy film 9a are formed.
In addition to the barrier metal layer for preventing the reaction with, a wet layer made of titanium for improving the wettability of the aluminum-based alloy film 9a is required to be about 50 to 300 Å. This allows
Although the contact holes 5 in which the good aluminum-based alloy film 9a is embedded are obtained, some of the contact holes 5 have large voids 10 as shown in the figure,
The reliability is significantly deteriorated.

The reason why the void 10 is generated will be described with reference to FIG. Normally, the interlayer oxide film 4 is BPSG.
Or TEOS (tetraethyl orthosilicate) as a raw material is formed by the CVD method (chemical vapor deposition method). This interlayer oxide film 4 is a film which has a good so-called step coverage but is not a perfect silicon oxide film (SiO ₂ ).
It contains many defects and free oxygen (O ₂ ). In the process of the aluminum flow method, in order to improve the wettability at the interface between the aluminum alloy film and the base, an aluminum alloy film such as titanium and a metal having good wettability are laid and used as a wet layer.

However, during the application of the aluminum reflow method or the high temperature aluminum sputtering method, the semiconductor substrate 1 is 480
Since the temperature is as high as ℃ to 580 ℃, oxygen 11 diffuses into the contact hole 5 from the interlayer oxide film 4. The oxygen 11 reacts with the wet layer of the barrier metal film 9b, and the barrier metal film 9b substantially changes into the metal oxide film 12. The wettability between the metal oxide film 12 and the aluminum alloy film 9a is extremely poor, and as a result, the aluminum alloy film 9a is not embedded in the contact hole 5 and a void 10 is generated.

[0012]

Since the conventional semiconductor device is constructed as described above, the coverage ratio in the contact hole of the metal wiring is very poor and the reliability is poor, and in order to improve this coverage ratio. Even if the aluminum reflow method etc. is used, a large void is generated in an arbitrary contact hole, and there is a problem that the reliability of the semiconductor device is remarkably deteriorated due to disconnection of metal wiring.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a highly reliable semiconductor device having an improved coverage of metal wiring in a contact hole and a manufacturing method thereof. .

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device, a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, and the interlayer insulating film penetrating the semiconductor substrate. Through the contact hole formed in the contact hole, the side wall of the same conductivity type as the diffusion layer to be contacted in the semiconductor substrate, and the contact hole in which the side wall is formed. The metal wiring connected to the diffusion layer is provided.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises: forming an interlayer insulating film on a semiconductor substrate; forming a contact hole reaching the semiconductor substrate in the interlayer insulating film; A step of forming a polysilicon film on the contact hole, a step of etching back the polysilicon film to form a sidewall in the contact hole, and a diffusion layer to be in contact with the semiconductor substrate on the sidewall. It includes a step of introducing impurities of the same conductivity type and a step of forming a barrier metal layer and a metal layer in at least the contact hole in which the sidewall is formed.

In a method of manufacturing a semiconductor device according to a third aspect of the present invention, at least a step of forming an interlayer insulating film on the semiconductor substrate, a step of forming a contact hole reaching the semiconductor substrate in the interlayer insulating film, A step of forming a polysilicon film on the contact hole, a step of etching back the polysilicon film to form a sidewall in the contact hole, and a diffusion layer to be in contact with the semiconductor substrate on the sidewall. A step of introducing impurities of the same conductivity type, a step of forming a barrier metal layer and a wet layer at least in the contact hole where the sidewall is formed, and a step of forming a metal layer on the wet layer in a vacuum state And a step of performing high temperature heat treatment.

[0017]

According to the present invention, since the sidewall of the same conductivity type as the diffusion layer to be contacted in the semiconductor substrate exists in the contact hole, the shape of the contact hole is substantially the shape of the sidewall. Since the shape of the metal wiring is such that the material of the metal wiring is easily embedded, for example, the forward tapered shape, the coverage of the metal wiring in the contact hole is improved.

According to the second aspect of the invention, a polysilicon film is formed on the contact hole, the polysilicon film is etched back to form a sidewall in the contact hole, and the semiconductor substrate is formed on the sidewall. An impurity of the same conductivity type as that of the diffusion layer to be contacted is introduced to make it conductive, and thereafter, a metal wiring including a barrier metal layer and a metal layer is formed in the contact hole. As a result, the shape of the contact hole is substantially a predetermined shape defined by the shape of the sidewall, for example, a forward taper shape, so that the barrier metal layer and the metal layer forming the metal wiring can be easily and surely filled, and the contact The coverage of the metal wiring in the hole is improved.

Further, in the third aspect of the present invention, a polysilicon film is formed on the contact hole, the polysilicon film is etched back to form a sidewall in the contact hole, and the semiconductor substrate is formed on the sidewall. The impurity of the same conductivity type as that of the diffusion layer to be contacted is introduced to make it conductive, and then a barrier metal layer and a wet layer are formed in the contact hole, and then a metal layer is formed on the wet layer in a vacuum state. Heat treatment at high temperature. As a result, the shape of the contact hole substantially becomes a predetermined shape defined by the shape of the sidewall, for example, a forward taper shape, and since the metal layer is heat-treated at a high temperature, the wet layer is not oxidized and the inside of the contact hole of the metal layer is not oxidized. Since the wettability of the metal wiring is ensured, the barrier metal layer and the metal layer forming the metal wiring can be embedded easily and reliably with good reproducibility, and the coverage rate of the metal wiring in the contact hole is further improved. .

[0020]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings by taking a semiconductor device such as a MOSFET as an example. FIG. 1 shows a MOSFE according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the structure of T, and the portions corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 6A indicates the transistor 2 through the contact hole 5.
In the metal wiring 6A, the aluminum-based alloy film 6c as a metal layer containing, for example, copper or silicon, and the aluminum alloy film 6c react with the underlying semiconductor substrate 1. To prevent this, the barrier metal layer 6d is made of, for example, titanium nitride (TiN). By thus forming the metal wiring 6A in multiple layers, wiring with higher reliability is realized.

Reference numeral 20 is a sidewall formed in the contact hole 5 and made of, for example, polysilicon.
The sidewall 20 has the same conductivity type as the source region 2a and the drain region 2b. Due to the presence of the side wall 20, the shape of the contact hole 5 becomes substantially a forward taper shape, and the barrier metal layer 6d is formed by PVD method (physical vapor deposition method), for example, sputtering method.
And the coverage rate of the aluminum-based alloy film 6c becomes good.

2 and 3 are cross-sectional views showing a manufacturing process of a MOSFET according to an embodiment of the present invention, and the manufacturing method will be described in order with reference to FIGS. 2 and 3. First, in FIG. 2A, an interlayer insulating film, for example, an interlayer oxide film 4 is formed on a semiconductor substrate 1 of the first conductivity type, for example, P type, and then a part of the interlayer oxide film 4 is opened to form a semiconductor substrate. A contact hole 5 reaching the main surface 1 is formed. Then, impurities of the second conductivity type, for example N type, are introduced through this contact hole 5 to form a diffusion layer 21 to be the source region 2a or drain region 2b of the transistor 2 on the main surface of the semiconductor substrate 1.

Next, as shown in FIG. 2B, polysilicon is deposited on the interlayer oxide film 4 including the contact holes 5 by, for example, the low pressure CVD method and etched back to form a polysilicon film 22. The polysilicon film 22 formed by the low pressure CVD method has a very good coverage ratio and is formed almost uniformly. The thickness of the polysilicon film 22 is preferably about 1/3 of the outer diameter of the contact hole 5.

Next, referring to FIG. 2C, for example, CCl
Reactive ion etching (RIE) is performed on the polysilicon film 22 by using reactive ions 23 obtained by ionization from a reactive gas such as a gas such as ₄ , Cl ₂ or SiCl ₄ or a mixed gas thereof. . At this time, the reactive ions 23 have a strong anisotropy, and finally, in the flat portion, the polysilicon film 22 is formed.
Is etched, and the side wall of the contact hole 5 is thin at the top as shown in the figure and becomes thicker toward the bottom.
2 remains. Therefore, the shape of the contact hole 5 is a forward taper shape which is convenient when a metal wiring is formed in a later step.

Next, in FIG. 2D, since the polysilicon film 22 is not made conductive at the stage of FIG. 2C, an impurity such as arsenic (As) having the same conductivity type as the underlying diffusion layer 21 is formed. ) 24 is introduced from above, and a sintering process (not shown) is conducted to render the contact hole 5 conductive.
Sidewalls 20 are formed on the side portions of the. Note that this step is a so-called SAC that is usually performed in a MOS device.
It is also possible to combine the use of (self-aligned contact).

Next, in FIG. 3A, a barrier metal film 6d made of titanium nitride or the like is formed, for example, in order to prevent the aluminum alloy film 6c formed in a later step and the underlying semiconductor substrate 1 from reacting with each other. It is formed on the exposed portion of the main surface of semiconductor substrate 1 in contact hole 5, sidewall 20, and interlayer oxide film 4 by a sputtering method or the like. At this time, due to the existence of the conductive sidewall 20,
The thickness of the barrier metal layer 6d formed by the sputtering method is 500.
Approximately 1500 Å, which is almost uniform, and the coverage ratio is extremely good.

Next, in FIG. 3B, an aluminum alloy film 6c is formed on the barrier metal layer 6d by, for example, a sputtering method. This aluminum-based alloy film 6c also has a good coverage ratio like the barrier metal layer 6d. Also,
The contact resistance between the metal wiring 6A made of the aluminum-based alloy film 6c and the barrier metal layer 6d and the diffusion layer 21 in the semiconductor substrate 1 is not only the contact between the metal wiring 6A and the semiconductor substrate 1 but also the conductivity made of polysilicon. Since the contact is made also in the converted sidewall 20,
As a result, low resistance is realized. Finally, in FIG. 3C, a protective film 10 made of, for example, a silicon nitride film or a silicon oxide film is formed on the aluminum-based alloy film 6a of the metal wiring 6A by, for example, a plasma CVD method.

As described above, in this embodiment, since the sidewall 20 is formed in the contact hole 5, the shape of the contact hole 5 becomes a stable forward taper shape, and the metal wiring 6A embedded in the contact hole 5 is formed. As a result, the coverage rate of the contact hole 5 is high and favorable, and the metal wiring or the like is not broken, so that a highly reliable MOSFET can be obtained.

Example 2. FIG. 4 is a sectional view showing the structure of a MOSFET according to another embodiment of the present invention. The parts corresponding to those in FIG. 1 are designated by the same reference numerals and the detailed description thereof will be omitted. In the figure, 9A is a metal wiring using an aluminum reflow method, and this metal wiring 9A is, for example, 48 in a vacuum.
Aluminum-based alloy film 9 as a metal layer containing, for example, copper or silicon, reflowed at a high temperature of about 0 to 580 ° C. for about 1 to 3 minutes
c and a barrier metal layer made of, for example, titanium nitride for preventing the aluminum alloy film 9c from reacting with the underlying semiconductor substrate 1 and for improving the wettability of the aluminum alloy film 9c in the contact hole 5. And a barrier metal film 9d having a double structure of a wet layer made of titanium.

Thus, also in this embodiment, the contact hole 5 has a substantially forward tapered shape due to the presence of the side wall 20, and the barrier metal film 9d and the aluminum film formed by the PVD method (physical vapor deposition method), for example, the sputtering method. The coverage ratio of the system alloy film 9c becomes good.

5 and 6 are cross-sectional views showing the steps of manufacturing a MOSFET according to another embodiment of the present invention. The manufacturing method will be described in order with reference to FIGS. 5 and 6. First, in FIG. 5A, an interlayer insulating film, for example, an interlayer oxide film 4 is formed on a semiconductor substrate 1 of the first conductivity type, for example, P type, and then a part of the interlayer oxide film 4 is opened to form a semiconductor substrate. A contact hole 5 reaching the main surface 1 is formed. Then, impurities of the second conductivity type, for example N type, are introduced through this contact hole 5 to form a diffusion layer 21 to be the source region 2a or drain region 2b of the transistor 2 on the main surface of the semiconductor substrate 1.

Next, in FIG. 5B, polysilicon is deposited on the interlayer oxide film 4 including the contact holes 5 by, for example, the low pressure CVD method and etched back to form a polysilicon film 22. The polysilicon film 22 formed by the low pressure CVD method has a very good coverage ratio and is formed almost uniformly. The thickness of the polysilicon film 22 is preferably about 1/3 of the outer diameter of the contact hole 5.

Next, referring to FIG. 5C, for example, CCl
Reactive ion etching (RIE) is performed on the polysilicon film 22 by using reactive ions 23 obtained by ionization from a reactive gas such as a gas such as ₄ , Cl ₂ or SiCl ₄ or a mixed gas thereof. . At this time, the reactive ions 23 have a strong anisotropy, and finally, in the flat portion, the polysilicon film 22 is formed.
Is etched, and the side wall of the contact hole 5 is thin at the top as shown in the figure and becomes thicker toward the bottom.
2 remains. Therefore, the shape of the contact hole 5 is a forward taper shape which is convenient when a metal wiring is formed in a later step.

Next, in FIG. 5D, since the polysilicon film 22 is not made conductive at the stage of FIG. 5C, an impurity such as arsenic (As) having the same conductivity type as the underlying diffusion layer 21 is formed. ) 24 is introduced from above, and a sintering process (not shown) is conducted to render the contact hole 5 conductive.
Sidewalls 20 are formed on the side portions of the. Note that this step is a so-called SAC that is usually performed in a MOS device.
It is also possible to combine the use of (self-aligned contact).

Next, in FIG. 6A, the thickness is 500
~ 1500Å barrier metal layer and thickness 50 ~ 30
A barrier metal film 9d made of a wet layer having a thickness of about 0Å is formed on the exposed portion of the main surface of the semiconductor substrate 1 in the contact hole 5, the sidewall 20 and the interlayer oxide film 4 by, eg, sputtering. At this time, due to the presence of the conductive sidewall 20, the thickness of the barrier metal film 9d formed by the sputtering method becomes substantially uniform, and the coverage ratio thereof becomes extremely good.

Next, in FIG. 6 (b), an aluminum alloy film 9c is formed on the barrier metal film 9d at a low temperature (about 50 ° C.) to a predetermined film thickness, and then at a temperature of 480-580 ° C.
Then heat for 1 to 3 minutes. In this process, aluminum alloy film 9c
Has good wettability with the underlying barrier metal film 9d, so that it is completely embedded in the contact hole 5. Although oxygen 11 is degassed from the interlayer oxide film 4, it is trapped by the sidewall 20, and as a result, the silicon oxide film 25 is formed on the portion of the sidewall 20 in contact with the interlayer oxide film 4. Therefore, the wet layer of the barrier metal film 9d is not oxidized, and the wettability of the aluminum alloy film 9c in the contact hole 20 is not hindered. As a result, the aluminum-based alloy film 9c can be embedded in the contact hole 5 with excellent reproducibility. Here, reproducibility means that, for example, when there are 1 million contact holes, all 1 million are filled with an aluminum alloy film.

Finally, in FIG. 6C, the metal wiring 9
A protective film 10 made of, for example, a silicon nitride film or a silicon oxide film is formed on the aluminum-based alloy film 9c of A by plasma C, for example.
It is formed by the VD method or the like.

As described above, in this embodiment, the side wall 20 is formed in the contact hole 5 so that the contact hole 5 has a stable forward taper shape, and is reflowed by the aluminum reflow method. Alloy film 9c
Since the contact hole 5 is embedded in the contact hole 5, the aluminum alloy film 9c can be easily embedded with good reproducibility and fine contact, and thus the coverage of the contact hole 5 by the metal wiring 9A is high. As a result, a finer MOSFET having higher reliability can be obtained because the metal wiring or the like is not broken.

Example 3. In the above embodiments, the case where titanium nitride is used as the barrier metal layer has been described.
For example, titanium tungsten, tungsten silicide, molybdenum silicide, or the like may be used without being limited thereto.

Example 4. Further, a tungsten silicide film, a molybdenum silicide film, or the like may be used instead of the aluminum-based alloy film used in the above embodiment.

Example 5. Further, in the above embodiment, the case where the semiconductor device is a MOSFET has been described.
The present invention is not limited to this, and can be similarly applied to other semiconductor devices, and the same effect can be obtained.

[0042]

As described above, according to the first aspect of the invention, the semiconductor substrate, the interlayer insulating film provided on the semiconductor substrate, and the interlayer insulating film penetrating the interlayer insulating film are formed on the semiconductor substrate. Through the contact hole that is bored, a sidewall of the same conductivity type as the diffusion layer to be contacted in the semiconductor substrate, which is provided in the contact hole, and the contact hole provided with the sidewall. Since the metal wiring connected to the diffusion layer is provided, the coverage of the metal wiring in the contact hole is improved, and a highly reliable semiconductor device can be obtained.

According to a second aspect of the present invention, a step of forming an interlayer insulating film on the semiconductor substrate, a step of forming a contact hole reaching the semiconductor substrate in the interlayer insulating film, at least the contact hole. A step of forming a polysilicon film thereon, a step of etching back the polysilicon film to form a sidewall in the contact hole, and a conductive layer having the same conductivity as the diffusion layer to be in contact with the semiconductor substrate on the sidewall. Of the barrier metal layer and the metal layer forming the metal wiring, since it includes a step of introducing a type impurity and a step of forming a barrier metal layer and a metal layer in at least the contact hole in which the sidewall is formed. The filling is easy and reliable, and the coverage of the metal wiring in the contact hole is Is good, there is an effect that highly reliable semiconductor device can be obtained.

According to a third aspect of the present invention, a step of forming an interlayer insulating film on the semiconductor substrate, a step of forming a contact hole reaching the semiconductor substrate in the interlayer insulating film, at least the contact hole. A step of forming a polysilicon film thereon, a step of etching back the polysilicon film to form a sidewall in the contact hole, and a conductive layer having the same conductivity as the diffusion layer to be in contact with the semiconductor substrate on the sidewall. Type impurities, a step of forming a barrier metal layer and a wet layer in at least the contact hole where the sidewall is formed, and a metal layer formed on the wet layer in a vacuum state at a high temperature. Since the heat treatment step is included, it is necessary to re-fill the barrier metal layer and the metal layer forming the metal wiring. Sexual well easily and reliably can be carried out, the coverage rate of the metal wiring in the contact hole is further improved, there is an effect that a more reliable semiconductor device can be obtained in fine.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view showing another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing an example of a conventional semiconductor device.

FIG. 8 is a cross-sectional view showing another example of a conventional semiconductor device.

FIG. 9 is a cross-sectional view for explaining problems in another example of the conventional semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 4 Interlayer Oxide Film 5 Contact Hole 6A, 9A Metal Wiring 6c, 9c Aluminum Alloy Film 6d Barrier Metal Layer 9d Barrier Metal Film 20 Sidewall

[Procedure amendment]

[Submission date] December 16, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

The reason why the void 10 is generated will be described with reference to FIG. Normally, the interlayer oxide film 4 is BPSG.
It is formed by or TEOS CVD method (tetraethyl d'Seo silicate) as a raw material (chemical vapor deposition). This interlayer oxide film 4 is a film which has a good so-called step coverage but is not a perfect silicon oxide film (SiO ₂ ).
It contains many defects and free oxygen (O ₂ ). In the process of the aluminum flow method, in order to improve the wettability at the interface between the aluminum alloy film and the base, an aluminum alloy film such as titanium and a metal having good wettability are laid and used as a wet layer.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Further, in the third aspect of the present invention, a polysilicon film is formed on the contact hole, the polysilicon film is etched back to form a sidewall in the contact hole, and the semiconductor substrate is formed on the sidewall. Then, an impurity having the same conductivity type as that of the diffusion layer to be contacted is introduced to make it conductive, and then a barrier metal layer and a wet layer are formed in the contact hole, and then a metal layer is formed on the wet layer in a vacuum state. Heat treatment at high temperature. As a result, the shape of the contact hole substantially becomes a predetermined shape defined by the shape of the sidewall, for example, a forward taper shape, and the wet layer is not oxidized while the metal layer is subjected to the high temperature heat treatment. Since the wettability in the hole is guaranteed, the barrier metal layer and the metal layer that compose the metal wiring can be embedded easily and reliably with good reproducibility, and the coverage rate of the metal wiring in the contact hole is further improved. To be done.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 21/8242 27/108 7210-4M H01L 27/10 325 P

Claims (3)

[Claims] 1. A semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a contact hole penetrating the interlayer insulating film on the semiconductor substrate, and provided in the contact hole. A sidewall of the same conductivity type as the diffusion layer to be contacted in the semiconductor substrate, and a metal wiring connected to the diffusion layer through the contact hole provided in the sidewall. Semiconductor device. 2. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole reaching the semiconductor substrate in the interlayer insulating film, and a step of forming a polysilicon film on at least the contact hole. A step of etching back the polysilicon film to form a side wall in the contact hole, and a step of introducing into the side wall an impurity of the same conductivity type as a diffusion layer to be contacted of the semiconductor substrate. A step of forming a barrier metal layer and a metal layer in the contact hole in which the sidewall is formed, the method of manufacturing a semiconductor device. 3. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole reaching the semiconductor substrate in the interlayer insulating film, and a step of forming a polysilicon film at least on the contact hole. A step of etching back the polysilicon film to form a side wall in the contact hole, and a step of introducing into the side wall an impurity of the same conductivity type as a diffusion layer to be contacted of the semiconductor substrate. A step of forming a barrier metal layer and a wet layer in the contact hole in which the sidewall is formed, and a step of forming a metal layer on the wet layer in a vacuum state and subjecting the metal layer to a high temperature heat treatment. Of manufacturing a semiconductor device.