JPH07221099A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a capacitance part from being polished when an interlayer insulating film which is flat is formed by a method wherein a stopper layer whose polishing speed is remarkably smaller than that of the interlayer insulating film is formed at the upper part of an element or an interconnection arrangement, the interlayer insulating film is deposited on the surface, including the upper part of the stopper layer and the interlayer insulating film is polished and removed until the stopper layer is exposed. CONSTITUTION:A second-layer interlayer insulating film 19 which is composed of a BPSG film is deposited on the whole face of the capacitance part of a memory cell 12 which is composed of a lower-part electrode 13 and of a capacitance insulating film 17 and an upper-part electrode 18 which are laminated on it. After that, a stopper film 20 which is composed of a silicon nitride film is formed. In succession, a third- layer interlayer insulating film 21 which is based on a silicon oxide film is formed. After that, a polishing operation is executed, a difference in level is eliminated in a part in which the stopper film 20 is exposed, and a flat face 22 is formed. At this time, the polishing speed of the stopper film 20 which is composed of the silicon nitride film is slow by five to ten times as compared with that of the BPSG film as the second interlayer insulating film 19. Thereby, a capacitance part including the upper- part electrode 18 is not polished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a flat interlayer insulating film on a device.

[0002]

2. Description of the Related Art In order to enable lithography and etching for finely densified wiring, an underlying insulating film must be sufficiently flattened in advance. If you need a pattern resolution of 0.5 μm or less,
It is necessary to secure the flatness of the base insulating film locally or over a wide area (over the entire surface of the exposure region). The local flatness of the underlying insulating film can be achieved by the conventionally used oxide film reflow, but when strict flatness is required over a wide area, only polishing technique is available.

The VMIC (1990 PROCEEDIN of 1990) is used as a polishing technique for flattening the underlying interlayer film of wiring.
G IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE
) In P.). 438-P. 440 has been proposed. 10 to 11 show a polishing technique for an underlying interlayer film of a wiring in the order of steps thereof.
(A)-(b) is sectional drawing which showed the planarization method using the conventional polishing in order of process, and FIG. 11 is sectional drawing which showed the planarization method using the conventional polishing in order of process. It is shown. The conventional polishing technique will be described below in accordance with this. FIG. 10A shows a cross-sectional structure of an underlying device of an insulating film for flattening. An element isolation (32), a source (33a), a drain (33b) and a gate electrode (34) are formed on a silicon substrate (31).
Further, the gate electrode (34) and the wiring (35) in the same layer as the gate electrode (34)
There is a first inter-layer insulating film (36) made of reflowed BPSG on the upper layer of which a contact (37) is formed, and a lower layer wiring (about 0.9 μm) made of CVD W / TiN / TiSi ₂ ( 38) has been formed.

From this state, as shown in FIG.
A 7 μm plasma CVD oxide film is grown on the entire surface. Here, a colloidal silica slurry is used as a polishing liquid and a polyurethane pad is used as a polishing pad, and polishing is performed for about 12 to 20 minutes by a normal polishing apparatus. In polishing, the polishing platen serves as a reference flat surface, and the convex portion has a higher polishing rate than the concave portion, so that the surface is flattened. However, in such a normal polishing method, as shown in FIG. 11, a step difference of about 20 nm to 50 nm remains. Further, if polishing is performed to remove such a step, there is a problem that the step is not reduced and the lower layer wiring (38) is exposed.

Therefore, as compared with the case of forming a highly precise flat surface, a method of providing a stopper layer for stopping polishing at a portion where polishing is not desired to exceed a certain value is disclosed in JP-A-63-76349. Was proposed in. The method will be described with reference to FIGS. This FIG. 12 (a)
6B to 6B are cross-sectional views of the structure of the wiring and the contact in order to explain the reason why the conventional planarization method by polishing using a stopper film is required. (A) is a cross-sectional view of the contact portion of the two-layer wiring. FIG. 13B is a cross-sectional view of a contact portion for explaining a problem caused by a conventional planarization method by polishing without using a stopper film, and FIGS. 13A to 13C are conventional stopper films. 14A to 14C are cross-sectional views showing, in the order of steps, a flattening method by polishing using the above method, and FIGS. 14A to 14C are cross-sectional views showing, in the order of steps, a flattening method by polishing using a conventional stopper film. .

First, the reason why the above-mentioned highly accurate flat surface is required will be described. FIG. 12A is an explanatory diagram of a two-layer wiring structure that requires a highly accurate flat surface. The second layer wiring (5) is provided to the first layer wiring (51) through the contact hole (53) formed in the insulating film (52).
4) shows the cross-sectional structure of the connected portion. In the contact portion of such a two-layer wiring, the diameter a of the contact hole (53) tends to be smaller than the depth b thereof as the integrated circuit is highly integrated. When the aspect ratio given by this b / a becomes large, for example, when aluminum is vapor-deposited as the second layer wiring (54), the insulating film (52)
The thickness t ₂ of the aluminum on the side wall of the contact hole becomes t _1> t ₂ with respect to the thickness t ₁ of the aluminum on the flat portion of the.

The current value applied to the aluminum wiring is set by calculating the step area of the aluminum wiring. In the above-described example, the contact hole (53) in the second layer wiring (54).
The cross-sectional area of the second-layer wiring (54) on the side surface of the
It becomes smaller than the cross-sectional area of the layer wiring (54), and there is a problem that the resistance becomes large in the contact hole portion. In order to solve such a problem, the first method as shown in FIG.
A method has been proposed in which a columnar convex portion (59) is provided on the layer wiring (57) and the first layer wiring (57) and the second layer wiring (62) are connected via the columnar convex portion (59). . As a method of matching the heights of the columnar convex portions (59) and the upper surface of the insulating film (52) of this structure, a highly precise flattening technique is required.

When a conventional polishing method is used to form this structure, as shown in FIG. 12 (b), the first layer wiring (52) at the same level has a columnar shape with the same height as shown by the solid line in the figure. A convex portion (55) is provided, and an insulating film (52) is deposited on the entire surface so as to completely cover the columnar convex portion (55) as shown by a dotted line. Polishing is used as a polishing technique until the surface of the columnar protrusion (55) is exposed. In this case, a distribution of the degree of polishing within the surface of the silicon substrate, that is, a portion that is over-polished (over-polished), a portion that is just well polished and a portion that is not sufficiently polished (under-polished) may occur. Is inevitable. In FIG. 12 (b), the left shape protrusion (55) is polished to the exact position, but the right columnar protrusion (55) is overpolished as indicated by the dotted line. In such a state, the distribution of polishing in the silicon substrate is the same as that of the columnar protrusion (55).
And the height of the second layer wiring (54) is non-uniform.

Therefore, the polishing technique provided with the above-mentioned stopper layer is required. 13 to 14 show a process of forming a two-layer structure wiring for explaining this technique in the order of steps. FIG. 13A shows the structure of the underlying wiring of the insulating film for planarization. Reference numeral (56) is a support substrate on which the first-layer wiring (57) is arranged. An etching stopper (58) and a columnar convex portion forming member (59) having the same shape are laminated on the first layer wiring (57). From this state, as shown in FIG. 13B, a PSG film (60) is deposited as an interlayer insulating film by 1.5 μm. Further, a polishing stopper film (silicon nitride film) (61) having a thickness of 0.3 μm and a resist film (62) are laminated on the entire surface.
Are sequentially deposited.

The polishing stopper film (61) is shown in FIG.
As shown in (b) and (c), the polishing stopper flat portion (61a) and the polishing stopper raised portion (61b) have PSG.
It is formed corresponding to the shape of the film (60). Subsequently, dry etching is performed to remove the polishing stopper raised portion (61b) as shown in FIG. 13 (c). Next, FIG.
As shown in (a), the PSG film (60) is polished until the surface of the columnar protrusion forming member (59) is exposed. Even if this polishing varies within the surface of the supporting substrate, the polishing stopper flat portion (61a) works there to prevent overpolishing.

Therefore, all the columnar protrusion forming members (5
Until the surface of 9) is exposed, polishing is performed while preventing overpolishing shown in FIG. FIG. 14 shows a shape of the structure shown in FIG. 14A after the polishing is viewed from the lateral direction.
It is shown in (b). Then, the columnar convex portion forming member (5
The etching of 9) is performed to form the columnar protrusion (59a) shown in FIG. 14C, and then the second layer wiring (62) is formed. The polishing technique provided with this stopper film can prevent overpolishing and flatten the insulating film in a relatively small area such as the contact portion of the conventional two-layer wiring as described above. The polishing stopper flat portion (61a) shown in FIG. 13 (c) occupies most of the entire area of the wafer to be polished, and the columnar protrusion forming portion (59) to be flattened (FIG. 14 (a)). ) And the surrounding area are very small areas.

Therefore, in the semiconductor device as dealt with in the present invention, in particular, in a memory device having a wide array region (having many repeating patterns),
When attempting to flatten the surface of the insulating film on this device, over-polishing, which did not occur with the above-mentioned polishing technique using the stopper film, occurred in the vicinity of the central portion of the wide array region, resulting in a flat interlayer insulating film. The shape cannot be obtained. Moreover,
If this over-polishing becomes severe, the inter-layer insulating film on the device will be completely polished and removed, and a fatal problem will occur such that the upper surface of the device is also polished.

[0013]

FIG. 15 schematically shows a device cross section in this state. That is, FIG. 15 is a diagram for explaining a problem that occurs when a planarization method by polishing using a conventional stopper film is applied to a memory device.
3 is a cross-sectional view of a memory device. FIG. When the polishing technique using the above-mentioned stopper film (73) is applied to the device as shown in FIG. 15, the convex portion (7) of the step of the insulating film to be removed by polishing is applied.
2) Since the stopper film (73) is arranged in a region other than (the portion indicated by the dotted line on the device array region (71)), the region where the stopper film (73) exists is illustrated as shown. Since it is narrow, the stopping performance of over-polishing deteriorates, and the over-polishing region (74) is formed. According to the present invention, when the convex portion of the step of the insulating film to be polished and removed is wider than the others as shown in FIG. 15, the convex portion is not over-polished and further It is an object of the present invention to provide a polishing flattening technique that prevents the device portion from being polished.

[0014]

According to the present invention, in a structure in which an array of elements or wirings having a predetermined height is present in a main surface area of a semiconductor substrate, an interlayer insulating film is formed on at least an upper portion of the array of elements or wirings. Providing a stop layer having a significantly lower polishing rate than the film, depositing an interlayer insulating film on the surface including the upper part of the stop layer, and removing the stop layer by polishing to form a flat surface And a step of manufacturing the semiconductor device. Further, in a structure in which an array of elements or wirings having a predetermined height is present in the main surface area of the semiconductor substrate, a stop layer having a significantly smaller polishing rate than the interlayer insulating film is provided at least above the array of elements or wirings. And a step of providing
A step of depositing an interlayer insulating film on a surface including an upper portion of the stop layer, a step of polishing and removing the stop layer until the stop layer is exposed, and a step of forming a flat surface for removing the stop layer by etching. And a method for manufacturing a semiconductor device.

Further, in a structure in which an array of elements or wirings having a predetermined height exists in the main surface region of the semiconductor substrate, at least an upper portion of the array of elements or wirings is provided.
Providing a stop layer having a significantly lower polishing rate than the interlayer insulating film; depositing an interlayer insulating film on the surface including the upper part of the stop layer; polishing and removing until the stop layer is exposed; A step of removing the layer by etching and forming a flat surface on which an interlayer insulating film is deposited, the method comprising the steps of:

An insulating film or a conductive film can be used as the stopper layer, that is, the stopper film, which has a significantly lower polishing rate than that of the interlayer insulating film. Specifically, a silicon nitride film or a titanium nitride film is used. Is a method of manufacturing a semiconductor device. Further, in order to provide a stop layer, that is, a stopper film, having a polishing processing speed significantly lower than that of the interlayer insulating film, on the array upper part of the element or wiring having a predetermined height in the main surface area of the semiconductor substrate, the element or wiring of the element or wiring is required. An interlayer insulating film may be provided between the upper portion of the array and the stopper film, or the interlayer insulating film may not be provided.

[0017]

According to the present invention, a stop layer having a significantly lower polishing rate than that of the interlayer insulating film is provided at least above the array of elements or wirings having a predetermined height in the main surface area of the semiconductor substrate. An interlayer insulating film is deposited on the surface including the upper part, and is polished and removed until the stop layer is exposed to form a flat surface, and the convex portion of the step of the insulating film to be polished and removed is not overpolished, Furthermore, it is possible to prevent the device portion below the convex region from being polished and to form the interlayer insulating film of the semiconductor device flat.

Embodiments of the present invention will be described with reference to the drawings.

【Example】

[Embodiment 1] FIGS. 1 to 3 are sectional views showing a first embodiment of a polishing and flattening technique of the present invention in the order of steps. In the following description, a stack capacitor type DRAM (dynamic random access memory) in which a large step difference in the insulating film is generated between the memory array region and the peripheral region is used as a base device for polishing and flattening. As for the structure of the device, the bit lines are omitted for simplicity of explanation, and only the diffusion layer region to which the bit lines are connected is referred to as a bit line.

FIG. 1 shows a device structure cross section of an underlayer of an interlayer film for planarization. Memory cells (12) are formed on a silicon substrate (11), and although only two memory cells are shown in the drawing, these memory cells are arranged to form a memory cell array (14). Hereinafter, only these two memory cells (12) will be described in detail. A bit line (15) made of an impurity diffusion layer and a storage node (12a) are formed on a silicon substrate (11). Silicon substrate sandwiching the bit line (15) (1
A gate insulating film (12b) made of a silicon oxide film is formed on the region (1), and a gate electrode (1b) is formed on the gate insulating film (12b).
By arranging 2c), a switching transistor of the memory cell (12) is formed.

On the silicon substrate (11) including the gate electrode (12c), a first silicon oxide film-based insulating film is formed.
It is covered with an interlayer insulating film (16) and adjacent gate electrodes (12
c) and the contact hole (16a) are not only laterally insulated, but also vertically insulated between the gate electrode (12c) and the lower electrode (13). The contact hole (16a) is formed in the first interlayer insulating film (16), and the storage node (12
a) and the lower electrode (13) are electrically connected.

The capacity portion which is a constituent element of the memory cell (12) includes a lower electrode and a capacity insulating film (1) laminated on the lower electrode.
7) and the upper electrode (18). The lower electrode is made of, for example, CVD-grown doped polycrystalline silicon. In 64M DRAM to 1G DRAM, the lower electrode (13) is formed to have a height of about 0.8 μm to 1.2 μm. A composite film of a silicon nitride film and a silicon oxide film is generally used as the capacitive insulating film (17),
The thickness of the silicon oxide film is about 5 nm to 3.8 nm. Further, the upper electrode is formed by CVD.
It is made of polycrystalline silicon of about 0 to 200 nm. In this state, as shown in FIG. 2, a silicon oxide film-based second interlayer insulating film (19) is deposited on the entire surface of 0.1 μm to 0.3 μm.

BPS is used as the second interlayer insulating film (19).
Reflow may be performed using a film having a reflow property such as G. After that, a stopper film (20) made of a silicon nitride film is formed by a 0.1 μm to 0.2 μm CVD method. Subsequently, as shown in FIG. 3A, a silicon oxide film-based third interlayer insulating film (21) is formed to a thickness of about 1.5 μm to 1.8 μm. Polishing is performed from this state. As the polishing technique, either a chemical mechanical polishing method or a mechanical polishing method may be used. The difference between the two is that, in the chemical polishing method, not only the ordinary polishing material (abrasive grains) is suspended in the polishing liquid, but also the material to be polished is chemically etched. By law,
Polishing is performed using a polishing liquid containing only an abrasive having no chemical etching property. As an example,
The mechanical polishing method will be described.

FIG. 16 shows a conceptual diagram of polishing. The polishing pad (82) is attached to the rotating surface plate (81), and while the polishing liquid (83) is appropriately applied, the wafer holder (84) is attached.
The wafer (85) held by is rotated while applying a load, and polishing is performed. If the polishing pad (82) is made of foamable polyurethane, has a polyurethane-impregnated polyester fiber structure, or has a laminated structure of these, it is suitable for the polishing described in the examples.
Further, as the polishing liquid, it is preferable to suspend silica abrasive grains in pure water as described above. In the chemical mechanical polishing method, for example, colloidal silica suspended in an aqueous ammonia solution may be used as a polishing liquid.

When polishing is performed by such a method, as shown in FIG.
The portion having a high step formed on the third interlayer insulating film (21) shown in (a) is selectively polished to reduce the step. In the experiment, the third interlayer insulating film (2
The speed at which the step was reduced was about 1.5 to 2 times faster than the reduction amount of the film thickness in 1). Thus, FIG.
Where the stopper film (20) shown in (b) is exposed, there is almost no step, and a flat surface shown as (22) in the figure can be formed.

Here, if the stopper film (20) is not provided as in this embodiment and the polishing is not stopped after the flat surface can be formed, the second interlayer insulating film (19) is formed. ) Is polished, and after about 2 minutes, the upper electrode (18) is also polished. When the polishing of the upper electrode (18) starts, if the upper electrode (18) is made of polycrystalline silicon, the polishing rate is higher than that of the BPSG film forming the interlayer insulating film. The whole is polished and does not function as a memory cell.

However, if a stopper film (20) made of, for example, a silicon nitride film is provided as in this embodiment, the progress rate of polishing is higher than that of the BPSG film used as the second interlayer insulating film (19). Since the (polishing rate) is about 5 to 10 times slower, the second interlayer insulating film (19) is not polished even if excessive polishing is performed for about 12 to 22 minutes after the stopper film is exposed. The capacitive part including the upper electrode (18) is not polished. The time of 12 minutes to 22 minutes is sufficient to form a flat surface on the entire surface of the wafer by adding this time even if a nonuniform image is generated in the polishing rate on the surface of the wafer. It is possible to stop the polishing with sufficient margin. Therefore, according to this embodiment, the interlayer insulating film on the capacitance portion of the DRAM having the stack capacitance can be easily flattened over the entire surface of the wafer.

[Embodiment 2] Next, a second embodiment of the present invention will be described. 4A to 4D are cross-sectional views showing a polishing step for explaining the second embodiment. The cross-sectional shape when starting polishing is the same as that in FIG. From this state, polishing is performed by the same method as in the first embodiment. As compared with the case of the first embodiment, the polishing rate of the third interlayer insulating film (21) on the lower side of the step becomes faster, and the flatness is inferior to that of the first embodiment, that is, FIG. In the case where a surface shown as a recess (23) is formed, for example, when a silicon nitride film is used as the stopper film (20), hot phosphoric acid is used to form the third interlayer insulating film (21). The stopper film (20) in the uncovered portion is removed by wet etching.

According to this method, even if the recesses (23) are formed, the upper portion of the step can be lowered by the film thickness of the stopper film (20), and there are some polishing techniques that are insufficient. This can be avoided, and a flat surface similar to that of the first embodiment can be formed. The difference between the second embodiment and the first embodiment is that
Even if the second embodiment is inferior to the first embodiment in the polishing technique, the same flat surface can be formed, that is, the polishing technique can be made more flexible.

[Third Embodiment] Next, a third embodiment will be described. In FIG. 1 used to describe the first embodiment,
The state where the upper electrode (18) and the capacitive insulating film (17) are patterned is shown. However, in the third embodiment, as shown in FIG. A stopper layer (20) made of, for example, a silicon nitride film is formed directly above the upper electrode member (18a) of FIG. 5A) by a CVD method of 0.1 μm to 0.2 μm. After that, a resist (24) is applied and patterned into a shape of the upper electrode by a lithography technique. Using this as a mask, the upper electrode member (18a) and the capacitor insulating film (17) are dry-etched, and then, as shown in FIG.
Get the shape of.

Further, a silicon oxide film-based second interlayer insulating film (19) is deposited to a thickness of about 1.5 μm to 1.8 μm. From this state, polishing is started. By this polishing, the upper part of the step of the second interlayer insulating film (19) is selectively removed, and when the stopper film (20) is exposed, a flat surface (22) as shown in FIG. 6 is obtained. This stopper (20)
As described in the first and second embodiments, the film has a polishing rate sufficiently slower than that of the second interlayer insulating film, so that the upper electrode (18) is not exposed and polished.

The difference between the third embodiment and the first and second embodiments is that the stopper film (20) is not arranged immediately above the upper electrode in the first and second embodiments, and the stopper film (20) is not provided. )
That is, an interlayer insulating film is interposed between the upper electrode (18) and the upper electrode (18). In the third embodiment, since the interlayer insulating film is eliminated, the total height of the interlayer insulating films forming the entire device becomes thin, and the depth of the contact formed in the interlayer insulating film becomes shallow. There is an advantage that the formation thereof is easy and the contact resistance is low.

[Fourth Embodiment] Next, a fourth embodiment will be described. In the fourth embodiment, the film loss of the second interlayer insulating film (19) around the stopper film (20) is large in the polishing of the third embodiment (FIG. 6), and the flatness is better than in the case of FIG. This is a method of improving flatness when a shape having an inferior shape is formed. A shape with poor flatness is shown in FIG.
There is a shape as shown in. From this state, only the stopper film (20) not covered with the second interlayer insulating film (19) is selectively and selectively removed by etching.

When, for example, a silicon nitride film is used as the stopper film (20) as in the above-described embodiments, the stopper film (20) not covered with the second interlayer insulating film by hot phosphoric acid is formed. Remove as in 7 (b). After that, a silicon oxide film-based third interlayer insulating film (2
1) is deposited on the order of 0.2 μm to 0.3 μm. According to the fourth embodiment, the stopper film (20) is formed after polishing is completed.
Even if a level difference of about 0.2 μm is formed between the second interlayer insulating film (19) and the second interlayer insulating film (19), a flat surface (22) having substantially no level difference can be formed.

The advantage of the fourth embodiment is that the substantially flat surface formed by polishing can be made more flat, and in addition, a stopper film (20) is formed on the capacitance portion and between the adjacent capacitance portions. It can be said that the silicon nitride film does not remain, so that stress is not applied to the capacitor portion. As the polishing stopper film, it is highly likely that a film material that is suitable for processing, that is, a material that is hard and easily causes stress is selected. Therefore, it is convenient from the viewpoint of device characteristics to remove this stopper film that is a source of stress. In particular, in order to increase the capacitance, a structure with less stress is preferable when a tantalum oxide film having a larger relative dielectric constant is used as the capacitance insulating film (17) instead of a laminated structure of a nitride film and an oxide film. Is. When a stress is applied to a high-dielectric-constant film, the leak current increases. Therefore, if the stress is low, the leak current can be reduced and the memory retention characteristics can be improved.

[Fifth Embodiment] Finally, a fifth embodiment will be described. In the first to fourth embodiments, the case where the insulating film is used as the stopper film has been shown, but in the fifth embodiment, the case where the conductive stopper film is used will be described. The upper electrode member (1
Instead of the stopper film (20a) on 8a), a titanium nitride film formed by, for example, a sputtering method or a CVD method is grown on the entire surface of the wafer as a conductive stopper film. Further, as described in the third embodiment, the upper electrode, the capacitor insulating film, and the conductive stopper film are patterned into a capacitor shape. The structure after growing the second interlayer insulating film (19) of the silicon oxide film on this shape is shown in FIG. Here, (20a) is a conductive stopper film. The second interlayer insulating film (19) may be formed to a film thickness of about 1.5 μm to 1.8 μm as in the previous embodiments.

Polishing is started from the state shown in FIG. By stopping the polishing when the conductive stopper film (20a) is exposed, the first flat surface (22a) as shown in FIG. 8B can be formed. In this case, since the stopper film has conductivity, it is not possible to form the wiring in the upper layer as it is. Therefore, as shown in FIG.
By forming the silicon oxide film-based third interlayer insulating film (21), the final second flat surface (22b) can be formed.

In this embodiment, the conductive stopper film (2
Although a titanium nitride film is used as 0a), it has a more excellent function as a stopper for polishing than the stopper film using a silicon nitride film shown so far, so that the effect of protecting the capacitance portion can be further increased. Further, when the high dielectric constant film is used as the capacitive insulating film, the metal-based film is used as the upper electrode, which is also advantageous in that the consistency of the entire process is good.

In these examples, the planarization of the interlayer insulating film above the capacitor has been described. For the formation of the memory cell, a contact hole is opened in this interlayer insulating film.
A process such as forming the wiring mainly of aluminum is required. In some cases, one or more wirings may be formed on the upper layer. The flattening method of the present invention can be applied to flattening the interlayer insulating film on the wirings arranged in an array as described above, and a flat surface suitable for forming the wiring of the upper layer can be formed. It is possible to form. Further, as an example among silicon oxide film-based materials as an interlayer insulating film for planarization,
Although the BPSG film having the reflow property is used, the same effect is obtained when an oxide film containing no phosphorus or boron having a small reflow property, for example, an oxide film formed by plasma CVD or an oxide film formed by atmospheric pressure CVD is used. Is obtained.

[0039]

According to the flattening method of the interlayer insulating film of the present invention, the step of the interlayer insulating film between the array region and the peripheral region which is a problem in the DRAM memory cell array can be removed, and the flat interlayer insulating film can be formed. Can be formed. This flat interlayer insulating film shape has the effect of facilitating the formation of a device such as an upper wiring layer and enabling the device to be miniaturized and highly integrated.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of planarizing an interlayer insulating film according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of planarizing an interlayer insulating film according to the first embodiment of the present invention in the order of steps.

3A and 3B are cross-sectional views showing a method of planarizing an interlayer insulating film according to the first embodiment of the present invention in the order of steps.

4A and 4B are cross-sectional views showing a method of planarizing an interlayer insulating film according to a second embodiment of the present invention in the order of steps.

5A and 5B are cross-sectional views showing a method of planarizing an interlayer insulating film according to a third embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing a step of a method of planarizing an interlayer insulating film according to a third embodiment of the present invention.

7 (a) and 7 (b) are cross-sectional views showing a method of planarizing an interlayer insulating film according to a fourth embodiment of the present invention in the order of steps.

8A and 8B are cross-sectional views showing a method of planarizing an interlayer insulating film according to a fifth embodiment of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing a method of planarizing an interlayer insulating film according to a fifth embodiment of the present invention in the order of steps.

10 (a) and 10 (b) are cross-sectional views showing a conventional planarizing method using polishing in the order of steps.

FIG. 11 is a cross-sectional view showing a conventional flattening method by polishing in the order of steps.

12 (a) and 12 (b) are cross-sectional views of a conventional wiring and contact structure using a stopper film, and FIG.
It is sectional drawing of the contact part of layer wiring. (B) is a cross-sectional view of a contact portion in which a conventional stopper film is not used.

13A to 13C are cross-sectional views showing, in the order of steps, a conventional flattening method by polishing using a stopper film.

14A to 14C are cross-sectional views showing a conventional planarizing method by polishing using a stopper film in the order of steps.

FIG. 15 is a cross-sectional view of a memory device for explaining a problem that occurs when a conventional planarizing method by polishing using a stopper film is applied to the memory device.

FIG. 16 is a conceptual diagram for explaining a polishing technique and a polishing method used in the examples of the present invention.

[Explanation of symbols]

 11 Silicon Substrate 12 Memory Cell 13 Lower Electrode 14 Memory Cell Array 15 Bit Line 16 First Interlayer Insulating Film 17 Capacitance Insulating Film 18 Upper Electrode 18a Upper Electrode Member 19 Second Interlayer Insulating Film 20 Stopper Film 20a Conductive Stopper Film 21 Third Interlayer Insulating film 22 Flat surface 22a First flat surface 22b Second flat surface 23 Recess 24 Resist 32 Element isolation 33a Source 33b Drain 34 Gate electrode 35 Wiring 36 First interlayer insulating film 37 Contact 38 Lower layer wiring 39 Second interlayer insulating film 40 step 51 first layer wiring 52 insulating film 53 contact hole 54 second layer wiring 55 columnar convex portion 56 supporting substrate 57 first layer wiring 58 etching stopper film 59 columnar convex portion forming member 59a columnar convex portion 60 PSG film 61 polishing stopper Membrane 61a Polishing stock Over the flat part 61b polishing stopper ridges 62 resist film 71 device array region 72 convex portion 73 stopper film 74 over-polishing region 81 rotating platen 82 Polishing pad 83 Polishing solution 84 wafer holder 85 Wafer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 27/108 7210-4M H01L 27/10 325 C

Claims (5)

[Claims] 1. In a structure in which an array of elements or wirings having a predetermined height exists in a main surface region of a semiconductor substrate, a polishing processing speed is remarkably higher than that of an interlayer insulating film on at least an upper portion of the array of elements or wirings. A step of providing a small stop layer, a step of depositing an interlayer insulating film on the surface including the upper part of the stop layer, and a step of polishing and removing until the stop layer is exposed to form a flat surface. Of manufacturing a semiconductor device. 2. In a structure in which an array of elements or wirings having a predetermined height is present in a main surface region of a semiconductor substrate, a polishing processing speed is remarkably higher than that of an interlayer insulating film on at least an upper portion of the array of elements or wirings. Providing a small stop layer, depositing an interlayer insulating film on the surface including the upper part of the stop layer, polishing and removing until the stop layer is exposed, and then forming a flat surface for removing the stop layer by etching A method of manufacturing a semiconductor device, comprising: 3. In a structure in which an array of elements or wirings having a predetermined height is present in a main surface region of a semiconductor substrate, a polishing speed is significantly higher than that of an interlayer insulating film at least above the array of elements or wirings. Providing a small stop layer, depositing an interlayer insulating film on the surface including the upper part of the stop layer, polishing and removing until the stop layer is exposed, then removing the stop layer by etching, and then And a step of forming a flat surface on which an interlayer insulating film is deposited. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the stop layer having a polishing rate significantly lower than that of the interlayer insulating film is a silicon nitride film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the stop layer having a polishing rate significantly lower than that of the interlayer insulating film is a titanium nitride film.