JPH07220406A - PRML phase synchronization circuit - Google Patents

Abstract

(57) [Summary] [Object] A steady phase error due to a calculation error is reduced in a phase synchronization circuit for PRML of a magnetic disk device. [Structure] A sample hold and distributor ₁ which outputs sample signals Y _2m , Y _{2 (m-1)} , and Y _2m-1 at the same timing for every two symbols of a reproduced signal, and three values of those sample signals. The first to third ternary decision circuits 2 to 4 for making a decision and the first difference for the sample signals Y _2m and Y _{2 (m-1) in} the even columns
Subtractor 5, _first and second multipliers 6 and 7 for multiplying the ternary judgment output signal of the sample signal of the even number column and the sample signal Y _2m-1 of the odd number column, and the sample signal of the odd number column The third multiplier 8 that multiplies the output signal of the first subtractor 5 by the ternary determination signal, and the second and third output signals of the first multiplier 6
Second subtractor 9 for subtracting the output signals of the multipliers 7, 8 of
, A loop filter 10, and a voltage controlled oscillator 11 that outputs a sample clock signal.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a partial response (PR) system and maximum likelihood detection (M).
The present invention relates to a phase locked loop circuit for PRML of a magnetic disk device, which is combined with an OST Likelihood method. In the magnetic disk device, development of high-density recording is being advanced in response to the demand for miniaturization and large capacity. Accordingly, the reproduced signal read by the head has a low level and is subjected to intersymbol interference, which causes a problem that the demodulated data contains an error. In order to solve such a problem, the PRML method, which is a combination of the PR (partial response) method and the ML (maximum likelihood detection) method, is regarded as promising.

The PRML system is a system for detecting the maximum likelihood of the amplitude of a reproduction signal at a point (signal point) where the eye pattern is most opened. In this case, since the PR method is used, when the eye becomes an acute angle and the sample point shifts, the data error rate is rapidly deteriorated. Therefore, P
In the RML method, accuracy of sampling timing is required. Therefore, the sampled signal is arithmetically processed to obtain the phase error, and the control point corresponding to the phase error is fed back to the voltage controlled oscillator for generating the sample clock signal, so that the signal point and the sample point are separated. Phase synchronization is required.

[0003]

2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example.
2 is a sample hold circuit (S / H), 83 and 84 are 3
Value judging circuit, 85 and 86 are multipliers, 87 is an adder, 88
Is a loop filter (LF), 89 is a voltage controlled oscillator (V
CO), 90 and 91 are maximum likelihood detectors.

A reproduction signal of the magnetic disk device is equalized into a waveform according to a PR (Partial Response) system by an equalizer (not shown), and a sample hold circuit 81 is provided.
And is sampled and held by the sample clock signal from the voltage controlled oscillator 89. In this case, the reproduction signal read from the magnetic disk by the head corresponds to the signal differentiated from the write signal, so that when D is one sampling period, the reproduction signal has a waveform corresponding to 1-D. Then, when equalized with the characteristic of 1 + D by the equalizer, 1-D
^The waveform corresponds to Class IV of the PR system of No. ² . This equalized reproduction signal becomes a ternary analog signal.

The signal Y _{n at} time n sampled and held by the sample and hold circuit 81 is supplied to the multipliers 85 and 3
In addition to the value judgment circuit 84, it is added to the maximum likelihood detectors 90 and 91 which are switched every sample period.
Further, the signal Y _n-1 sampled and held in the next sample and hold circuit 82 is supplied to the multiplier 86 and the ternary decision circuit 8
In addition to 3. Ternary decision circuit 83 and 84, the signal Y _n-1, Y _n sampled and held by the level identification -1,0 performs a ternary decision of +1.
Further, the multiplier 85 outputs the judgment output signal X of the three-value judgment circuit 83.
_n-1 is multiplied by the sample-and-hold signal Y _n ,
Further, the multiplier 86 outputs the judgment output signal X _n of the three-value judgment circuit 84.
And the sampled and held signal Y _n-1 are multiplied, and in the adder 87, the output signal of the multiplier 85 is used to calculate the multiplier 8
The output signal of 6 is subtracted to obtain the phase error signal τ _n . That is, the phase error signal τ _n is obtained by τ _n = Y _n-1 X _n -Y _n X _n-1 (1).

The phase error signal τ _n is converted into the loop filter 8
8 is used as a control voltage of the voltage controlled oscillator 89 to synchronize the phase of the sample clock signal with the phase of the reproduction signal (for example, Mueller et al., "Timing recovery i").
n digital synchronous datareceivers ”, IEEE
TRANS. vol. COM-24, No. 5, May1
976, pp.516-631).

[0007]

In the above-mentioned conventional example, the following calculation error occurs at the change point due to the delay of the three-value determination processing in the three-value determination circuits 83 and 84. τ _n = Y _n-1 X _n-1 -Y _n X _n-2 (2) Since the correlated Y _n-1 X _n-1 term cannot be removed by the loop filter 88, It will remain as a stationary phase error.

Further, there is a strong demand for high-speed transfer, and accordingly, the sample period is shortened. With the shortening of the sample period, the ratio of the calculation error increases and the steady phase error increases, so that the data There is a problem that the deterioration of the error rate becomes large. It is an object of the present invention to reduce the steady phase error caused by the phase error calculation.

[0009]

A phase-locked loop circuit for PRML according to the present invention will be described with reference to FIG. 1. When the sampling timing is m for every two symbols from the reproduction signal of the magnetic disk device, the sampling signal is at the same timing. Y _2m ,
Y 2 _(m-1), a sample hold and distributor 1 for outputting a Y _2m-1, the sample signal _{Y 2m, Y 2 (m-} 1), Y 2m-1 ternary determines first to third Of the three-value determination circuits 2, 3 and 4, the first subtracter 5 for _obtaining the difference between the sample signals Y _{2 (m-1)} and Y _{2m in} the even columns, and the sample signals Y _2m and Y _{2 (in the} even columns _{) m-1)} three-value determination output signal and odd-numbered sample signal Y _2m-1 for multiplying _first and second multipliers 6 and 7, and odd-numbered sample signal Y _2m-1 three-value determination From the output signals of the third multiplier 8 and the first multiplier 6 that multiply the output signal and the output signal of the first subtractor 5, the output signals of the second and third multipliers 7 and 8 , A loop filter 10 for adding the output signal of the subtractor 9,
And a voltage controlled oscillator 11 for applying the output signal of 1 as a control voltage for controlling the phase of the sample clock signal.

Further, the sample-hold and distributor 1 divides the sample clock signal by two to obtain a positive-phase and negative-phase sample clock signal, a frequency divider, an even-numbered column tracking holder, and an odd-numbered column tracking holder. And a reproduction signal is alternately sampled and held for each symbol by the sample clock signals of the positive phase and the negative phase in the tracking holder of the even-numbered column and the tracking holder of the odd-numbered column, and the sampled signal is sampled every two symbols. Y _2m , Y _{2 (m-1)} , Y
_2m-1 can be output at the same timing.

Further, the second ternary judgment circuit 3 can be constituted by a flip-flop which delays the ternary judgment output signal of the first ternary judgment circuit 2.

[0012]

From the sample hold and distributor 1, every two symbols, the sample signal Y _2m ,
Y2 _(m-1) and _Y2m-1 are output. The three-value determination output signals of the first to third three-value determination circuits 2 to 4 are set to X _2m , X _{2 (m-1)} , and X _2m-1.
Then, from the first multiplier 6, Y _2m-1 × X _2m
From the multiplier 7 of Y _2m-1 × X _{2 (m-1)} to the third multiplier 8
From the output _{(Y 2m -Y 2 (m-} 1)) × X 2m-1. Then, from the second subtractor 9, τ _2m = (Y _2m-1 × X _2m )-(Y _2m-1 × X _{2 (m-1)} )-(Y _2m -Y _{2 (m-1)} ) × X _2m-1 (3) is output. In this case, due to the delay due to the three-value determination, the following calculation error occurs at the change point. τ _2m = (Y _2m-1 × X _{2 (m-1)} )-(Y _2m-1 × X _{2 (m-2)} )-(Y _2m -Y _{2 (m-1)} ) × X _{2 (m -1) -1} (4) Since this calculation error does not have a correlated term, it is removed by the loop filter 10, so that a steady phase error does not occur.

The sample and hold and divider 1 is composed of a frequency divider and a plurality of tracking holders. The frequency divider divides the sample clock signal by two to divide it into a positive phase and a negative phase. Phased sample clock signals are used to form an even-numbered column and an odd-numbered column in which a plurality of tracking holders are connected in cascade, and the positive and negative phased sample clock signals are alternately added to each other, and the reproduction signal is alternately set for each symbol. The sample signals Y _2m and Y _2m , Y are sampled and held in the even-numbered columns and the odd-numbered columns, so that every two symbols have the same timing.
_{2 (m-1)} and Y _2m-1 can be output.

Since the second ternary decision circuit 3 makes a ternary decision of the sample signal two symbols before the first ternary decision circuit 2, the third ternary decision circuit 3 has a three-valued decision. By delaying the value judgment output signal by two symbols by the flip-flop, the same three-value judgment output signal as the second three-value judgment circuit 3 can be obtained.

[0015]

FIG. 2 is an explanatory view of the first embodiment of the present invention, in which 21 to 27 are tracking holders (T / H), 28
˜30 is a ternary decision circuit, 31˜33 are multipliers, 34, 3
5 is a subtractor, 36 is a loop filter (LF), 37 is a voltage controlled oscillator (VCO), 38 is a flip-flop that constitutes a frequency divider circuit, and 39 and 40 are maximum likelihood detectors.

The tracking holders 21 to 24 are connected in cascade to form an even column, the tracking holders 25 to 27 are connected to form an odd column, and the clock signal from the voltage controlled oscillator 37 is applied to the clock terminal CK of the flip-flop 38.
To the output terminal * Q of the flip-flop 38 and the data terminal D to form a frequency divider, and the positive-phase sample clock signal sck is output from the output terminal Q of the flip-flop.
1. Sample clock signal sc of opposite phase from output terminal * Q
Output k2 respectively.

The positive phase sample clock signal sck
1 to the tracking holders 21, 23 and 26, and the reverse phase sample clock signal sck2 is added to the tracking holder 2
Add to 2, 24, 25, 27. With these configurations, the sample hold and distributor 1 in FIG. 1 is configured. Further, the three-value determination circuits 28 to 30 are the second, first, and second
Corresponding to the third ternary value judging circuits 3, 2 and 4, the multipliers 31 to 31
Reference numeral 33 corresponds to the second, first and third multipliers 7, 6, 8 in FIG. 1, and subtractors 34, 35 correspond to the first and second subtractors 5, 9 in FIG.

A reproduction signal of the magnetic disk device is equalized by an equalizer (not shown) and applied to the head tracking holders 21 and 25 of even and odd columns. Therefore, for example, the 0th symbol of the reproduced signal is the positive phase sample clock signal sck1 in the tracking holder 21.
And the next first symbol is sampled in the tracking holder 25 by the anti-phase sample clock signal sck2. At that time, the 0th symbol sampled by the tracking holder 21 is shifted to the next tracking holder 22.
In this case, the tracking holders 21 and 22 correspond to master / slave flip-flops, and the tracking holders 23 and 24 also correspond to master / slave flip-flops. Similarly, the tracking holder 2
Reference numerals 5 and 26 also correspond to master-slave flip-flops. The tracking holder 27 is for timing adjustment.

In the same manner as described above, the even-numbered symbols are assigned to the even-numbered column tracking holders 21 to 24 by the sample clock signals sck1 and sck2 of the positive phase and the negative phase.
The odd-numbered symbols are sample-held by the tracking holders 25 to 27 in the odd-numbered columns. Then, the output signal of the tracking holder 24 is set to Y
_{2 (m-1)} , the output signal of the tracking holder 22 is _Y2m , and the output signal of the tracking holder 27 is _Y2m-1 , the signals Y2 _(m-1) , _Y2m , and Y output at the same timing. _2m-1
Indicates that sample signals of the 0th, 2nd, and 1st symbols are set when m = 1. The maximum likelihood detector 39 demodulates the data using the sample signal Y _{2 (m-1)} of the even-numbered symbol, and the maximum likelihood detector 40 uses the sample signal Y _2m-1 of the odd-numbered symbol. The data will be demodulated. In this case, the maximum likelihood detector 39 as in the conventional example,
There is no need for a means for switching 40.

Therefore, for every two symbols, the odd-numbered symbol sample signal Y _2m-1 and the even-numbered symbol sample signals Y _{2 (m-1)} and Y _2m before and after it are output at the same timing. It These sample signals Y _{2 (m-1)} ,
Since Y _2m and Y _2m-1 are signals of three-valued level as described above, three-valued determination circuits 28 to 30 respectively perform three-valued determination. Each three-value judgment signal X _{2 (m-1)} , X _2m , X _2m-1
Are added to the multipliers 31-33.

In the multiplier 31, Y _2m-1 ×
X _{2 (m-1)} , in the multiplier 32, Y _2m-1 × X _2m , and in the multiplier 33, (Y _2m −Y _{2 (m-1)} ) × X _2m-1 Multiplication is performed and the multiplication output signal is input to the subtractor 35. The subtractor 35 is (Y _2m-1 × X _2m )-(Y _2m-1 × X _{2 (m-1)} )-
The calculation of [(Y _2m −Y _{2 (m−1)} ) × X _2m−1 ] is performed to obtain the phase error signal and add it to the loop filter 36. This phase error signal becomes the control voltage of the voltage controlled oscillator 37 via the loop filter 36, and the predetermined sampling point of the equalized reproduction signal and the phase of the sample clock signal from the voltage controlled oscillator 37 are synchronized. .

In this case, a calculation error as expressed by the above equation (4) occurs, but since the calculation error does not include a term having a correlation and only high-frequency components are included, the loop filter 36 facilitates the calculation. Can be removed. Thereby, the steady phase error can be reduced.

FIG. 3 is an explanatory view of the second embodiment of the present invention. The same reference numerals as those in FIG. 2 indicate the same parts, and 37A is a voltage controlled oscillator (VCO). This voltage controlled oscillator 37A
2 has a configuration in which the oscillation frequency is 1/2 of that of the voltage controlled oscillator 37 in FIG. 2 and the complementary output signals of the positive phase and the negative phase are obtained, and the flip-flop circuit constituting the frequency divider in FIG. This makes it possible to omit the loop 38. Other configurations and operations are similar to those of the embodiment shown in FIG.

FIG. 4 is an explanatory view of the third embodiment of the present invention, in which 51 to 57 are tracking holders (T / H) and 58.
Is a flip-flop (FF), 59 and 60 are ternary decision circuits, 61 to 63 are multipliers, 64 and 65 are subtractors, 66 is a loop filter (LF), 67 is a voltage controlled oscillator (VC).
O), 68 is a flip-flop which constitutes a frequency dividing circuit, 6
Reference numerals 9 and 70 are maximum likelihood detectors.

This embodiment corresponds to a structure in which a flip-flop 58 is provided instead of the ternary value judging circuit 28 of the embodiment shown in FIG. That is, the second three-value determination circuit 3 of FIG.
Corresponds to the configuration of a flip-flop that delays the three-value determination output signal X _n of the first three-value determination circuit 2. This is the sample signal Y _{2 (m-
1)} is the sample signal Y _2m from the tracking holder 52
Are the sample clock signals sck1, sck of the positive phase and the negative phase.
Since it corresponds to the signal delayed by ck2, the ternary judgment output signal X of the ternary judgment circuit 28 in FIG.
_{2 (m-1)} is the same as the delayed three-value determination output signal _X2m of the three-value determination circuit 29. Therefore, the three-value determination circuit 5
The ternary judgment output signal X _2m of 9 is added to the data terminal D of the flip-flop 58, and the positive-phase sample clock signal sck1 is added to the flip-flop 58.
_2m is output from the output terminal Q of the flip-flop 58 as a three-value determination output signal X _{2 (m- 1)} .

Further, the voltage controlled oscillator 67 is configured to output a sample clock signal of a complementary signal of a positive phase and a negative phase, similarly to the voltage controlled oscillator 37A of the embodiment shown in FIG. 3, and a flip-flop constituting a frequency divider. It is also possible to adopt a configuration in which the cap 68 is omitted. The present invention is not limited to the above-mentioned embodiments, but various additions and modifications can be made.

[0027]

As described above, according to the present invention, the PR
In a phase locked loop circuit of the PRML system in which the (partial response) system and the ML (maximum likelihood detection) system are combined,
A voltage-controlled oscillator that outputs sample signals Y _2m , Y _{2 (m-1)} , and Y _2m-1 at the same timing every two symbols from a reproduction signal of a magnetic disk device, and _obtains a phase error to generate a sample clock signal. 11 is controlled, and the phase error calculation does not include a term having a correlation with the calculation error, so that it can be easily removed by the loop filter 10. Therefore, there is an advantage that a steady phase error due to a calculation error does not occur.

Further, by providing an even-numbered column tracking holder and an odd-numbered column tracking holder and sample-holding the reproduced signal by the two-phase sample clock signals of the positive phase and the negative phase, 1/2 of the conventional example is obtained. Since it can be realized by a circuit configuration that operates at the speed of, it is possible to reduce power consumption. Therefore, there is an advantage that integration into an integrated circuit is facilitated.

Further, the second ternary judgment circuit 3 is constituted by a flip-flop, and the ternary judgment output signal of the first ternary judgment circuit 2 is delayed to reduce the circuit scale,
There is an advantage that power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Sample and Hold and Distributor 2-4 First to Third Three-Valued Judgment Circuit 5 First Subtractor 6-8 First to Third Multiplier 9 Second Subtractor 10 Loop Filter (LF) 11 Voltage Controlled oscillator (VCO) 12,13 Maximum likelihood detector

Claims (3)

[Claims] 1. A PRML phase-locked loop circuit for a magnetic disk device in which a partial response method and a maximum likelihood detection method are combined, wherein the sampling timing is m for every two symbols from the reproduced signal of the magnetic disk device, and the same timing is used. in sample signal _{Y 2m, Y 2 (m-} 1), sample-and-hold and distributor outputs the Y _2m-1 (1), the sample signal _{Y 2m, Y 2 (m-} 1), the Y _2m-1 First to third three-value determination circuits (2), (3), (4) for three-value determination
When the sample signal Y _2m in the even-numbered columns, Y 2 first subtractor for obtaining the _(m-1) the difference between (5), the sample signal Y _2m of the even columns, Y 2 _(m-1) of the 3 _First and second multipliers (6) and (7) for multiplying the value judgment output signal and the odd-numbered sample signal Y _2m-1 and the three-value judgment output of the odd-numbered sample signal Y _2m-1 A third multiplier (8) for multiplying a signal by the output signal of the first subtractor (5), and the second and third multiplications from the output signal of the first multiplier (6) Second, which subtracts the output signals of the devices (7) and (8)
Subtractor (9), a loop filter (10) for adding the output signal of the second subtractor (9), and the output signal of the loop filter (10) as a control voltage for controlling the phase of the sample clock signal. A phase locked loop circuit for PRML, comprising: a voltage controlled oscillator (11) to be applied. 2. The sample-hold and distributor (1)
Includes a frequency divider that divides the sample clock signal by two to obtain a positive-phase and negative-phase sample clock signal, an even-numbered column tracking holder, and an odd-numbered column tracking holder. In the even-numbered tracking holders and the odd-numbered tracking holders, the sample clock signals of the positive phase and the negative phase are alternately sampled and held for each symbol, and the sample signal Y _{2 (m- 1)} , Y _2m-1 and Y _2m are output at the same timing.
ML phase locked loop circuit. 3. The second ternary decision circuit (3) is constituted by a flip-flop for delaying the ternary decision output signal of the first ternary decision circuit (2). 1. A phase-locked loop circuit for PRML according to 1.