JPH07219796A - Information processor - Google Patents

Abstract

PURPOSE:To attain the retrial of an instruction generating an error in CPU. CONSTITUTION:CPU includes CSVR 4 storing the same contents as CVR 3 one cycle behind. When an error is generated in an arithmetic unit 1, at the same time when an error flag becomes active, data at the time of the generation of the error is written into SVR 3. That the error becomes active deters writing into CSVR 4. In this case, the contents in CSVR 4 are restored in SVR 3 so as to retry the instruction generating the error. On the other hand, when the error is detected in CSVR 4, the contents in CSV 3 are restored in CSVR 4 and retried. The error is processed under the control of a diagnostic processor. Whether to mediate a firmware for generating timing of shifting control to the diagnostic processor or not is indicated by setting a mode flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device having an error recovery mechanism, and more particularly to a register opened to software (software visible register, hereinafter referred to as S
The present invention relates to an information processing device having an error recovery mechanism (referred to as VR).

[0002]

2. Description of the Related Art In a conventional information processing apparatus, when a failure occurs in the central processing unit, if the data affected by the failure is written to the SVR, the instruction is retried from the time when the failure occurred. It will be difficult. This is because the data required for the retry is overwritten and lost by writing the data affected by the failure in the SVR.

It is theoretically possible not to write to the SVR when a failure occurs, but in reality, it is necessary to collect error occurrence signals from various parts in the central processing unit to suppress the writing to the SVR. However, this process takes time. In particular, recent information processing devices operate under a high-speed clock, and it is more difficult to suppress writing to the SVR.

A failure recovery mechanism of this type is intended to recover from a soft error in a memory chip of a main memory connected to a central processing unit via a bus, as shown in US Pat. No. 4,996,687, for example. A backup memory having the same contents as the main memory is provided, and the contents of the backup memory are returned to the main memory when a failure occurs.

[0005]

In the above-mentioned prior art,
The state in the central processing unit cannot be backed up appropriately. Therefore, for example, there is a problem that it is impossible to deal with a case where erroneous data is overwritten in the SVR due to an error occurring in the arithmetic unit.

Further, if the central processing unit is reset during the processing of a certain instruction during the error processing, there is a possibility that the instruction may not be retried even after the reset.

On the other hand, there is a case where urgency is required and it is necessary to generate an interrupt immediately rather than retrying.

The object of the present invention is to solve the above-mentioned problems, and even if incorrect data is overwritten in the SVR due to an internal error of the central processing unit, it is possible to retry the instruction from the time when the error occurs. Another object of the present invention is to provide an error recovery mechanism for realizing an information processing device with high fault tolerance. Furthermore, it aims at realizing this error recovery mechanism flexibly.

Another object of the present invention is to adjust the timing at which error processing is activated in order to increase the probability of successful retry of an instruction after reset. further,
The purpose is to identify the location of the error and retry from an appropriate state.

Further, another object of the present invention is to select whether to give priority to retries or urgency by mode setting.

[0011]

In order to solve the above problems, according to the present invention, there is provided an error recovery mechanism in an information processing apparatus having a central processing unit including a group of storage means composed of at least one word. It may include a group of auxiliary storage means having the same structure as the storage means and having the data written therein after a certain data is written in the storage means. It may also include error detection means for detecting an error that has occurred in the central processing unit.
Further, it may include an error processing unit that processes an error in the central processing unit and returns the central processing unit in response to the error notification from the error detection unit.

The error processing means analyzes the cause of the error in the central processing unit, saves the contents of the storage means and the preliminary storage means in the save area, and then resets the central processing unit to save the saved area. It may further include an error processing processor for restoring the contents to the storage means and the preliminary storage means.

The error processing means prepares for error processing from the error report from the error detection means,
It may further include error processing firmware that generates timing suitable for error recovery and causes the error processing processor to start error processing at the timing.

Further, the error detecting means may include a preliminary storage error detecting section for detecting an error generated in the group of preliminary storage means. Further, the error processing means may include a preliminary storage error flag indicating that an error has occurred in the preliminary storage error detection unit, and when the error processing processor restores the contents of the save area to the storage means and the preliminary storage means. If the preliminary storage error flag indicates "error occurred", the contents of the save area relating to the storage means are restored to the storage means and the preliminary storage means, and if the preliminary storage error flag indicates "error not occurred", preliminary storage The contents of the save area relating to the means may be restored to the storage means and the preliminary storage means.

Also, the error processing means specifies an error processing mode in which an error detected by the error detection means is directly notified to the error processing processor or a mode in which the error processing processor is activated via the error processing firmware. It may further include a flag.

The group of storage means may be a group of registers, and the group of preliminary storage means may be a group of backup registers.

The group of storage means may be a group of registers visible to software.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the data transmitting / receiving apparatus of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention adopts a pipeline structure, an arithmetic stage 31 for performing an arithmetic operation, a writing stage 32 for writing an arithmetic result into an SVR 3, and an arithmetic operation. Copy result SV
Copy stage 33 for writing to R (hereinafter, CSVR) 4
And an error check stage 34 for checking the occurrence of an error.

In the arithmetic stage 31, the arithmetic circuit 1 performs an arithmetic operation. As a result of this calculation, the error detection circuit 23 detects whether or not a failure has occurred in the calculation circuit 1.

In the write stage 32, the calculation result of the calculation circuit 1 is written in the SVR 3. The SVR3 is a software-visible register and is generally configured to have a plurality of words each having a plurality of bytes. Therefore, the write stage 32 has a write data register (WDR) that holds the calculation result from the calculation circuit 1.
12, a write address register (WAR) 11 that holds the write address of the SVR 3, and a write flag (WF) 17 that instructs the SVR 3 to write. Further, the error information detected by the error detection circuit 23 is the error detection flag group (E
F) Hold at 5. The writing stage 32 includes an OR circuit 6 to detect that any error information held in the error detection flag group 5 indicates that an error has occurred.

In the copy stage 33, a CSVR4 for backup of the SVR3 is provided, and the calculation result by the calculation circuit 1 is written in the CSVR4. This CSVR
4 has the same configuration as SVR3 and has the contents one clock before SVR3. This CSVR4 cannot be recognized by software, that is, it does not appear in the instruction set. Therefore, the copy stage 33 uses the copy WD that holds the value of the write data register 12 with a delay of one clock.
R (CWDR) 14 and copy write address register (CWAR) 1 that holds the write address of CSVR 4
3 and a copy write flag (CWF) 18 for instructing writing to the CSVR 4. It also includes an error flag (EF) 19 that holds the error information collected by the OR circuit 6. In addition, CSVR
4 for reading the CSVR 4 for the purpose of detecting the error occurrence, the copy read address register (CRAR) 15 for holding the read address and the increment circuit 27 for incrementing the content of the copy read address register 15 by one. Includes and.

In the error check stage 34, the CSV
An error detection circuit 2 for detecting the occurrence of an error in R4 is provided, and together with the information of the error flag 19, a check for activating error processing is performed. Therefore, in the error check stage 34, a copy data read register (CDR that holds read data from the CSVR 4 is stored.
R) 16 is included. As will be described later, a mode flag (M
DF) 20 is included. Further, an event flag (EVF) 22 indicating that error processing via the firmware has been started, and a diagnostic processor (DGP) 2
4 includes an error display flag (EIF) 21 indicating that the error processing for No. 4 has been started. This DGP2
Reference numeral 4 denotes a processor for diagnosing the information processing device,
It has a DGP memory (DGPM) 26 as a memory dedicated to P.

The information processing apparatus of this embodiment is a CP
Although it is assumed that the U firmware (CPU-FW) 25 controls the firmware, this may be based on hardware connection logic.

In the above structure, the calculation result by the calculation circuit 1 of the calculation stage 31 is sent to the SVR 3 via the WDR 12.
Written in. At this time, the write destination address of the SVR 3 is the one held by the WAR 11. The write timing is given by the WF 17. These WAR11 and WF17 are set based on the command corresponding to the write data. The result of this calculation is CWDR1 at the next clock written in SVR3.
Written to CSVR4 via 4. In this case CSVR
As the write destination address of 4, the address held by the CWAR 13 is used. The write timing is CWF.
Given by 18. That is, CSVR4 is S
This means that the state of one clock before VR3 is held.

When an error occurs in the arithmetic circuit 1, the error is detected by the error detection circuit 23 of the arithmetic stage 31, and the corresponding flag of the error detection flag group 5 becomes active. Then, the OR circuit 6 generates a logical sum of all bits of the error detection flag group 5,
The error flag 19 becomes active. In this case, the calculation result regarding the error is written in SVR3, but is not written in CSVR4. This is CSV
This is realized by inputting the negative logic of the error flag 19 as the input of the AND circuit 8 which instructs the writing to R4. That is, since the error flag 19 becomes active, its negative logic becomes inactive,
This is because the output of the AND circuit 8 is made inactive regardless of the value of the CWF 18. Therefore, when an error occurs in the arithmetic circuit 1, the state immediately after the error occurs is held in the SVR3, while the state immediately before the error occurs is held in the CSVR4.

When an error occurs in the CSVR 4, the error detection circuit 2 of the error check stage 34
Detects the error. This CSVR4 error is detected as follows. For CSVR4, C
Write data is written from the WDR 14, and in parallel with this, data reading for error detection is performed in the CDRR 16. Read-out to this CDR R16 is CRAR1
It is performed according to the address indicated by 5. This CRAR15
Is incremented every clock by the increment circuit 27 to sequentially point each word.
This CRAR15 is cyclically incremented so that if it points to the last word, the next clock will point to the first word. The error detection circuit 2 detects the occurrence of an error in the data read by the CDRR 16 by a method such as parity check.

According to the information from the error detection circuit 2 or the error display flag 19, the error check stage starts the error processing as follows. First, when the error detection circuit 2 detects an error, the AND circuit 9
And the event is input to the input terminal of the AND circuit 10. On the other hand, MDF is connected to the other input terminals of those AND circuits.
A signal based on 20 is input, and the output of only one of the AND circuits is controlled to be active. That is, the output of the error detection circuit 2 is MDF2.
If 0 is "1", it is output from the AND circuit 9 and MDF
If 20 is "0", it is output from the AND circuit 10.
As a result, when the error detection circuit 2 detects an error,
If MDF20 is "1", EIF21 is set,
If the MDF 20 is "0", the EVF 22 is set.

When EIF21 is set, DGP24
Error handling starts with. When the EVF 22 is set, the CPU-FW 25 generates the timing for starting the error processing, and then the EIF 21 is set,
Similar to the above, the DGP 24 starts error processing. The difference between the case of using the EIF21 set and the case of using the EVF set affects the timing at which error processing is started, as will be described later. DGP24 directly via EIF21
If the error is notified to, the error handling can be started immediately. However, on the other hand, the timing may be such that the instruction being processed is interrupted, and in that case, the retry of the instruction from the time when the failure occurs may not be successful. On the other hand, when error processing is performed from the EVF 22 via the CPU-FW 25, the error processing can be started after waiting for the end of the instruction in the middle of the processing, so that the probability of successful retry of the instruction increases. Therefore, the method of starting these error processes should be set according to various situations of the information processing apparatus, and the MDF 20 is provided for this setting in this embodiment. The MDF 20 can be set when the system is started up, for example, by a scan path.

When an error of the arithmetic unit is reported from the error display flag 19, the EI is sent via the OR circuit 7.
F21 is set. This activates the error processing of the DGP 24. In this embodiment, the error from the error display flag 19 is reported to the EIF 21, but the error detection circuit 2 may use the firmware depending on the mode as in the case of the error detection circuit 2.

Next, the processing in the CPU-FW 25 will be described with reference to the drawings.

Referring to FIG. 2, the CPU-FW 25 is
A control store 54 that stores a microprogram, a control memory address register (CSAR) 51 that indicates a read position of the control store 54, and a control store instruction register (CSI) that holds read data from the control store 54.
R) 52 and. Further, a start address register (SAR) 50 for holding the start address of the error processing routine of the microprogram, a selector 55 for selecting the SAR 50 or the next address, and an AND circuit 56 for giving a control signal to the selector 55. Is included. The next address is an address designated by the microprogram in the control store 54, and generally means the address of the microprogram instruction executed next to the microprogram instruction currently being processed. Also, C
A signal is transferred to the signal lines 41, 44 and 46 by the micro program instruction read by the SIR 52.

Referring to FIG. 3, the instruction field of the microprogram stored in the control store 54 and read by the CSIR 52 is an OPC indicating a microinstruction code.
521, NEXT 522 indicating the next address, EOP 527 indicating the end of the machine language instruction level instruction, and CSVR
4 includes a CSVRE 528 for setting the error occurrence in CSV4 in the CSVREF 53, an EI 529 for setting the error occurrence in the EIF 21, and the like. NEXT
522 is input as one of the inputs of the selector 55.
The EOP 527 is transferred to the signal line 44 and the AND circuit 56
Is ANDed with the output 45 of the EVF 22.
The CSVRE 528 is connected to the CSVREF 5 via the signal line 46.
Used to set 3. The EI 529 is input to the OR circuit 7 via the signal line 41 and used to set the EIF 21.

Next, the error detection circuit 2 causes the CSVR 4
CPU-FW when an error is detected in
An example of operation in No. 25 will be described with reference to FIGS. 4 and 5.

Referring to FIG. 4, the error detected by the error detection circuit 2 in the first cycle is reported to the EVF 22. As a result, in the next second cycle, the EVF22
Output becomes active. However, since the EOP 527 is not active in this second cycle, that is, the machine language instruction level instruction is being processed, the start of the interrupt processing is delayed.

In the third cycle, since it is found that the EOP 527 becomes active and the machine language instruction level instruction is completed, the output of the AND circuit 56 selects the SAR 50 by the selector 55, so that an error occurs in the next fourth cycle. The process starts.

Referring to FIG. 5, as a procedure for error processing in the CPU-FW 25, the EVF 22 is first reset (step 72). This is to accept the next error. The reset of the EVF 22 is instructed in the fourth cycle, and the output of the EVF 22 becomes non-active in the next fifth cycle.

Then, CSVREF 53 indicating that an error has occurred in CSVR 4 is set (step 73),
The EIF 21 that activates the DGP 26 is set (step 74). These setting processes are simultaneously instructed in the fifth cycle, and both become active in the sixth cycle. E
When the IF 21 becomes active, the error processing in the DGP 24 is started (step 75).

Next, the procedure of error processing in the DGP 24 will be described with reference to the drawings.

Referring to FIG. 6, first, the DGP 24 is S
D, contents of VR3, CSVR4 and CSVREF53
It is saved in the GPM 26 (step 76). This evacuation is
For example, the scan path can be used. Further, when it is directly reported to the DGP 24 without going through the CPU-FW 25, the DGP 24 checks the CDRR 16 to detect the error of the CSVR 4. Below, CSVRE4 error detected in this way is also CSVRE
It is treated as being saved as F. After this evacuation, the DGP 24 resets the CPU once (step 77).

After the CPU is reset, if the value of CSVREF saved in the DGPM 26 is "1", it means that an error has occurred in the CSVR 4, so the DGPM 26
The contents of the SVR saved in the SVR3 and CSVR4
(Step 79). C saved in the DGPM 26
If the value of SVREF is "0", no error has occurred in CSVR4, so CS saved in DGPM26
The contents of VR are returned to SVR3 and CSVR4 (step 80). After these restorations are completed, the CPU is retried from the instruction at the time when the error occurred (step 81).

[0042]

As is apparent from the above description, according to the present invention, the CSV for saving the state of the SVR one clock before is stored.
By providing R, SV will be generated due to an error inside the CPU.
Even if erroneous data is overwritten in R, the instruction can be retried from the time when the error occurs, and high fault tolerance can be maintained especially against intermittent failures.
Furthermore, by providing a diagnostic processor, flexible error handling is possible.

Further, according to the present invention, the timing of activating the error processing can be adjusted, and the instruction can be retried after the reset. Further, by providing the CSVR error detection circuit, it is possible to specify the location where the error has occurred and retry from an appropriate state.

Further, according to the present invention, by providing a mode flag for setting whether to give priority to retry or priority to urgency, it is possible to operate according to the request of the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a failure recovery mechanism for explaining an embodiment of an information processing apparatus of the present invention.

FIG. 2 is a block diagram of CPU firmware.

FIG. 3 is a diagram showing a format of a micro instruction of CPU firmware.

FIG. 4 is a diagram showing a timing from error occurrence to error processing.

FIG. 5 is a flow chart of processing until CPU firmware calls a diagnostic processor for error processing.

FIG. 6 is a flowchart of error processing in the diagnostic processor.

[Explanation of symbols]

 1 Operation Circuit 2 Error Detection Circuit 3 Software Appearance Register (SVR) 4 Copy SVR (CSVR) 5 Error Detection Flag Group (EF) 6, 7 OR Circuit 8-10 AND Circuit 11 Write Address Register (WAR) 12 Write Data Register ( WDR) 13 copy WAR (CWAR) 14 copy WDR (CWDR) 15 CSVR read address register (CRAR) 16 CSVR read data register (CDRR) 17 write flag (WF) 18 copy WF (CWF) 19 error flag (EF) 20 mode Flag (MDF) 21 Error display flag (EIF) 22 Event flag (EVF) 23 Error detection circuit 24 Diagnostic processor (DGP) 25 CPU firmware (CPU-FW) 26 DGP memory (DGPM) 5 0 start address register (SAR) 51 control store address register (CSAR) 52 control store instruction register (CSIR) 53 CSVR error flag (CSVREF) 54 control store 521 instruction code field (OPC) 522 next address field (NEXT) 527 operation end Field (EOP) 528 CSVR error field (CSVRE) 529 Error display field (EI)

Claims (8)

[Claims] 1. An error recovery mechanism in an information processing apparatus having a central processing unit including a group of storage means made up of at least one word, the error recovery mechanism having the same configuration as the group of storage means. A group of preliminary storage means to which the data is written after a certain data is written to the means; an error detection means for detecting an error generated in the central processing unit; and an error notification from the error detection means Accordingly, the information processing apparatus includes: an error processing unit that performs error processing in the central processing unit and restores the central processing unit. 2. The error processing means analyzes the cause of an error in the central processing unit, saves the contents of the one group of storage means and the one group of preliminary storage means in a save area, and then the central processing unit. The information processing apparatus according to claim 1, further comprising: an error processing processor that resets the contents of the save area to the group of storage units and the group of preliminary storage units; 3. The error processing means makes preparations for error processing with respect to an error report from the error detection means, generates timing suitable for error recovery, and performs error processing on the error processing processor at that timing. 3. The information processing apparatus according to claim 2, further comprising: error processing firmware for starting. 4. The error detection means includes a preliminary storage error detection section that detects an error that has occurred in the group of preliminary storage means, and the error processing means includes that an error has occurred in the preliminary storage error detection section. And when the error processing processor restores the contents of the save area to the group of storage means and the group of spare storage means, the spare storage error flag is
If "error occurrence" is indicated, the contents of the save area relating to the one group of memory means are restored to the one group of memory means and the one group of spare memory means, and the reserve memory error flag indicates "error not occurred". 4. The information processing apparatus according to claim 3, wherein the contents of the save area relating to the group of preliminary storage units are restored to the group of storage units and the group of preliminary storage units. 5. The error processing means has one of a mode in which an error detected by the error detection means is directly notified to the error processing processor and a mode in which the error processing processor is activated via the error processing firmware. The information processing apparatus according to claim 3, further comprising a designated error processing mode flag. 6. The error detection means includes a preliminary storage error detection section that detects an error that has occurred in the group of preliminary storage means, and the error processing means includes that an error has occurred in the preliminary storage error detection section. And when the error processing processor restores the contents of the save area to the group of storage means and the group of spare storage means, the spare storage error flag is
If "error occurrence" is indicated, the contents of the save area relating to the one group of memory means are restored to the one group of memory means and the one group of spare memory means, and the reserve memory error flag indicates "error not occurred". 6. The information processing apparatus according to claim 5, wherein the contents of the save area relating to the group of preliminary storage units are restored to the group of storage units and the group of preliminary storage units. 7. The information processing apparatus according to claim 6, wherein the group of storage means is a group of registers, and the group of preliminary storage means is a group of backup registers. 8. The group of storage means is a group of registers visible to software.
The information processing device described.