JPH07218602A - Semiconductor tester - Google Patents

Abstract

PURPOSE:To shorten the time required for setting the test conditions when a large number of devices of same model are tested repetitively. CONSTITUTION:Test condition numbers and corresponding test condition data are stored in a memory 14. When devices of same model are tested, a test control unit 10 transfers an instruction 'Test under conditions (n)' to an instruction analytic circuit 13. The circuit 13 analyzes the instruction and designates a test condition number for the memory 14 thus reading out a test condition data therefrom. The test condition data controls a variable signal delay circuit. This constitution reduces the read/write operation of disc and the number of times for delivering an instruction from a test control unit to the instruction analytic unit thus shortening the time required for setting the test conditions while enhancing the efficiency of entire system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus which shortens the test condition setting time when a large number of devices of the same model are repeatedly tested.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional circuit block for setting test conditions. This circuit block includes a disk device 15 for storing test condition data and the like, a test control unit 10 for transferring a test condition instruction for transferring the test condition data to an instruction analysis circuit 13 via an inter-unit bus, and an instruction analysis unit. The circuit 13 includes an instruction analysis unit 11 that analyzes an instruction and writes test condition data to the register 12, and a register 12 that rewrites the test condition data for each test item.

As shown in FIG. 4, the test condition data written in the register 12 is relative to the set signal, the reset signal, the drive enable signal, the strobe H signal, and the strobe L signal transferred from the semiconductor test apparatus to the test head. It is used for adjusting the time relation between the signals, and controls the signal delay variable circuit 16 incorporated in each signal.

In the conventional circuit, when a large number of devices of the same model are repeatedly tested, it is necessary to transfer a test condition instruction for each test item from the test control unit 10 and rewrite the test condition data in the register 12 each time. Repeated testing of devices of the same model requires the same amount of time as testing devices of different models. Moreover, the test condition data is stored in the disk device 15 connected to the test control unit 10, and it is necessary to read the test condition data from the disk each time the test condition command is transferred to the command analysis unit 11. Therefore, it takes a lot of time to read from the disc.

[0005]

As described above, there is a drawback in that the test time is not shortened even though it is a repeated test of devices of the same model. It is an object of the present invention to shorten the test condition setting time when a large number of devices of the same model are repeatedly tested.

[0006]

[Means for Solving the Problems]

(Solution of claim 1) The test condition setting for setting the test condition data for setting the delay time is performed in order to adjust the relative time relationship of a plurality of signals transferred from the semiconductor test apparatus body to the test head by the signal delay variable circuit. In the circuit, a memory 14 is provided in the instruction analysis unit 11. Then, when a test condition setting instruction for which the test condition has not been set is transferred from the test control unit 10 to the instruction analysis circuit 13, the instruction analysis circuit 13 writes the test condition data in the register 12, and at the same time, the memory 14 Then, the same test condition data is stored with the test condition number added. When testing devices of the same model, the memory 14
Since the test condition number and the test condition data corresponding thereto are written in, the test control unit 10 may transfer the instruction “test under test condition n” to the instruction analysis circuit 13. The instruction analysis circuit 13 analyzes the instruction,
The test condition number is specified in the memory 14 to read the test condition data, and the test condition data is written in the register 12. The test condition data output from the register 12 controls the variable signal delay circuit 16.

(Solution to Claim 2) Since the relative time relationship of a plurality of signals transferred from the semiconductor test apparatus main body to the test head is adjusted by the signal delay variable circuit, test condition data for setting the delay time is set. In the test condition setting circuit, the register 12 is replaced with the memory 14. Then, when a test condition setting command that has not been set as the test condition is transferred from the test control unit 10 to the command analysis circuit 13, the command analysis circuit 13 causes the memory 14 to store the test condition number and the test condition corresponding thereto. Write the data. When testing devices of the same model, since the test condition number and the test condition data corresponding thereto are already written in the memory 14, the test control unit 10
May transfer the instruction “test under test condition n” to the instruction analysis circuit 13. The instruction analysis circuit 13 analyzes the instruction, specifies the test condition number in the memory 14, and reads the test condition data. The test condition data output from the memory 14 directly controls the variable signal delay circuit 16.

[0008]

The test condition setting circuit configured as described above is
It reduces the number of times data is read from and written to the disk device, and the number of times commands are issued from the test control unit to the instruction analysis unit, so the entire system can be used more for purposes other than setting test conditions. Has the effect of improving system efficiency.

[0009]

【Example】

(Embodiment 1) Referring to FIG. 1, an embodiment will be described in which the test condition setting time is shortened when a large number of devices of the same model are repeatedly tested. In this embodiment, a memory 14 for storing the same test condition data as the test condition data transferred to the register 12 is added in the instruction analysis unit 11. Then, the operation is performed as follows. The test control unit 10 transfers the test condition instruction of the test item 1 to the instruction analysis circuit 13 via the inter-unit bus. The instruction analysis circuit 13 writes the test condition data 1 to the register 12 and at the same time, sends a write signal and test condition number 1 to the memory 14 to write the test condition number and the test condition data corresponding thereto. When there are n test items, the same processing is performed, and the test condition 1, test condition 2, ... Test condition n and the test condition data corresponding thereto are written in the memory 14. When testing devices of the same model, since the test condition number and the test condition data corresponding thereto are written in the memory 14, the test control unit 10 only issues the command “test under test condition n” to the unit. Transfer to the instruction analysis circuit 13 via the inter-bus. The instruction analysis circuit 13 sends the read signal and the test condition number to the memory 14, and at the same time, sends the write signal to the register 12 to write the test condition data of the test condition n to the register 12.

As described above, two devices of the same model
In the subsequent tests, the test condition data is not transferred from the disk device 15 connected to the test control unit 10 to the instruction analysis circuit 13 via the inter-unit bus, and the test condition data is Under the control of the analysis circuit 13, the data is directly transferred from the memory 14 in the instruction analysis unit 11 to the register 12. Therefore, the register 12
The test condition setting time is shortened, and the test time can be shortened when a large number of devices of the same model are tested repeatedly.

(Embodiment 2) FIG. 2 shows another embodiment for shortening the test condition setting time when a large number of devices of the same model are repeatedly tested. In this embodiment, the register 12 is replaced with the memory 14. In this case, the operation is performed as follows. The test control unit 10 transfers the test condition instruction of the test item 1 to the instruction analysis circuit 13 via the inter-unit bus. The instruction analysis circuit 13 sends a write signal and test condition number 1 to the memory 14, and writes the test condition number and the test condition data corresponding thereto. When there are n test items, the same processing is performed, and the test condition 1,
Test condition 2, ... Test condition n and test condition data corresponding thereto are written. When testing devices of the same model, since the test condition number and the test condition data corresponding thereto are written in the memory 14, the test control unit 10 issues only the command “test under test condition n” to the unit. Transfer to the instruction analysis circuit 13 via the inter-bus. The instruction analysis circuit 13 sends a read signal and a test condition number to the memory 14 and selects data of the test condition n.

As described above, two devices of the same model
In the subsequent tests, the test condition data is not transferred from the disk device 15 connected to the test control unit 10 to the instruction analysis circuit 13 via the inter-unit bus, and the test condition data is Under the control of the analysis circuit 13, it is set only by designating the test condition number of the memory 14. Therefore, the test condition is not set in the register 12, the test condition data is specified only by setting the test condition number of the memory 14, the signal delay variable circuit 16 is controlled by the value, and a large number of devices of the same model are repeated. When testing, the test time can be shortened.

[0013]

As described above, when a large number of devices of the same model are repeatedly tested, the test condition data is not read from the disk after the second time, and the test condition is set in the variable signal delay circuit in a short time. This is an effective invention that can set data and shorten the time for setting test conditions.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of test condition setting according to the present invention.

FIG. 2 is another circuit block diagram for setting test conditions according to the present invention.

FIG. 3 is a circuit block diagram of conventional test condition setting.

FIG. 4 is a circuit block diagram for one test pin that controls a variable signal delay circuit with a register.

[Explanation of symbols]

 10 Test Control Unit 11 Instruction Analysis Unit 12 Register 13 Instruction Analysis Circuit 14 Memory 15 Disk Device 16 Signal Delay Variable Circuit

Claims (2)

[Claims] 1. A test condition setting circuit for setting test condition data for setting a delay time in order to adjust a relative time relationship of a plurality of signals transferred from a semiconductor test apparatus body to a test head by a signal delay variable circuit, Test control unit for generating test condition setting command (10)
And analyzing the instruction transferred from the test control unit (10) and writing the test condition data to the register (12),
An instruction analysis circuit (13) for controlling writing and reading of the test condition number and the corresponding test condition data to the memory (14); and a test condition number transferred by the instruction analysis circuit (13), The test condition data corresponding to it is stored, and the test condition data of the test condition number is read out in the test of the same number as the already stored test condition number.
A memory (14) for transferring to a register (12), a register (12) for outputting test condition data for setting a delay amount to a signal delay variable circuit (16) for determining a delay amount of a signal given to a test head, and above. A semiconductor test apparatus comprising: 2. A test condition setting circuit for setting test condition data for setting a delay time for adjusting a relative time relationship of a plurality of signals transferred from a semiconductor test apparatus body to a test head by a signal delay variable circuit, Test control unit for generating test condition setting command (10)
And an instruction analysis circuit (13) which analyzes the instruction transferred from the test control unit (10) and controls writing and reading of the test condition number and the corresponding test condition data to the memory (14), The test condition number transferred by the instruction analysis circuit (13) and the test condition data corresponding thereto are stored, and the test condition data of the test condition number is stored in the test of the same number as the already stored test condition number. A semiconductor test apparatus comprising: a memory (14) provided to a signal delay variable circuit (16) that determines a delay amount of a signal provided to a test head; and the above.