JPH0721775B2 - Memory write control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory write control circuit for a random access memory in a device such as a computer that requires a random access memory.

[Conventional technology]

Fig. 4 shows the conventional memory writing shown in the block diagram of the PCA8506A module of "'86 Mitsubishi semiconductor data block board computer edition" (published on April 20, 1986, Semiconductor Business Division, Mitsubishi Electric Corporation). It is a block diagram showing a control circuit, 1 is a system bus connected to a CPU device such as a central processing unit or an IO control device, 2 is an address buffer for inputting an address signal included in the system bus 1 to a memory circuit. An address decoder 3 detects whether or not the memory module is selected by decoding the upper part of the address signal and generates a selection signal (hereinafter referred to as a CS signal) for each memory element. A data buffer consisting of a bidirectional buffer and having a data bus buffer function between the system bus 1 and a memory. A buffer IC for inputting a read command (MRDCL) and a memory write command (MWTCL) to the memory module, and 7 is composed of one or a plurality of random access memory elements (hereinafter referred to as RAM elements). A memory bank (hereinafter referred to as RAM).

Next, the operation will be described. Here, FIG. 5 is a time chart showing the time relationship of each signal for explaining the operation. The CPU device connected to the system bus 1 first outputs an address signal (ADRSL) for selecting a memory and write data (DATAL) on the system bus 1. The memory module inputs the address signal (ADRSL) from the address buffer 2 and outputs the upper address signal to the address decoder 3. The address decoder 3 detects whether or not this memory module is selected by an internal address matching detection logic, and if selected, sets the data buffer 4 to the output enable side, and when it is selected,
Make the signal significant. After that, the CPU device makes the memory write instruction (MWTCL) significant and outputs it to the system bus 1.
When the memory write instruction (MWTCL) becomes significant, the buffer IC6
The write control signal (WR) output from becomes significant and data writing to the RAM 7 starts. After the CPU device satisfies timing conditions such as the pulse width condition of the write control signal (WR) to RAM7, the access time, etc., the memory write command (MWTC
L) to the unwilling side. As a result, the output (WR) of the buffer IC6 also becomes insignificant, and after that, after satisfying the data for the RAM7, the set-up time of the address, the hold time, etc., the address signal (ADRSL), the data signal (DAT)
The output of (AL) is stopped, the CS signal becomes insignificant, and the series of writing operations to the memory ends.

[Problems to be solved by the invention]

Since the conventional memory write control circuit is configured as described above, the CPU device during data writing has a hardware reset, or software for resetting all CPU devices at the same time via the system bus 1. When an automatic reset occurs, the address signal (ADRS
L) Write data (DATAL) and memory write command (MWTCL) become invalid on the way, and the timing conditions for the RAM element of RAM7 are not satisfied, so incorrect data is written and the memory contents are destroyed. There is a problem that the use of hardware reset and software reset is strictly impossible.

The present invention has been made in order to solve the above-mentioned problems, and during write operation to the memory, even if the memory write instruction disappears halfway, the correct write data is initially selected at the memory address. The purpose is to obtain a memory write control circuit capable of writing to.

[Means for solving problems]

A memory write control circuit according to the present invention includes a flip-flop that stores that a memory write instruction is significant and that a memory is selected, and a valid address signal when the memory write instruction becomes significant. A latch circuit that latches the write data is provided, and two types of timer circuits that operate when the flip-flop becomes significant are also provided. As a result, the timing that satisfies the timing conditions for the RAM element of RAM is internally It was created.

[Action]

The memory write control circuit according to the present invention latches the write data and the address signal at the time of writing, and internally generates the timing satisfying the timing condition for the RAM element of the RAM, so that the memory write instruction is executed. Even if it ends abnormally,
The write data is accurately written in the memory address originally selected.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, reference numeral 1 is a system bus, 3 is an address decoder, 5 and 6 are buffer ICs, and 7 is a RAM, which are the same as or equivalent to those of the conventional ones shown in FIG. Is omitted. Further, 8 is an address latch circuit which is in a latch state during a write operation and is in a through state in other cases, 9 is a data latch circuit which latches write data, and 10 outputs read data to the system bus 1. Output data buffer, 11 is a gate that generates an output enable signal of the output data buffer 10 at the time of reading data, 12 is an inverter that outputs a high level signal (hereinafter referred to as “H”) when the memory module is selected, and 13 is a memory module. A flip-flop of D type that makes the output signal significant by the selection of the Yule and the memory write command becoming significant, and 14 outputs the write control signal to the memory for a certain time when the flip-flop 13 becomes significant. do it,
A first timer circuit 15 for generating a pulse width of a memory write command outputs a reset signal after a lapse of a fixed time after the output signal of the first timer circuit 14 becomes insignificant, and creates a reset timing for the flip-flop 13. It is a second timer circuit.

Next, the operation will be described. Here, FIG. 2 is a time chart showing the time relationship of each signal for explaining the operation. It is connected to the system bus 1.

When starting writing to the memory, the CPU device makes the address signal (ADRSL) and the write data (DATAL) significant and outputs them on the system bus 1. First, the address latch circuit 8 is in the through state, inverts the address signal (ADRSL) on the system bus 1, and outputs it as an address signal (ADRS) in the memory module. Address decoder 3
Decodes its upper address signal (ADRS),
It is detected whether or not the module is selected, and if they match, a low level signal (hereinafter referred to as “L”) is output to the gate 11 and the inverter 12, and also to the RAM 7.
Output the CS signal and select the RAM element to write the data. After that, the CPU device makes the memory write instruction (MWTCL) significant and outputs it on the system bus. The buffer IC 6 outputs the memory write command (MWTCL) into the module. The flip-flop 13 inputs the output of the inverter 12 which becomes "H" when the module is selected to the D terminal, samples it at the falling edge of the memory write command (MWTCL), and when the module is selected. The "1" terminal output signal (F
・ F ・) is made significant. Also, this flip-flop
The "0" terminal output signal (FF) of 13 is input to the latch enable terminal (LE) of the address latch circuit 8, the output enable terminal (OE) and the latch enable terminal (LE) of the data latch 9. When the "0" terminal output signal (FF) of the flip-flop 13 becomes "L", the address latch circuit 8 latches the address signal (ADRSL), and the data latch circuit 9 latches the write data (DATAL). At the same time, the inverted data of the write data (DATAL) is output to the RAM 7. On the other hand, the first timer circuit 14 causes the write control signal (WR) to the RAM 7 to be significant ("L") at the same time that the "1" terminal output signal (FFQ) of the flip-flop 13 becomes "H". Then, the state is continued for a predetermined time t ₁ . After the lapse of t ₁ time that satisfies timing conditions such as the pulse width of the memory write command to RAM 7 and the access time, the first timer circuit 14 turns off the write control signal (WR) to RAM 7 (“H”). Side). Second timer circuit 15
Starts the operation from the rising edge where the write control signal (WR) becomes insignificant, and the address signal (ADRSL) to RAM7,
Time t ₂ that satisfies the hold time of write data (DATAL)
When is passed, the reset signal is output to the flip-flop 13. The reset signal causes the flip-flop 13 to be reset, releasing the latched state of the address latch circuit 8 and the data latch circuit 9 and, at the same time, setting the output enable terminal OE of the data latch circuit 9 to the inhibit side and ending a single write operation.

Next, if a reset pulse is input during the write operation, write data (DATAL) and address signal (A
Although the DRSL) and the memory write command (MWTCL) are ineffective as shown by the broken line in FIG. 2, the address signal and write data in the memory module are the same as the address latch circuit 8 and the data latch as described above. Since it is latched by the circuit 9, it is stable thereafter. Further, the write control signal (WR) for the RAM 7 is also stable because it is generated by the first timer circuit 14.

Therefore, due to the reset, even if the write operation from the CPU device ends abnormally, the internal circuit is not affected. Therefore, write the correct write data correctly to the originally selected memory address. Is possible.

In the above embodiment, the D flip-flop is used as the flip-flop 13 for detecting that the memory write command becomes significant, but the address signal and the write data are valid as the system bus timing condition. After that, if the memory write command becomes significant almost at the same time, as shown in FIG. 3, among the outputs of the address decode 3, the signal which becomes “L” when the module is selected and the output signal of the buffer 6 are shown. When both gates go to "L", a gate 16 that outputs "H" is provided, the output is connected to the J terminal, and the K terminal is always connected to "L". J ・ K type flip-flop 17
The output signal of the "1" terminal is (F, F, Q), "0"
The terminal output signal may be (F · F ·). In this case, a clock source 18 for operating the JK type flip-flop is required. Also in this method, the operation after the output of the flip-flop 17 becomes significant once is the same as that in the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, the write data and the address signal at the time of writing are latched, and the timing that satisfies the timing condition for the RAM element of the RAM is internally generated. Even if the write operation from the memory is abnormally terminated due to resetting, normal write data can be correctly written to the originally selected memory address, increasing the reliability of the device and improving This has the effect of relaxing restrictions on resets in the SETA system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory write control circuit according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation thereof, and FIG. 3 is a flip-flop and another embodiment of the present invention. FIG. 4 is a block diagram showing a peripheral portion, FIG. 4 is a block diagram showing a conventional memory write control circuit, and FIG. 5 is a time chart for explaining its operation. 1 is a system bus, 8 is an address latch circuit (latch circuit), 7 is RAM, 9 is a data latch circuit (latch circuit), 13 and 17 are flip-flops, 14 is a first timer circuit, and 15 is a second timer circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A flip-flop for storing that a memory write command is input from the system bus, and a latch for latching an address signal and write data input from the system bus while the output signal of the flip-flop is significant. A circuit, a first timer circuit for outputting a write control signal to the memory for a fixed time when the flip-flop becomes significant, and a flip-flop for a fixed time after the output signal of the first timer circuit becomes insignificant. A memory write control circuit including a second timer circuit that outputs a reset signal.