JPH07211814A - Surface mount semiconductor package and mother board mounting method of surface mount semiconductor package - Google Patents
Surface mount semiconductor package and mother board mounting method of surface mount semiconductor packageInfo
- Publication number
- JPH07211814A JPH07211814A JP667794A JP667794A JPH07211814A JP H07211814 A JPH07211814 A JP H07211814A JP 667794 A JP667794 A JP 667794A JP 667794 A JP667794 A JP 667794A JP H07211814 A JPH07211814 A JP H07211814A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- external connection
- mounting
- pads
- surface mount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims description 6
- 238000005476 soldering Methods 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 15
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- -1 or the like Substances 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、表面実装用半導体パッ
ケージと、該表面実装用半導体パッケージをマザーボー
ドへ実装する実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mounting semiconductor package and a mounting method for mounting the surface mounting semiconductor package on a mother board.
【0002】[0002]
【従来の技術】従来、電子機器に使用されている半導体
パッケージ、とくにリードレス半導体パッケージには、
リードレスチップキャリア(以下、LCC)等がある。
LCCの一例を示すと、図5の斜視図に示す如く、セラ
ミック基板、またはプラスチック基板等の四つの側面す
べてに電極パッド(8)を設け、該基板(1)の上面の
中央部には半導体チップを搭載する凹部(9)を穿設
し、凹部(9)の周囲には上記電極パッド(8)と半導
体チップとを連結するための回路パターン(3)が形成
されたリードのない表面実装型パッケージである。ま
た、図6は、上記LCCをマザーボードとなるプリント
配線板に実装したときの一部破断拡大斜視図で、実装す
るプリント配線板(4)の上面に形成された外部接続用
パッド(5)にLCCの側面に形成された電極パッド
(8)が対向し、リフロー半田付けによりプリント配線
板(4)の外部接続用パッド(5)と接続を行い、LC
Cの上面の回路パターン(3)、電極パッド(5)、外
部接続用パッド(5)と一連の導通回路を形成する。し
かしながら、上記LCCにおいては、電極パッド(5)
が半円筒状に形成されるため、加工時の裁断により発生
したストレスに起因した、電極パッド(5)のメッキ剥
がれや亀裂が生じたり、半田上げが充分であったりし
て、導通不良が起こるといった問題がある。2. Description of the Related Art Conventionally, semiconductor packages used in electronic equipment, especially leadless semiconductor packages, are
There are leadless chip carriers (hereinafter, LCC) and the like.
As an example of the LCC, as shown in the perspective view of FIG. 5, electrode pads (8) are provided on all four side surfaces of a ceramic substrate, a plastic substrate, or the like, and a semiconductor is provided at the center of the upper surface of the substrate (1). A leadless surface mount in which a recess (9) for mounting a chip is formed and a circuit pattern (3) for connecting the electrode pad (8) and the semiconductor chip is formed around the recess (9). It is a type package. FIG. 6 is a partially cutaway enlarged perspective view of the above LCC mounted on a printed wiring board serving as a mother board, showing the external connection pads (5) formed on the upper surface of the printed wiring board (4) to be mounted. The electrode pads (8) formed on the side surfaces of the LCC are opposed to each other and are connected to the external connection pads (5) of the printed wiring board (4) by reflow soldering.
A series of conductive circuits are formed with the circuit pattern (3) on the upper surface of C, the electrode pad (5), and the external connection pad (5). However, in the above LCC, the electrode pad (5)
Is formed into a semi-cylindrical shape, and therefore, the peeling or cracking of the plating of the electrode pad (5) occurs due to the stress generated by cutting during processing, and the soldering is sufficient, resulting in poor conduction. There is such a problem.
【0003】[0003]
【発明が解決しようとする課題】本発明は上記の事情に
鑑みてなされたものであり、その目的とするところは、
この表面実装用半導体パッケージをプリント配線板等か
らなるマザーボードに搭載して用いる場合、該表面実装
用半導体パッケージの外部接続用パッドとマザーボード
上の外部接続用パッドの半田付けによる接続を確実に
し、一連の導通回路の信頼性の向上を図ることができる
表面実装用半導体パッケージ、及び該表面実装用半導体
パッケージを用いてマザーボードに実装する、表面実装
用半導体パッケージの電気的接続の信頼性が高い実装方
法を提供することにある。The present invention has been made in view of the above circumstances, and its object is to:
When this surface-mounting semiconductor package is mounted on a mother board such as a printed wiring board and used, the external connection pad of the surface-mounting semiconductor package and the external connection pad on the mother board are securely connected by soldering, Surface mounting semiconductor package capable of improving the reliability of the conduction circuit of the same, and a mounting method with high reliability of electrical connection of the surface mounting semiconductor package, which is mounted on a mother board using the surface mounting semiconductor package. To provide.
【0004】[0004]
【課題を解決するための手段】本発明の請求項1に係る
表面実装用半導体パッケージは、表面に半導体チップを
搭載し、この半導体チップと接続する回路パターン
(3)、裏面に外部接続用パッド(6)、この外部接続
用パッド(6)内に表面の回路パターン(3)と導通す
るスルーホール導電路を(2)を形成したことを特徴と
する。A semiconductor package for surface mounting according to claim 1 of the present invention has a semiconductor chip mounted on the front surface, a circuit pattern (3) for connecting to the semiconductor chip, and a pad for external connection on the back surface. (6) In the external connection pad (6), a through-hole conductive path (2) that is electrically connected to the circuit pattern (3) on the surface is formed (2).
【0005】また、請求項2に係る表面実装用半導体の
マザーボード実装方法は、請求項1記載の表面実装用半
導体パッケージをマザーボードに実装する際に、互いの
外部接続用パッド(6)(5)を一致させ、スルーホー
ル導電路(2)内に半田上げすることにより互いの回路
を接続し、表面実装用半導体パッケージ(1)をマザー
ボードに実装することを特徴とする。According to a second aspect of the present invention, there is provided a method for mounting a surface-mounting semiconductor on a mother board, wherein when mounting the surface-mounting semiconductor package according to the first aspect on a mother board, pads (6) (5) for external connection to each other. Are matched and soldered into the through-hole conductive path (2) to connect the circuits to each other, and the surface mounting semiconductor package (1) is mounted on the motherboard.
【0006】[0006]
【作用】本発明に係る表面実装用半導体パッケージによ
ると、表面実装用半導体パッケージ(1)の表面に形成
された回路パターン(3)と裏面に形成された外部接続
用パッド(6)がスルーホール導電路(2)により導通
しているので、表面実装用半導体パッケージ(1)を実
装するプリント配線板(4)等とリフローにより半田付
けした際に、周囲が閉塞されているためスルーホール導
電路(2)の開孔部より内壁に向かい毛細管現象の如く
半田上がりが生じる。半田上がりが生じることにより、
表面実装用半導体パッケージ(1)とプリント配線板
(4)との接続を確実なものとすることができる。According to the surface mounting semiconductor package of the present invention, the circuit pattern (3) formed on the surface of the surface mounting semiconductor package (1) and the external connection pad (6) formed on the back surface are through holes. Since it is conducted by the conductive path (2), when soldered to the printed wiring board (4) or the like on which the semiconductor package for surface mounting (1) is mounted by reflow soldering, the surroundings are closed and the through hole conductive path is formed. Solder rises from the opening of (2) toward the inner wall like a capillary phenomenon. Due to solder rise,
It is possible to secure the connection between the surface-mounting semiconductor package (1) and the printed wiring board (4).
【0007】以下、本発明を添付した図面に沿って詳細
に説明する。Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【0008】[0008]
【実施例】図1は本発明の一実施例に係る表面実装用半
導体パッケージの斜視図である。図2は本発明の一実施
例に係る表面実装用半導体パッケージをマザーボードと
なるプリント配線板に実装したときの一部破断拡大図で
ある。1 is a perspective view of a surface-mounting semiconductor package according to an embodiment of the present invention. FIG. 2 is a partially cutaway enlarged view of a semiconductor package for surface mounting according to an embodiment of the present invention, which is mounted on a printed wiring board serving as a mother board.
【0009】本発明の表面実装用半導体パッケージを構
成する基板(1)の表面には、図1に示すごとく、表面
の中央部を座ぐって形成された半導体チップを搭載する
凹部(9)と、回路パターン(3)を備え、この回路パ
ターン(3)は、該基板(1)の表面に配設された金属
箔をエッチングして形成された回路パターン、その他金
属メッキで形成した回路など、とくに制限はなく、凹部
(9)に搭載された半導体チップと接続される。また、
基板(1)の表面の半導体チップを搭載する凹部(9)
は、半導体チップを搭載できればとくにその形状、製法
は限定しない。As shown in FIG. 1, on the surface of the substrate (1) constituting the surface-mounting semiconductor package of the present invention, a recess (9) for mounting a semiconductor chip is formed by boring the central portion of the surface, A circuit pattern (3) is provided, and the circuit pattern (3) is formed by etching a metal foil provided on the surface of the substrate (1), or a circuit formed by other metal plating. There is no limitation, and the semiconductor chip mounted in the recess (9) is connected. Also,
A recess (9) for mounting a semiconductor chip on the surface of the substrate (1)
The shape and manufacturing method of the semiconductor are not particularly limited as long as the semiconductor chip can be mounted.
【0010】上記表面実装用半導体パッケージを構成す
る基板(1)としては、基材に樹脂ワニスを含浸し乾燥
して得られるプリプレグを重ね合わせ、加熱加圧成形し
て樹脂を硬化した絶縁樹脂基板、またはアルミナ等のセ
ラミック系の絶縁基板が用いられる。この絶縁樹脂基板
の基材としては、特に限定するものではないが、ガラス
繊維やアラミド繊維等の無機材料の方が耐熱性、耐湿性
などに優れて好ましい。また、耐熱性に優れる有機繊維
の布やこれらの混合物を基材として用いることもでき
る。上記基材に含浸する樹脂ワニスとしては、エポキシ
樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、
ポリエステル樹脂、ポリフェニレンオキサイド樹脂等の
単独、変性物、混合物等が用いられる。As the substrate (1) constituting the above-mentioned semiconductor package for surface mounting, an insulating resin substrate obtained by superposing a prepreg obtained by impregnating a base material with a resin varnish and drying, heat-pressing and curing the resin is applied. Alternatively, a ceramic insulating substrate such as alumina is used. The base material of the insulating resin substrate is not particularly limited, but an inorganic material such as glass fiber or aramid fiber is preferable because it is excellent in heat resistance and moisture resistance. Also, a cloth of organic fibers having excellent heat resistance or a mixture thereof can be used as a substrate. The resin varnish impregnating the base material, epoxy resin, polyimide resin, fluororesin, phenol resin,
Polyester resin, polyphenylene oxide resin, etc. may be used alone, modified, or a mixture.
【0011】上記基板(1)はスルーホール導電路
(2)を有する。このスルーホール導電路(2)は、上
面の回路パターン(3)と下面の外部接続用パッド
(6)を接続するために形成されたものであり、上面の
回路パターン(3)の一部は、半導体チップとワイヤー
ボンディングにより接続され、他の一部は、スルーホー
ル導電路(2)の開孔部に接続されて、一連の導通回路
を形成する。The substrate (1) has a through-hole conductive path (2). The through-hole conductive path (2) is formed to connect the circuit pattern (3) on the upper surface and the external connection pad (6) on the lower surface, and a part of the circuit pattern (3) on the upper surface is formed. , The semiconductor chip is connected by wire bonding, and the other part is connected to the opening of the through-hole conductive path (2) to form a series of conductive circuits.
【0012】上記外部接続用パッド(6)は、図3に示
すごとく、表面実装用半導体パッケージを構成する上記
基板(1)の下面に形成され、基板(1)の上面より貫
通するスルーホール導電路(2)の開孔部を有する。図
3においては、外部接続用パッド(6)は長方形のもの
を開示したが、形状や大きさは特に限定するものではな
く、半導体パッケージを実装するプリント配線板(4)
の外部接続用パッド(5)に応じて変わるもので、その
内部にスルーホール導電路(2)の開孔部を有するもの
であれば、円形や多角形のものでもよい。As shown in FIG. 3, the external connection pad (6) is formed on the lower surface of the substrate (1) constituting the surface mounting semiconductor package and is a through-hole conductive material penetrating from the upper surface of the substrate (1). It has an opening for the passage (2). In FIG. 3, the external connection pad (6) is disclosed as being rectangular, but the shape and size are not particularly limited, and a printed wiring board (4) for mounting a semiconductor package is provided.
The shape may vary depending on the external connection pad (5), and may be circular or polygonal as long as it has an opening for the through-hole conductive path (2) therein.
【0013】次に、上記表面実装用半導体パッケージを
プリント配線板に搭載して、実装する方法を説明する。Next, a method for mounting and mounting the above surface mounting semiconductor package on a printed wiring board will be described.
【0014】上記で説明した図1に示す表面実装用半導
体パッケージを、該表面実装用半導体パッケージの裏面
に形成された外部接続用パッド(6)と、実装するプリ
ント配線板(4)の上面に形成された外部接続用パッド
(5)が互いに一致するよう、プリント配線板(4)の
上面に配し、リフロー半田付けにより表面実装用半導体
パッケージとプリント配線板(4)を接続する。リフロ
ー半田付けを行った表面実装用半導体パッケージの状態
は、接続されている外部接続用パッド(6)の部分を断
面図として表すと、図4に示す如く、プリント配線板
(4)の外部接続用パッド(6)から表面実装用半導体
パッケージの外部接続用パッド(5)の間に半田の架橋
(7)が形成され、一部の半田が、スルーホール導電路
(2)の下部の開孔部より、スルーホール導電路(2)
の内壁に沿って上部の開孔部に向かって半田上がりが生
じる。この半田上がりは、従来のLCCに比べ非常に勝
るもので、その理由は、従来のLCCの外部接続用パッ
ドは半円筒状の電極パッドであり、本発明におけるスル
ーホール導電路(2)は周囲が閉塞されているために、
毛細管現象が著しく起こるためである。The surface mounting semiconductor package shown in FIG. 1 described above is formed on the external connection pad (6) formed on the back surface of the surface mounting semiconductor package and on the upper surface of the printed wiring board (4) to be mounted. The formed external connection pads (5) are arranged on the upper surface of the printed wiring board (4) so that they coincide with each other, and the surface mounting semiconductor package and the printed wiring board (4) are connected by reflow soldering. The state of the surface-mounting semiconductor package that has been subjected to the reflow soldering is shown in a sectional view of the connected external connection pad (6). As shown in FIG. 4, the external connection of the printed wiring board (4) is performed. A solder bridge (7) is formed between the pad (6) for external connection and the pad (5) for external connection of the surface mounting semiconductor package, and a part of the solder is opened at the bottom of the through-hole conductive path (2). From the part, through-hole conductive path (2)
Solder rises along the inner wall of the metal toward the upper opening. This solder rise is much superior to that of the conventional LCC, because the external connection pads of the conventional LCC are semi-cylindrical electrode pads, and the through-hole conductive path (2) in the present invention is surrounded by the surrounding area. Is blocked,
This is because the capillary phenomenon remarkably occurs.
【0015】上述のごとく、本発明に係る表面実装用半
導体パッケージは、基板(1)の表面の回路パターン
(3)より、裏面に形成された外部接続用パッド(6)
に対し、この外部接続用パッド(6)内にスルーホール
導電路(2)が貫通して形成されているので、該表面実
装用半導体パッケージを搭載するプリント配線板(4)
に対して、表面実装用半導体パッケージを正確な位置に
配し、半田上げすることにより確実に接続し、実装する
ことができる。As described above, in the surface mounting semiconductor package according to the present invention, the external connection pad (6) formed on the back surface of the circuit pattern (3) on the surface of the substrate (1).
On the other hand, since the through-hole conductive path (2) is formed so as to penetrate through the external connection pad (6), the printed wiring board (4) on which the surface mounting semiconductor package is mounted is mounted.
On the other hand, the surface-mounting semiconductor package can be placed at an accurate position and soldered to surely connect and mount it.
【0016】[0016]
【発明の効果】以上、述べたように、本発明の表面実装
用半導体パッケージによると、リードレスチップキャリ
アのごとく、半導体パッケージを半裁加工することがな
いのでスルーホールの壁面のメッキの剥がれや亀裂とい
った問題が発生することがない表面実装用半導体パッケ
ージを供給することができ、また、プリント配線板等の
マザーボードに実装する際には、該表面実装用半導体パ
ッケージとプリント配線板等の外部接続用パッドを接続
するためにリフロ半田付けを行うと、該表面実装用半導
体パッケージに形成されたスルーホール導電路の内壁に
半田上げを確認することができ、物理的接続と電気的接
続に高い信頼性を得ることができる。As described above, according to the semiconductor package for surface mounting of the present invention, unlike the leadless chip carrier, the semiconductor package is not half-cut, so that the plating on the wall surface of the through hole is peeled off or cracked. It is possible to supply a surface-mounting semiconductor package that does not cause such a problem, and when mounting on a mother board such as a printed wiring board, the surface-mounting semiconductor package and the printed wiring board are used for external connection. When reflow soldering is performed to connect the pads, soldering can be confirmed on the inner wall of the through-hole conductive path formed in the surface-mounting semiconductor package, and the physical and electrical connections have high reliability. Can be obtained.
【図1】本発明に係る一実施例の表面実装用半導体パッ
ケージの斜視図である。FIG. 1 is a perspective view of a surface-mounting semiconductor package according to an embodiment of the present invention.
【図2】本発明に係る一実施例の表面実装用半導体パッ
ケージをプリント配線板に実装した一部破断拡大図であ
る。FIG. 2 is a partially cutaway enlarged view of a surface mounting semiconductor package according to an embodiment of the present invention mounted on a printed wiring board.
【図3】本発明に係る一実施例の表面実装用半導体パッ
ケージの下面の一部破断拡大図である。FIG. 3 is a partially cutaway enlarged view of the lower surface of the surface-mounting semiconductor package according to an embodiment of the present invention.
【図4】本発明に係る一実施例の表面実装用半導体パッ
ケージのスルーホール導電路の断面図である。FIG. 4 is a cross-sectional view of a through-hole conductive path of a surface mount semiconductor package according to an embodiment of the present invention.
【図5】従来例の表面実装用半導体パッケージの斜視図
である。FIG. 5 is a perspective view of a conventional surface mounting semiconductor package.
【図6】従来例の表面実装用半導体パッケージをプリン
ト配線板に実装した一部破断拡大図である。FIG. 6 is a partially cutaway enlarged view of a conventional surface mounting semiconductor package mounted on a printed wiring board.
1 基板 2 スルーホール導電路 3 回路パターン 4 プリント配線板 5 外部接続用パッド 6 外部接続用パッド 7 半田の架橋 8 電極パッド 9 凹部 1 Board 2 Through Hole Conductive Path 3 Circuit Pattern 4 Printed Wiring Board 5 Pad for External Connection 6 Pad for External Connection 7 Bridge of Solder 8 Electrode Pad 9 Recess
Claims (2)
体チップと接続する回路パターン、裏面に外部接続用パ
ッド、この外部接続用パッド内に表面の回路パターンと
導通するスルーホール導電路を形成したことを特徴とす
る表面実装用半導体パッケージ。1. A semiconductor chip is mounted on the front surface, a circuit pattern for connecting to the semiconductor chip is formed, an external connection pad is formed on the back surface, and a through-hole conductive path for conducting the circuit pattern on the front surface is formed in the external connection pad. A semiconductor package for surface mounting, which is characterized in that
ージをマザーボードに実装する際に、互いの外部接続用
パッドを一致させ、スルーホール導電路内に半田上げす
ることにより互いの回路を接続し、表面実装用半導体パ
ッケージをマザーボードに実装することを特徴とする表
面実装用半導体パッケージのマザーボード実装方法。2. When mounting the semiconductor package for surface mounting according to claim 1 on a mother board, pads for external connection are made to coincide with each other and soldered into the through-hole conductive paths to connect the circuits to each other. A method for mounting a surface-mounting semiconductor package on a motherboard, wherein the surface-mounting semiconductor package is mounted on a motherboard.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667794A JPH07211814A (en) | 1994-01-25 | 1994-01-25 | Surface mount semiconductor package and mother board mounting method of surface mount semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP667794A JPH07211814A (en) | 1994-01-25 | 1994-01-25 | Surface mount semiconductor package and mother board mounting method of surface mount semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07211814A true JPH07211814A (en) | 1995-08-11 |
Family
ID=11645001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP667794A Withdrawn JPH07211814A (en) | 1994-01-25 | 1994-01-25 | Surface mount semiconductor package and mother board mounting method of surface mount semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07211814A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002080268A1 (en) * | 2001-03-30 | 2002-10-10 | Infineon Technologies Ag | A substrate for mounting a semiconductor chip |
US7615707B2 (en) | 2005-02-04 | 2009-11-10 | Lite-On Technology Corp. | Printed circuit board and forming method thereof |
-
1994
- 1994-01-25 JP JP667794A patent/JPH07211814A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002080268A1 (en) * | 2001-03-30 | 2002-10-10 | Infineon Technologies Ag | A substrate for mounting a semiconductor chip |
US7294853B2 (en) | 2001-03-30 | 2007-11-13 | Infineon Technologies, A.G. | Substrate for mounting a semiconductor |
US7615707B2 (en) | 2005-02-04 | 2009-11-10 | Lite-On Technology Corp. | Printed circuit board and forming method thereof |
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Legal Events
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A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010403 |