JPH07202962A - Modulator - Google Patents

Abstract

PURPOSE:To settle an excessive modulation circuit dynamic range, which is generated by synthesizing channel signals on the side of a base station, into the originally required irreducibly sufficient modulation circuit dynamic range only by adding any extremely simple circuit without damaging basic performance at a multiplex system. CONSTITUTION:At a transmission system, channel recognition codes are added to base band signals 1, 2,..., (n) by channel recognition encoders 4-6. These outputs are divided into the I and Q of orthogonal components by an orthogonally modulated I/Q divider 7, applied to respective D/A converters 8 and 9 and turned to the analog signals of multiplexed I and Q signals. These analog outputs are compressed by non-linear compressing circuits 30 and 31 corresponding to the levels of respective analog inputs, multiplied by orthogonal modulating multipliers 11 and 13 for I and Q signals, added by an adder 14 for orthogonal modulation and outputted through a BPF 15 and a transmission output amplifier 16 to a propagation path 17. Namely, power is applied to a channel multiplexed base band signal corresponding to the number of channels which voltage amplitudes are compressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device having a base station for a plurality of terminal stations, such as a mobile telephone installed in a public wireless telephone, an automobile or the like, or a modulator used in a communication network by optical communication. Is.

[0002]

2. Description of the Related Art In a base station communication device, for example, which needs to combine and transmit a plurality of communication channels using the same frequency band, conventionally, a method of adding individual voltage signals is generally used as shown in FIG. It was target.

FIG. 13 shows a system configuration diagram of a transmission system and a reception system in a conventional base station communication device.

The system configuration example shown in FIG. 13 deals with the case where QPSK, that is, four-phase modulation is used for code transmission. QPSK is a serial baseband signal in the base band converted into two series of orthogonal signals and is composed of parallel 2-bit signals. By making them parallel, the transmission rate can be halved without changing the base frequency bandwidth, and it is easy to detect the influence of external noise that interferes almost simultaneously, that is, it is easy to eliminate the influence of external noise. It has many advantages.

In FIG. 13, in the transmission system (I), the signals of a plurality of channels, that is, the baseband signal 1 (1), the baseband signal 2 (2), ..., The baseband signal n (3) correspond to each other. Channel recognition encoders 4, 5, ..., 6 to receive a channel recognition code. Each output receiving the addition of the channel recognition code is a quadrature modulation I / Q divider 7
Is divided into I and Q of quadrature component by and added to I signal digital-analog converter (D / A) 8 and Q signal digital-analog converter (D / A) 9 and multiplexed I and Q signals It becomes the analog signal of. The combined signals are respectively multiplied by the quadrature modulation reference carrier signal 10. That is,
On the I signal side, a quadrature modulation multiplier for I signal 11 is used. On the Q signal side, a phase shifter 12 gives a quadrature modulation reference carrier signal 10 with a phase difference of 90 degrees.
Is multiplied by.

These multiplication outputs are added by the quadrature modulation adder 14
Is added to the transmission output amplifier 16 through the band pass filter (BPF) 15 and the output is sent to the receiving system side. The transmitted signal reaches the reception system (II) through the propagation path 17 in the air or a cable, and is multiplied by the orthogonal demodulation reference carrier signal 18 for orthogonal demodulation. On the I signal side, the I signal orthogonal demodulation multiplier 19
On the Q signal side, the phase shifter 20 gives a phase difference of 90 degrees to the Q signal quadrature demodulation multiplier 21.

Thus, the demodulated signals that have undergone the quadrature demodulation pass through the low pass filters (LPF) 22 and 23, respectively, and the I signal and Q signal analog-digital converters (A / D) 24,
It is digitized by 25, and the desired I and Q signals of the channel j are extracted by the channel signal detection circuits 26 and 27, respectively, and the decoder 28 that receives these two outputs receives the channel j
Of the baseband signal j (29) is reproduced.

FIG. 14 is a diagram showing the outputs of the quadrature modulation I / Q signal digital-analog converters (D / A) 8 and 9 of FIG. 13 on the IQ plane, where I is the I signal axis and Q. Is the Q signal axis.

[0009]

[Problems to be Solved by the Invention] As shown in FIG.
A lattice formed on the IQ plane of SK multiplexing, that is, since this is a QPSK signal, in the case of only one channel,
Only the central circle with stitches is present, and the signal exists at four points at 45 degrees diagonal. Next, when one channel is added, all the diagonals of the four circles with each of these four points as the center of the new circle
It becomes a point of 45 degrees. At this point, the number of points is nine. When a signal of one channel is further added, nine new circles centering on the above nine points are formed, and the number of QPSK lattice points becomes 16.

As the number of channels increases, the radius to the outermost shell increases in proportion to the number of channels. As a result, the power peak value that increases with channel combination increases dramatically in proportion to the square of the channel increase. Therefore, the power dynamic range of the transmitter, which should have the power equivalent to the channel multiplexing of the power of a single channel, requires an excessive dynamic range of the square, which is a very big problem. Was there.

As described above, the multiplexing by the voltage signal increases squarely in terms of electric power, and the larger the number of channels, the larger the load on the transmitter including the modulator.

The present invention solves the above problems, and in a multiplex communication system, an excessively simple circuit is used in the excess modulation circuit dynamic range generated by the combination of channel signals on the base station side without impairing the basic performance. It is an object of the present invention to provide a modulation device that can be included in a necessary and sufficient modulation circuit dynamic range that is originally required only by adding.

[0013]

In order to solve the above problems and achieve the object, the present invention provides a first means for receiving a plurality of communication channels and a means for combining signals of the plurality of communication channels. And a means for receiving the combined output to obtain an output proportional to a square root according to the magnitude, a means for receiving the output and modulating a carrier signal, and a means for outputting the modulated output to an amplification stage. To do.

The second means includes means for receiving a plurality of communication channels, means for combining the signals of the plurality of communication channels, and means for receiving the combined output and obtaining an output approximately proportional to a square root according to the size. , And means for receiving the output and modulating the carrier signal, and means for outputting the modulated output to the amplification stage.

A third means is a means for receiving a plurality of communication channels, a means for performing a Gray code or encoding similar to the channel composite signals of the plurality of communication channels, and an upper bit if necessary. The present invention is characterized by including a truncation unit, a unit that performs modulation using the truncated output, and a unit that outputs the modulated output to the amplification stage.

A fourth means is a means for receiving a plurality of encoded communication channels, a means for combining the signals of the plurality of communication channels, and an output proportional to a square root according to a size of the combined output. It is characterized by having means for obtaining, an means for receiving the output thereof and converting it into an analog signal, a means for receiving the analog signal and modulating the carrier signal, and a means for outputting the modulated output to an amplification stage.

A fifth means is a means for receiving a plurality of encoded communication channels, a means for synthesizing signals of the plurality of communication channels, and an analog output proportional to a square root according to a magnitude of the synthesized output. Is provided, means for converting the analog signal to a carrier signal, and means for outputting the modulated output to an amplification stage.

A sixth means is a means for receiving a plurality of encoded communication channels, and a channel composite signal of the plurality of communication channels in a lattice range corresponding to a square root of the number of channels on the I and Q voltage axes. It is characterized in that it has a limiting means, a means for performing modulation using the output subjected to limiting processing in the lattice range, and a means for outputting the modulated output to the amplification stage.

[0019]

According to the present invention, in the channel combination in the modulator for base station transmission, by having means for controlling the lattice range corresponding to the square root of the number of channels on the I and Q voltage axes, the value to be originally added is reduced. Limit the channel composite signal to the range of the I and Q voltage axes where approximately 100% of the power is present. Therefore, the electric power of a value twice the number of channels to be added is realized. This solves the problem of excessive dynamic range and excessive power of the I and Q combined signals.

Further, by adding a Gray code or coding similar thereto to the channel-synthesized signal in the base transmission apparatus, and a means for truncating the higher-order bits as necessary, it should be added originally. Limit the channel composite signal to the range of the I and Q power axes where approximately 100% of the value power lies.

Therefore, the range of the I and Q voltage axes is limited, and the dynamic range of the modulator which is close to the value of the number of channels to be added is realized. This gives I
It solves the excessive dynamic range of the Q-synthesized signal and excessive power generation.

[0022]

1 is a block diagram of a transmission system system of a base station communication device according to a first embodiment of the present invention.
The reference numerals indicating the respective constituent elements in FIG. 1 are the non-linear compression circuit 3
Except for 0 and 31, they are the same as those shown in FIG. 13 of the conventional example. This is characterized by a configuration provided in front of the I and Q signal quadrature modulation multipliers 11 and 13.

Next, the configuration and operation of the first embodiment will be described with reference to FIG. Similarly to the conventional example, each channel signal that has entered the quadrature modulation IQ division unit 7 through the channel recognition encoders 4, 5, ... The signals are combined and added to an I signal digital-to-analog converter (D / A) 8 and a Q signal digital-to-analog converter (D / A) 9, respectively. The I signal digital-analog converter (D / A) 8 and the Q signal digital-analog converter (D / A) 9 generate analog outputs corresponding to linear digital inputs. I
The respective analog outputs of the signal digital-analog converter (D / A) 8 and the Q signal digital-analog converter (D / A) 9 are supplied to the non-linear compression circuits 30 and 31, and compressed according to the magnitude of each input. And outputs the output to the quadrature modulation multiplier 11 for I signal and the quadrature modulation multiplier 13 for Q signal. All other configurations and operations are the same as those described in the conventional example, and therefore description thereof will be omitted.

According to the present embodiment having the above-mentioned configuration, the input of the transmission output amplifier 16 is compressed in voltage amplitude with respect to the channel-multiplexed baseband signals 1, 2, ... State, that is, it can be given as electric power corresponding to the number of channels. Therefore, the transmission output amplifier 16 needs to secure only the power dynamic range corresponding to the number of channels.

FIG. 2 is a circuit diagram of the first concrete example of the nonlinear compression circuits 30 and 31 shown in FIG. This Figure 2
Is an example of a square root circuit, the buffer amplifier 33 receiving the input voltage 32 outputs the output voltage 34 equal to the input voltage 32, and the output voltage 34 is supplied to the resistor 35, and further, through the resistor 35, the transistor 36 of the transistor 36. Connected to the emitter, the collector of the transistor 36 is connected to the anode of the diode 37. The cathode of the diode 37 is grounded. The base of the transistor 36 is connected to the base power supply (V _B ) 38. The emitter of the transistor 36 is a resistor 39.
Through an emitter power supply (V _E ) 40.

In such a configuration, the output voltage 41, which is the terminal voltage of the diode 37, is the input voltage of the buffer amplifier 33.
The voltage difference that occurs between the output voltage 34, which is equal to the voltage at 32, and the emitter current of transistor 36 is dominated by the emitter current flowing through resistor 35. Ie diode
This is because the current supplied to 37 is the collector current of the transistor 36 and the collector current is approximately equal to the emitter current. The transistor 36 functions as a current source due to the high output resistance characteristic of the collector, and since the input voltage 32 is determined by the resistance value of the resistor 35, it is supplied to the diode 37 as a divided current.

In order to prevent the operating region of the transistor 36 from interfering with the operating region of the diode 37, the transistor 36 keeps the base power source (V _B ) 38 sufficiently away from the ground potential, and the inside of the resistor 35 generated by the transistor 36 is generated. The direct current decrease amount of is compensated from the emitter power source (V _E ) 40 through the resistor 39.

FIG. 3 is a diagram showing the forward characteristic of the diode voltage V (output) with respect to the diode current I (input) in the diode 37 of FIG.
It is understood that, when the input currents given by the square function as shown by 3 and I4 are supplied, the output voltages at equal intervals shown by the diode voltages V1, V2, V3 and V4 can be obtained.

FIG. 4 shows the second non-linear compression circuit 30 and 31 of FIG.
3 is a circuit configuration diagram of a specific example of FIG. Input voltage 32
The buffer amplifier 33 which has received the output voltage equal to the input voltage 32
The output voltage 34 is supplied to the resistor 42, and is further connected to the anode of the diode 43 through the resistor 42. The cathode of the diode 43 is grounded. A resistor 44 is connected in parallel to the diode 43.
In such a configuration, the input voltage 32 is converted into a current and supplied to the diode 43 and the resistor 44 through the resistor 42.

Upon receiving the currents of the diode 43 and the resistor 44, a voltage determined by the combined resistance value of the diode 43 and the resistor 44 is generated as the output voltage 45. At this time, by setting the resistance value of the resistor 44 smaller than the internal resistance of the diode 43 in the small current region, the output voltage is the product of the current and the resistance value of the resistor 44 in the range where the supplied current is small. Generally, the output voltage 45 can be made approximately proportional to the input voltage 32.

Next, when the input voltage 32 increases and the internal resistance of the diode 43 decreases to approach the resistance value of the resistor 44, the resistor
The current supplied through 42 shunts to the diode 43 and the resistor 44, and the output voltage 45
43 begins to rule. Therefore, the output voltage 45 is generally given by the square root of the input voltage 32 of the buffer amplifier 33, and when the input voltage 32 further increases, the diode 43
The internal resistance of is further reduced, so that the output voltage 45 is completely dominated by the diode 43.

FIG. 5 is a diagram showing the characteristic of the output voltage V with respect to the input current I by the diode 43 and the resistor 44 of FIG.
When an input current given by a square function as shown by input currents I1, I2, I3, I4 is supplied, output voltages V1, V
It is shown that the non-linear output voltages indicated by 2, V3 and V4 can be obtained.

According to this second specific example, the output voltage is
When the input voltage is small, it is output linearly, that is, proportionally, and approaches the square root as the input increases.
Therefore, a voltage proportional to the number of channels is provided when the number of input channels is small, and a voltage closer to the square root of the number of channels is provided as the number of channels is increased. The two-sided effect that communication power in a large number of states can be limited to an appropriate value is obtained.

FIG. 6 is a block diagram of a transmission system system of a base station communication device according to the second embodiment of the present invention. The reference numerals for the respective constituent elements in FIG. 6 correspond to those in the first embodiment shown in FIG. 1 except for the I and Q signal data converters 49 and 50. Here, in this embodiment, the I signal data conversion unit 49 and the Q signal data conversion unit 50 are replaced by I and Q signal digital-analog converters.
(D / A) 8 and 9 are characterized by being built in.

Next, referring to FIG. 6 for the second embodiment,
The configuration and operation will be described.

Similarly to the conventional example, each channel signal that has entered the quadrature modulation IQ division unit 7 through the channel recognition encoders 4, 5, ..., 6 is QPSK I by the quadrature modulation IQ division unit 7. A signal composite signal 46 and a Q signal composite signal 47 are created and supplied to the I signal data converter 49 and the Q signal data converter 50, respectively. This I signal data converter 49 and Q
In the signal data converter 50, the upper bits are truncated when the data length exceeds the required value.

The fluctuation speed of the upper bits is the slowest of all the bits, and the bit with the highest fluctuation, that is, the highest frequency is the LSB. Therefore, it can be said that the bits required to convey information correctly are close to LSB.

If the upper bits are simply truncated, a significant discontinuity occurs before and after the digit digit raising operation. Therefore, the digit digit raising procedure before and after the bits to be truncated is made similar to the Gray code conversion. That is, when targeting the high-order bits consisting of 3 bits, the increasing states are 000, 001, 010, 011, 100, 101, 110, 11 in general binary numbers.
It is circulated and expressed as 1,000, but the part that continues after 111,000 becomes large discontinuity. Furthermore, if the upper 1 bit is truncated, it circulates as 00, 01, 11, 00, and the discontinuity between 11 and 00 becomes a problem. Therefore, the code is 000,001,011,010,11
Circulate 0, 111, 101, 100,000. In this case, the Hamming distances of adjacent codes are all 1, and even if the most significant bits are truncated, 00, 01, 11, 10, 10, 10, 11, 0
The cycle is 1,00,00 and the Hamming distance is 1 or less. Although there is a part where 10 and 00 overlap, it is obvious that the effect of preventing discontinuity outweighs the harmful effects. A similar method can be used to encode a number of 4 bits or more. In this way, by keeping the signal with more digits than necessary within the range of the desired digit, a modulated signal with a desired dynamic range can be realized without significantly mistaking the signal information.

FIG. 7 shows the I signal data converter shown in FIG.
4 is a circuit configuration diagram showing a concrete example of a digital modulation circuit of 49 and a Q signal data conversion unit 50. FIG. The I signal data conversion unit 49 and the Q signal data conversion unit 50 to which the I signal synthesis signal 46 and the Q signal synthesis signal 47 are supplied are supplied in parallel from the I signal synthesis signal 46 and the Q signal synthesis signal 47 in FIG. 7, respectively. The two ROMs that receive it, namely the I signal 1-4 quadrant ROM 52 and the I signal 2
-3 quadrant ROM 53 and Q signal 1-2 quadrant ROM 54 and Q
Signal 3-4 quadrant ROM 55, I signal 1-4 quadrant RO
M52, I signal 2-3 quadrant ROM 53, Q signal 1-2 quadrant RO
Output data of the M54, Q signal 3-4 quadrant ROM 55 is supplied to the data selection circuit 117. The data selection circuit 117 uses the modulation timing clock signal 56 from the clock control circuit 51 to adjust the phase rotation of QPSK to 45 degrees, 135 degrees.
Degrees, 225 degrees, and 315 degrees, in a fixed order, that is, ROM 52 for I signal 1-4 quadrant, ROM 5 for Q signal 1-2 quadrant
4, I signal 2-3 quadrant ROM53, Q signal 3-4 quadrant ROM5
The modulated output 57 is output in the order of 5.

FIG. 8 shows the I signal 1-4 quadrant ROM 52 and the I signal 2
-3 quadrant ROM 53 and Q signal 1-2 quadrant ROM 54 and Q
8 is a waveform diagram for explaining the compression function provided by the signal 3-4 quadrant ROM 55. FIG. 8 (a) shows the reference carrier waveform shown from the input data in time series, and FIG. 8 (b) shows the I signal. 1-4 quadrant ROM 52 and I signal 2-3 quadrant ROM 53 and Q signal 1
-The output data of the quadrant ROM54 and the Q signal 3-4 quadrant ROM55 is shown in FIG. 8 in comparison with the waveform of FIG. 8 (a).
The waveform in (b) shows the effect of being compressed to the square root value.

FIG. 9 is a block diagram of the transmission system of the base station communication device in the third embodiment of the present invention. The reference numerals of the components in FIG. 9 are the same as those of the first embodiment shown in FIG. The first embodiment is characterized in that the non-linear compression circuits 30 and 31 are built in the I and Q signal digital-analog converters (D / A) 8 and 9.

Next, referring to FIG. 9 for the third embodiment,
The configuration and operation will be described. Similarly to the conventional example, each channel signal that has entered the quadrature modulation IQ division unit 7 through the channel recognition encoders 4, 5, ... Although it is combined with the signal,
In the present embodiment, each composite output is a non-linear compression circuit.
The signals are supplied to 30 and 31 and subjected to a non-linear compression action corresponding to the magnitude of each input, and the compressed outputs thereof are an I signal digital-analog converter (D / A) 8 and a Q signal digital-analog converter (D / A), respectively. A) 9 is added. The I signal digital-to-analog converter (D / A) 8 and the Q signal digital-to-analog converter (D / A) 9 generate analog outputs corresponding to linear digital inputs. All other structures and operations are the same as those described with reference to FIG.

According to the present embodiment having the above-mentioned structure, the input of the transmission output amplifier 16 has the voltage amplitude compressed with respect to the channel-multiplexed baseband signals 1, 2, ... It is possible to give the electric power corresponding to the state, that is, the number of channels. Therefore, the transmission output amplifier 16 needs to secure only the power dynamic range corresponding to the number of channels.

FIG. 10 shows the I signal digital-analog converter.
(D / A) 8 and Q signal digital-analog converter (D / A)
FIG. 3 is a circuit configuration diagram showing a specific example of non-linear compression circuits 30 and 31 incorporated in A) 9. In FIG. 10, digital input 58, that is, first bit signal 59, second bit signal 60, third bit signal 61, fourth bit signal 62, fifth bit signal 63, ... Nth bit, that is, most significant bit signal 64 Is inputted to the operation gates 65, 66, 67, 68, ....
The output of each gate is supplied to the output gates 69, 70, 71, 72, 73, ... And the lower output gate suppression circuits 74, 75,
It is also supplied to 76, 77, 78, .... Output gate 69, 70, 7
The outputs of 1, 72, 73, ... Are lower output gate suppression circuits 74, 7
Controlled by the outputs of 5, 76, 77, 78, ..., the signal output 85,
That is, a new first bit signal 79, a new second bit signal 80,
Third bit signal 81, fourth bit signal 82, fifth bit signal
.., nth bit, that is, the most significant bit signal 84 is supplied to the I, Q digital-analog conversion circuits (D / A) 8, 9.

Next, the operation will be described. In FIG. 10, digital input 58, that is, first bit signal 59, second bit signal 60, third bit signal 61, fourth bit signal 6
2, a fifth bit signal 63, ... An n-th bit, that is, an input signal composed of the most significant bit signal 64, and receives an operation gate
65, 66, 67, 68, ... Comparing and detecting integer square numbers of 2 bits or more. For example, the gate 65 detects "4", the gate 66 detects "9", the gate 67 detects "1", and so on. The output of each gate is output gate 69, 70, 71, 7
, And also to the lower output gate suppression circuits 74, 75, 76, 77, 78 ,. The outputs of the output gates 69, 70, 71, 72, 73, ... Are controlled by the outputs of the lower output gate suppression circuits 74, 75, 76, 77, 78 ,. 2nd bit signal 8
Only one of 0, the third bit signal 81, the fourth bit signal 82, the fifth bit signal 83, ..., The nth bit, that is, the most significant bit signal 84 has the detection information. Conversion gate 86, 8
7, 88, ..., 89 convert these into binary numbers. That is, if the detection information is "3" indicating the input value "9", the new output bit is the first bit line 90 and the second bit line.
91 becomes "H". These new output bit lines 90, 9
An output signal 85 including 1, 92, ..., 93 is supplied to I, Q signal digital-analog conversion circuits (D / A) 8, 9.

FIG. 11 shows the operation gates 65 and 6 in FIG.
It is a circuit block diagram of the specific example of 6, 67, 68 ,. FIG. 11 shows an example used for detecting the input “9”. Digital input 58, that is, each bit line 59, 60, 61, 62 is "9"
Is input to the first-stage comparison gates 98, 99, 100, 101 together with the comparison data lines 94, 95, 96, 97 indicating. Comparison data line
94, 95, 96 and 97 are set to "H", "L", "L" and "H" from the LSB comparison data line 94 to indicate "9". If the digital input 58 indicates "7", the bit lines 59, 60, 61, 62 in FIG. 11 are "H", "H", "H", "L", respectively.
The output of the stage comparison gates 98, 99, 100, 101 is "L",
"H", "H", "H". Signal side second stage comparison gate
The highest 105 among 102, 103, 104 and 105 is "H" as a result.
And "L" of the bit line 62, the output is set to "H". On the other hand, the comparison data side second stage comparison gates 106, 107, 108, 109
The uppermost 109 of the above is "L" in response to the output "H" of the first stage comparison gate 101 and the comparison data line 97 "H". Lowermost bit limiting gate 110, 111, 112, 113, most significant gate 11
3 receives the output "H" of the signal side second stage comparison gate 105 and the output "L" of the comparison data side second stage comparison gate 109, and presents an output "L".

As a result, the lower bit gates 104 and 108 receive this, both outputs are made "H" regardless of the value of the other input, and the higher bit comparison result is given priority and transmitted to the output judgment gate 114. . Since the comparison result of the gate 105 of the most significant bit is "H", the gate 114 inverts it to "L", that is, signal <comparison value. The role of the most significant bit comparison gates 101, 105, 109, 113 is to provide magnitude comparison information to the output when the most significant bit is different from the compare value and to the lower order if the most significant bit is equal to the compare value. The lower bit limit gates 110, 111, 112, 113 are activated so that the bits are compared again. When all the bits match the comparison value, the output of the gate 112 becomes "H". In this specific example, since the square root of the input value needs to be equal to or greater than an integer, the output of the gate 114 and the output of the gate 110 are added by the OR circuit 115 to form the output 116. There is.

According to the present embodiment having the above-described structure, the input of the digital / analog converters (D / A) 8 and 9 has a voltage amplitude compressed with respect to the channel-multiplexed baseband signal, as can be seen from the above operation. It is possible to provide the electric power corresponding to the selected state, that is, the number of channels.

Therefore, the modulation circuit after the digital-analog converter needs to secure only the dynamic range corresponding to the number of channels.

FIG. 12 is a block diagram of the transmission system of the base station communication device in the fourth embodiment of the present invention. 12 are the same as those in the first to third embodiments (FIGS. 1, 6 and 9), and the same reference numerals are used.

This embodiment is attached to an I signal data conversion section 49 and a Q signal data conversion section 50 which receive an I signal synthesis signal 46 and a Q signal synthesis signal 47, which are output signals of the quadrature modulation IQ division unit 7, respectively. Further, it has an I signal data conversion ROM 49A and a Q signal data conversion ROM 50A driven by the clock control circuit 51. Then, the data selection circuit 11
A digital-analog converter (D / A) 118 is provided as an output example of 7.

Next, the configuration and operation of this embodiment will be described with reference to FIG.

Similarly to each of the above-mentioned embodiments, each channel signal which has passed through the channel recognition encoders 4, 5, ..., 6 and enters the quadrature modulation IQ division unit 7 is QPSK by the quadrature modulation IQ division unit 7. The I signal composite signal 46 and the Q signal composite signal 47 are generated and supplied to the I signal data converter 49 and the Q signal data converter 50, respectively. I signal data converter 49 and Q
Each of the signal data conversion units 50 has an RO for I signal data conversion.
The M49A and the Q signal data conversion ROM 50A are connected to exchange data. A clock signal is supplied from the clock control circuit 51 to these ROMs 49A and 50A.

The I signal data conversion unit 49 and the Q signal data conversion unit 50 respectively use the input I signal combined signal 46 and Q signal combined signal 47 as address information for I signal data conversion RO.
It is transmitted to the M49A and the Q signal data conversion ROM 50A, and the compressed value corresponding to the size of the address value is transferred to the I signal data conversion ROM 49A and the Q signal data conversion ROM 50A.
Read from. The I signal data conversion unit 49 and the Q signal data conversion unit 50 supply the output data of the ROM 49A and ROM 50A to the data selection circuit 117. In the data selection circuit 117, R
Clock control circuit for output data of OM49A and ROM50A
The modulation timing clock signal from 51 is combined and selected to the combination corresponding to 45 degrees, 135 degrees, 225 degrees, and 315 degrees according to the phase rotation of QPSK, and the digital-analog converter (D
/ A) 118. The digital-analog converter 118 is
Generates an analog output corresponding to a linear digital input. This analog output is a bandpass filter (BP
F) Remove unnecessary frequency components in 15 and transmit output amplifier 1
Supplied to 6. The rest of the configuration and operation are the same as those described in each of the above-mentioned embodiments, and therefore will be omitted.

The I signal data converter 49 shown in FIG.
And Q signal data conversion unit 50 and I signal data conversion ROM 49
ROM 50A for A and Q signal data conversion and clock control circuit
A concrete example of the digital modulation circuit composed of 51 is the same as that shown in FIG. The I signal data conversion unit 49, the Q signal data conversion unit 50, and the I signal data conversion ROMs 49A and Q to which the I signal synthesis signal 46 and the Q signal synthesis signal 47 are supplied.
The signal data conversion ROM 50A is composed of an I signal composite signal 46 and a Q signal.
Two ROMs respectively supplied in parallel from the signal synthesis signal 47, that is, the I signal 1-4 quadrant ROMs 52 and I in FIG.
Signal 2-3 quadrant ROM 53 and Q signal 1-2 quadrant ROM 54
And Q signal 3-4 quadrant ROM 55, output data of I signal 1-4 quadrant ROM 52, I signal 2-3 quadrant ROM 53, Q signal 1-2 quadrant ROM 54, Q signal 3-4 quadrant ROM 55 Is
It is supplied to the data selection circuit 117. This data selection circuit 1
17, the modulation timing clock signal 56 from the clock control circuit 51 adjusts the phase rotation of QPSK to 45 degrees,
Amplitudes corresponding to 5 degrees, 225 degrees, and 315 degrees are in a fixed order, that is, ROM 52 for I signal 1-4 quadrant, ROM for Q signal 1-2 quadrant
54, I signal 2-3 quadrant ROM 53, Q signal 3-4 quadrant ROM
The modulated output 57 is output in the order of 55.

ROM 5 for I signal 1-4 quadrant in FIG. 7 above
2 and I signal ROM 53 for 2-3 quadrants and Q signal R for 1-2 quadrants
The compression function provided by the OM 54 and the ROM 55 for the Q signal 3-4 quadrant is the same as that shown in FIG.

In the present embodiment, the grid range is limited to the square root of the number of channels on the IQ voltage axis, and the channel is in the range of the I and Q voltage axes where about 100% of the power of the value to be originally added exists. The combined signal can be limited, which avoids the excessive dynamic range and power of the I, Q combined signal.

[0058]

As described above, the modulation device of the present invention is extremely simple in the excessive modulation power dynamic range generated by the combination of digital signals in the channel where the channels are multiplexed, without impairing the basic performance. By adding only such a circuit, it becomes possible to fit within the necessary and sufficient modulation power dynamic range that is originally necessary. As a result, the dynamic range of the modulation circuit imposed on the transmitter of multiplexed communication can be corrected appropriately as the number of multiplexed channels increases, and the devices used for the modulator and amplifier can be supported with lower power ratings. Therefore, a great effect of reducing the power consumption of the device can be obtained. Further, the reduction of the heat generation amount of these circuits lowers the element temperature and improves the operation reliability. Further, this leads to reduction of heat dissipation and cooling device, which leads to downsizing of equipment and cost reduction.

[Brief description of drawings]

FIG. 1 is a transmission system system configuration diagram of a base station communication device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a first specific example of the nonlinear compression circuit shown in FIG.

3 is a forward characteristic diagram of a diode voltage in the nonlinear compression circuit shown in FIG.

FIG. 4 is a circuit configuration diagram of a second specific example of the nonlinear compression circuit shown in FIG.

5 is a characteristic diagram of an output voltage with respect to an input current by the diode and the resistor shown in FIG.

FIG. 6 is a configuration diagram of a transmission system of a base station communication device according to a second embodiment of the present invention.

7 is a circuit configuration diagram showing a specific example of a digital modulation circuit of the I, Q signal data conversion unit shown in FIG.

8 is a waveform diagram illustrating a compression function of the digital modulation circuit shown in FIG.

FIG. 9 is a transmission system system configuration diagram of a base station communication device according to a third embodiment of the present invention.

10 is a circuit configuration diagram of a specific example of the nonlinear compression circuit shown in FIG.

11 is a circuit configuration diagram of a specific example of the arithmetic gate shown in FIG.

FIG. 12 is a transmission system system configuration diagram of a base station communication device in a fourth embodiment of the present invention.

FIG. 13 is a system configuration diagram of a transmission system and a reception system in a conventional base station communication device.

14 is a diagram showing the output of the quadrature modulation IQ signal digital-analog converter in FIG. 13 as seen on the IQ plane.

[Explanation of symbols]

1 ... Baseband signal 1, 2 ... Baseband signal 2,
3 ... Baseband signal n, 4, 5, 6 ... Channel recognition encoder, 7 ... Quadrature modulation I, Q conversion divider, 8 ... I signal digital / analog converter, 9 ... Q signal digital / analog converter, 10 ... Reference carrier signal for quadrature modulation, 11 ... I
Quadrature modulation multiplier for signal, 12, 20 ... Phase shifter, 13 ... Quadrature modulation multiplier for Q signal, 14 ... Quadrature modulation adder, 15 ...
Band pass filter (BPF), 16 ... Transmission output amplifier,
17 ... Propagation path, 18 ... Quadrature demodulation reference carrier signal, 19
... Quadrature demodulation multiplier for I signal, 21 ... Quadrature modulation multiplier for Q signal, 22, 23 ... Low pass filter (LPF), 24, 25
... Analog-digital converter (A / D), 26,27 ... Channel signal detection circuit, 28 ... Decoder, 29 ... Channel j baseband signal j, 30,31 ... Non-linear compression circuit, 33 ...
Buffer amplifier, 36 ... Transistor, 37, 43 ... Diode, 46 ... I signal composite signal, 47 ... Q signal composite signal,
49 ... I signal data conversion section, 49A ... I signal data conversion ROM, 50 ... Q signal data conversion section, 50A ... Q signal data conversion ROM, 51 ... Clock control circuit, 52 ... I signal 1-4 quadrant ROM , 53 ... ROM for I signal 2-3 quadrant,
54 ... ROM for Q signal 1-2 quadrant, 55 ... R for Q signal 3-4 quadrant
OM, 56 ... Modulation timing clock signal, 65-68 ...
Operation gate, 69-73 ... Output gate, 74-78 ... Lower output gate suppression circuit, 86-89 ... Conversion gate, 98-10
1 ... First stage comparison gate, 102-105 ... Signal side second stage comparison gate, 106-109 ... Comparison data side second stage comparison gate,
110 to 113 ... Lower bit limit gate, 117 ... Data selection circuit, 118 ... Digital-analog converter (D / A).

Claims (6)

[Claims] 1. A means for receiving a plurality of communication channels, a means for combining the signals of the plurality of communication channels, a means for receiving the combined output and obtaining an output proportional to a square root according to a size, and a means for receiving the outputs. A modulator having means for modulating a carrier signal and means for outputting the modulated output to an amplification stage. 2. A means for receiving a plurality of communication channels, a means for synthesizing signals of the plurality of communication channels, a means for receiving the synthesized output and obtaining an output approximately proportional to a square root according to the size, and an output thereof. A modulator having means for modulating the received carrier signal and means for outputting the modulated output to an amplification stage. 3. Means for receiving a plurality of communication channels, means for applying a Gray code or coding similar to the channel composite signals of the plurality of communication channels, and means for truncating the upper bits as necessary. A modulator comprising: means for performing modulation using the truncated output and means for outputting the modulated output to an amplification stage. 4. A means for receiving a plurality of encoded communication channels, a means for combining the signals of the plurality of communication channels, and a means for receiving the combined output and obtaining an output proportional to a square root according to a size. A modulator comprising: a means for receiving the output and converting it into an analog signal; a means for receiving the analog signal and modulating the carrier signal; and a means for outputting the modulated output to an amplification stage. 5. A means for receiving a plurality of coded communication channels, a means for combining the signals of the plurality of communication channels, and an analog signal for receiving the combined output and obtaining an analog output proportional to a square root in accordance with the magnitude. Means to convert to
A modulator comprising: means for modulating the analog signal into a carrier signal; and means for outputting the modulated output to an amplification stage. 6. Means for receiving a plurality of encoded communication channels, and means for limiting a channel composite signal of the plurality of communication channels to a lattice range corresponding to the square root of the number of channels on the I and Q voltage axes. A modulation device comprising: a means for performing modulation using an output limited to a lattice range; and a means for outputting the modulated output to an amplification stage.