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JPH07202365A - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH07202365A
JPH07202365A JP5335063A JP33506393A JPH07202365A JP H07202365 A JPH07202365 A JP H07202365A JP 5335063 A JP5335063 A JP 5335063A JP 33506393 A JP33506393 A JP 33506393A JP H07202365 A JPH07202365 A JP H07202365A
Authority
JP
Japan
Prior art keywords
substrate
metal
metal substrate
film
semiconductor mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5335063A
Other languages
Japanese (ja)
Inventor
Haruo Tanmachi
東夫 反町
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5335063A priority Critical patent/JPH07202365A/en
Publication of JPH07202365A publication Critical patent/JPH07202365A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】 【目的】 基板には不向きと考えられていた所定金属を
基板として用い得るように巧みに構成し、強度的に優れ
た安価な薄膜(多層)基板を極めて容易に実用に供する
ことをその目的とする。 【構成】 金属基板1上の実質的全面に、導電率が高く
且つ非磁性体である金属膜2を形成し、その上にストリ
ップ線路(導体)3を形成し、金属膜2を、ストリップ
線路3の接地層又は電源層として用いるように構成した
ので、金属基板1には電磁場が生じにくい、すなわち高
周波に関する金属基板1の影響は、無視することができ
る。
(57) [Summary] [Purpose] It is extremely easy to put a thin film (multi-layer) substrate with excellent strength into practical use, by skillfully configuring it so that it can use a certain metal that was considered unsuitable for the substrate. Its purpose is to serve. A metal film 2 having a high conductivity and a non-magnetic material is formed on substantially the entire surface of a metal substrate 1, and a strip line (conductor) 3 is formed on the metal film 2. Since it is configured to be used as the ground layer or the power supply layer of No. 3, an electromagnetic field is unlikely to be generated in the metal substrate 1, that is, the influence of the metal substrate 1 on a high frequency can be ignored.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体実装基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting board.

【0002】[0002]

【従来の技術】薄膜回路を用いる配線基板は、配線密度
を高めることができ、また誘電体として比誘電率の低い
ポリイミド樹脂等を用いることができるので、実装密度
の向上や回路の高速動作化に最適である。しかしなが
ら、薄膜回路基板はコストが高く、広く普及するにいた
っていない。というのは、薄膜回路基板は、従来セラミ
ック基板やシリコン基板の上に形成されているが、セラ
ミック基板は、表面に不可避的にポアが存在するので、
表面処理(グレース層等の形成)及びその後の高価な研
磨加工が不可欠であり、他方、シリコン基板は、機械的
強度が弱く且つ大型のものの製造コストが高い、といっ
た不都合があるからである。
2. Description of the Related Art A wiring board using a thin film circuit can have a high wiring density and a polyimide resin having a low relative dielectric constant can be used as a dielectric, so that the packaging density can be improved and the circuit can operate at high speed. Is perfect for However, the thin film circuit board is high in cost and has not come into widespread use. The thin film circuit board is conventionally formed on a ceramic substrate or a silicon substrate, but since the ceramic substrate has pores inevitably on the surface,
This is because surface treatment (formation of a grace layer or the like) and subsequent expensive polishing are indispensable, and on the other hand, a silicon substrate has weak mechanical strength and large manufacturing cost is disadvantageous.

【0003】このため、基板として、良好な熱伝導性を
有し、大型のそれを安価且つ容易に製造し得る金属製の
ものを用いることが検討されている。ここで、代表的な
金属の特性を表1に示す。
For this reason, it has been considered to use a large-sized substrate made of metal which has good thermal conductivity and can be easily manufactured at a low cost. Here, the characteristics of typical metals are shown in Table 1.

【0004】[0004]

【表1】 [Table 1]

【0005】例えば、Cu,Al,Ni等の安価な金属
は、熱膨張係数が大きいために、必然的に用途が制限さ
れ、Mo,Ta等の高融点金属は、特性的に問題ない
が、材料自体が高価であり且つ加工が容易でないという
不都合を有している。その点、いわゆる4−2合金(F
e58%−Ni42%)やステンレス鋼(Fe78%−
Cr12%)は、特性的にバランスが良好であり、ま
た、加工も容易であり(圧延加工により、容易に板材を
得ることができる)、更には、材料が比較的安価でもあ
る。
For example, inexpensive metals such as Cu, Al and Ni have a large thermal expansion coefficient, so that their applications are necessarily limited, and refractory metals such as Mo and Ta have no problem in characteristics. It has the disadvantage that the material itself is expensive and not easy to process. In that respect, the so-called 4-2 alloy (F
e58% -Ni42%) and stainless steel (Fe78%-
Cr12%) has a good balance in characteristics, is easy to process (a plate material can be easily obtained by rolling), and is also relatively inexpensive.

【0006】[0006]

【発明が解決しようとする課題】しかるに、上記4−2
合金あるいはステンレス鋼は、強磁性体であるために、
その近傍に導体が配置された場合に、導体のインダクタ
ンスが上昇してしまう、すなわち、高速の回路には不向
きであるという欠点を有していた。そこで、本発明にお
いては、そのような電気的な特性の劣化を引き起こし得
る上記4−2合金及びステンレス鋼の生来的な特性を合
理的に克服することにより、それらの金属を基板として
実用可能にし、安価な薄膜基板(薄膜多層基板)を実現
することをその課題とする。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Alloys or stainless steels are ferromagnetic materials,
If the conductor is arranged in the vicinity of the conductor, the inductance of the conductor increases, that is, it is not suitable for a high-speed circuit. Therefore, in the present invention, by reasonably overcoming the inherent characteristics of the 4-2 alloy and the stainless steel, which can cause such deterioration of the electrical characteristics, those metals can be practically used as a substrate. The object is to realize an inexpensive thin film substrate (thin film multilayer substrate).

【0007】[0007]

【課題を解決するための手段】図1は、上記目的を達成
する本発明の基本原理を説明する原理図である。金属基
板1上の実質的全面には、非磁性且つ電気良導体の金属
膜2が形成され、その上には、図示しない電気部品(半
導体部品)等が搭載され得るストリップ線路(帯状の導
体)3が形成され、金属膜2は、ストリップ線路3の接
地層又は電源層として用いられる。
FIG. 1 is a principle diagram for explaining the basic principle of the present invention for achieving the above object. A nonmagnetic and electrically conductive metal film 2 is formed on substantially the entire surface of the metal substrate 1, and a strip line (belt-shaped conductor) 3 on which an electric component (semiconductor component) or the like (not shown) can be mounted is formed on the metal film 2. And the metal film 2 is used as a ground layer or a power supply layer of the strip line 3.

【0008】金属基板1は、鉄とクロム10〜15%を
含み、その他の元素が約5%以下であるステンレス鋼で
構成され得る。(尚、特に熱膨張の観点からクロム含有
率が10〜12%であることが望ましい。また、耐食性
向上のために、Mo,Ni等を5%以内で加えることが
できる。)金属基板1は、鉄とニッケル約42%を含
み、その他の元素が約5%以下である合金で構成され得
る。
The metal substrate 1 may be made of stainless steel containing iron and chromium of 10 to 15% and other elements of about 5% or less. (In particular, it is preferable that the chromium content is 10 to 12% from the viewpoint of thermal expansion. Further, in order to improve the corrosion resistance, Mo, Ni and the like can be added within 5%.) The metal substrate 1 , Alloys containing about 42% iron and nickel and up to about 5% other elements.

【0009】金属基板1上の導体は、パターン形成が為
されずに基板上全面に形成されて成り得る。金属基板1
は、その表面に硬質めっきを施した後に研磨されて成り
得る。
The conductor on the metal substrate 1 may be formed on the entire surface of the substrate without pattern formation. Metal substrate 1
Can consist of hard-plating the surface and then polishing.

【0010】[0010]

【作用】金属基板1上の実質的全面に、導電率が高く且
つ非磁性体である金属膜2を形成し、その上にストリッ
プ線路(導体)3を形成するように構成したので、伝送
特性が最も問題となる高周波領域を想定して、例えば、
ストリップ線路3と金属膜2との間に高周波電圧を加え
た場合に、ストリップ線路の幅(W:数10μ)及び厚
さ(t:数μ)が基板の大きさ(数cm)と比較して十分
小さいこともあり、金属膜2の表面にのみ電流が流れ、
金属基板1には電磁場が生じない、すなわち高周波に関
する金属基板1の影響は、無視することができる。
Since the metal film 2 having a high conductivity and a non-magnetic material is formed on substantially the entire surface of the metal substrate 1 and the strip line (conductor) 3 is formed on the metal film 2, the transmission characteristics are improved. Assuming the high frequency region where
When a high frequency voltage is applied between the strip line 3 and the metal film 2, the width (W: several 10 μ) and the thickness (t: several μ) of the strip line are compared with the size of the substrate (several cm). Is small enough, current flows only on the surface of the metal film 2,
No electromagnetic field is generated in the metal substrate 1, that is, the influence of the metal substrate 1 on the high frequency can be ignored.

【0011】[0011]

【実施例】以下、本発明の実施例を図面を参照して説明
する。先ず、第1の実施例について説明するに、図2を
参照すると、金属基板11は、成分的にいわゆる4−2
合金(Fe58%−Ni42%)で構成され、容易に圧
延加工で板状に形成された後に研磨加工(鏡面仕上げ)
が施される。尚、4−2合金の代わりに、ステンレス鋼
(例えば、Fe78%−Cr12%から成るステンレス
鋼)を用いることができるが、4−2合金又はステンレ
ス鋼のいずれの材料も、半導体(シリコン)に近い熱膨
張係数を有し得るので(表1参照)、半導体に熱的な過
大な力を及ぼさずに済み、好ましい。また、上記いずれ
の材料も、材料的及び加工的な大きさ(基板サイズ)に
関する制約が殆どなく、安価に入手できるため非常に好
都合である。ところで、上記研磨加工は、微細な配線を
形成する場合に、誘電体層のショートを防いだり電源層
のインピーダンスを下げる等のために基板表面を滑らか
にする必要があるために、重要な工程である。特に平滑
な面が要求される場合には、4−2合金をそのまま研磨
する代わりに、先に表面にめっき(例えば、緻密で安価
な無電解Niめっきが好適である)を施した後に研磨を
行うことが好ましい。
Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 2 for explaining the first embodiment, the metal substrate 11 is so-called 4-2 in terms of composition.
Composed of alloy (Fe58% -Ni42%), easily rolled into a plate shape and then polished (mirror finish)
Is applied. Note that stainless steel (for example, stainless steel composed of Fe78% -Cr12%) can be used in place of the 4-2 alloy, but any material of the 4-2 alloy or stainless steel can be used as a semiconductor (silicon). Since it may have a thermal expansion coefficient close to that of the semiconductor (see Table 1), it does not need to exert an excessive thermal force on the semiconductor, which is preferable. Further, any of the above-mentioned materials is very convenient because there are almost no restrictions on the material size and the processing size (substrate size) and they can be obtained at low cost. By the way, the above polishing process is an important step because it is necessary to smooth the substrate surface in order to prevent short-circuiting of the dielectric layer or lower the impedance of the power supply layer when forming fine wiring. is there. When a particularly smooth surface is required, instead of polishing the 4-2 alloy as it is, the surface is first plated (for example, dense and inexpensive electroless Ni plating is suitable) and then polished. It is preferable to carry out.

【0012】次いで、このような金属基板11の上(同
図では、下側)には、Cr(0.1μ)、Cu(5.0
μ)、Cr(0.1μ)から成る膜(以下、Cr/Cu
/Cr膜)13が成膜形成される。尚、この膜(層)1
3は、接地層として用いられる。本実施例では、DCマ
グネトロンスパッタリング法を用いて成膜形成すること
を予定するが、真空蒸着法やめっき法も用いられ得る。
公知のフォトリソグラフィ法を用いて、Cr/Cu/C
r膜のパターンを形成することができるが、通常の場
合、パターン形成は不要である。
Next, Cr (0.1 μ) and Cu (5.0 μm) are formed on the metal substrate 11 (on the lower side in the figure).
μ) and Cr (0.1 μ) (hereinafter Cr / Cu
/ Cr film) 13 is formed. This film (layer) 1
3 is used as a ground layer. In this embodiment, it is planned to form a film by using the DC magnetron sputtering method, but a vacuum vapor deposition method or a plating method can also be used.
Cr / Cu / C using known photolithography method
The pattern of the r film can be formed, but in the usual case, the pattern formation is unnecessary.

【0013】次いで、このCr/Cu/Cr膜13の上
には、感光性ポリイミド前駆体ワニスが、スピンコート
法で塗布され、その後、溶剤が乾燥せしめられる。そし
て、マスクを通して紫外光を照射し、これを現像するこ
とにより、ビアが形成される。次に、窒素中350〜4
50℃で焼成してポリイミド樹脂とする。次いで、Cr
/Cu/Cr膜を上記と同様に形成する。通常の方法で
レジストパターンを作成した後に、フェリシアン化カリ
ウムと水酸化カリウムの混合溶液を用いてCrをエッチ
ングし、硫酸と過酸化水素水の混合溶液を用いてCuを
エッチングし、更に下層のCrをエッチングする。レジ
ストを適当な剥離液で剥離し、導体パターン(信号層1
5,17や電源層19等)を得る。以上の工程を必要回
数だけ繰り返すことにより、多層配線パターンを得るこ
とができる。
Next, a photosensitive polyimide precursor varnish is applied on the Cr / Cu / Cr film 13 by spin coating, and then the solvent is dried. Then, a via is formed by irradiating ultraviolet light through the mask and developing this. Next, 350 to 4 in nitrogen
Baking at 50 ° C. gives a polyimide resin. Then Cr
A / Cu / Cr film is formed in the same manner as above. After forming a resist pattern by a normal method, Cr is etched using a mixed solution of potassium ferricyanide and potassium hydroxide, Cu is etched using a mixed solution of sulfuric acid and hydrogen peroxide solution, and Cr of the lower layer is further removed. Etching. The resist is peeled off with an appropriate peeling solution, and the conductor pattern (signal layer 1
5, 17 and the power supply layer 19) are obtained. By repeating the above steps a required number of times, a multilayer wiring pattern can be obtained.

【0014】最上層のパッド21は、Cu膜の上にNi
とAuをめっき処理することにより形成され、半導体部
品、すなわちICチップ23は、樹脂で接着・実装さ
れ、金ワイヤを介してボンディング接続が為される。
尚、4−2合金から成る金属基板の場合、熱伝導性が比
較的良くないので(表1参照)、基板の反対面には、必
要に応じて、放熱フィン25が取着され得る。
The uppermost pad 21 is made of Ni on the Cu film.
Are formed by plating Au and Au, the semiconductor component, that is, the IC chip 23 is bonded and mounted with a resin, and a bonding connection is made via a gold wire.
In the case of a metal substrate made of a 4-2 alloy, the heat conductivity is relatively poor (see Table 1), so that a radiation fin 25 can be attached to the opposite surface of the substrate, if necessary.

【0015】以下、表2の実施例について説明するに、
図2を参照する。金属基板31は、第1実施例と同様に
上記4−2合金又はステンレス鋼で構成され、この金属
基板31の上(同図では、下側)には、上記第1実施例
と同様に、Cr/Cu/Cr膜33が成膜形成される。
尚、この膜(層)33は、接地層として用いられる。
In the following, to describe the embodiment of Table 2,
Please refer to FIG. The metal substrate 31 is made of the 4-2 alloy or stainless steel as in the first embodiment, and on the metal substrate 31 (the lower side in the figure), as in the first embodiment, A Cr / Cu / Cr film 33 is formed.
The film (layer) 33 is used as a ground layer.

【0016】次いで、Cr/Cu/Cr膜33の上に
は、CVD法により、二酸化シリコン膜35(膜厚さ:
1μ以下、好ましくは約300nm)が形成される。尚、
Cr/Cu/Cr膜(導体)33及び二酸化シリコン膜
(誘電体層)35は、大容量のコンデンサを構成し、電
源のインピーダンスを低下させるので、IC等の動作電
流に起因する電圧ノイズが軽減されて好ましい。
Then, on the Cr / Cu / Cr film 33, a silicon dioxide film 35 (thickness:
1 μm or less, preferably about 300 nm) is formed. still,
The Cr / Cu / Cr film (conductor) 33 and the silicon dioxide film (dielectric layer) 35 form a large-capacity capacitor and lower the impedance of the power supply, so that voltage noise caused by the operating current of the IC or the like is reduced. Has been preferred.

【0017】次いで、この二酸化シリコン膜35の必要
な場所には、反応性イオンエッチング法により、ビア
(図示せず)が形成される。次いで、別のCr/Cu/
Cr膜37がその上に形成される。尚、この膜(層)3
7は、電源層として用いられる。金属基板31の上に、
このように、導体33、誘電体層35、導体37をこの
順序で形成し、一方の導体(33)を接地層、他方の導
体(37)を電源層として用いるのは、電源層(37)
のインピーダンスを下げるためである。
Then, vias (not shown) are formed in the silicon dioxide film 35 at the necessary places by the reactive ion etching method. Then another Cr / Cu /
The Cr film 37 is formed thereon. In addition, this film (layer) 3
7 is used as a power supply layer. On the metal substrate 31,
As described above, the conductor 33, the dielectric layer 35, and the conductor 37 are formed in this order, and one conductor (33) is used as a ground layer and the other conductor (37) is used as a power supply layer.
This is to reduce the impedance of.

【0018】これ以降の基板部分(信号層39,41や
パッド43等)の形成工程については、上記第1実施例
と同様であるので、その説明を省略する。
Subsequent steps of forming the substrate portion (signal layers 39, 41, pads 43, etc.) are the same as those in the first embodiment, and therefore the description thereof is omitted.

【0019】[0019]

【発明の効果】以上のように本発明によれば、基板には
不向きと考えられていた所定金属を基板として用い得る
ように巧みに構成したため、強度的に優れた安価な薄膜
(多層)基板を極めて容易に実用に供することが可能に
なる。
As described above, according to the present invention, an inexpensive thin film (multilayer) substrate excellent in strength is used because it is constructed so that a predetermined metal, which is considered unsuitable for a substrate, can be used as the substrate. Can be put to practical use very easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は、本発明の基本原理を説明する原理図で
ある。
FIG. 1 is a principle diagram illustrating a basic principle of the present invention.

【図2】図2は、本発明に係る半導体実装基板の第1実
施例の側部断面図である。
FIG. 2 is a side sectional view of a semiconductor mounting substrate according to a first embodiment of the present invention.

【図3】図3は、第2実施例の側部断面図である。FIG. 3 is a side sectional view of the second embodiment.

【符号の説明】[Explanation of symbols]

11,31…金属基板 13,33,37…Cr/Cu/Cr膜 15,17,39,41…信号層 19…電源層 21,43…パッド 23…ICチップ 35…二酸化シリコン膜 11, 31 ... Metal substrate 13, 33, 37 ... Cr / Cu / Cr film 15, 17, 39, 41 ... Signal layer 19 ... Power supply layer 21, 43 ... Pad 23 ... IC chip 35 ... Silicon dioxide film

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 金属基板(1)と、 金属基板(1)上の実質的全面に形成された非磁性且つ
電気良導体の金属膜(2)と、 金属膜(2)上に形成されたストリップ線路(3)、と
を有し、 金属膜(2)は、ストリップ線路(3)の接地層又は電
源層として用いられることを特徴とする半導体実装基
板。
1. A metal substrate (1), a metal film (2) of non-magnetic and good electric conductor formed on substantially the entire surface of the metal substrate (1), and a strip formed on the metal film (2). And a line (3), wherein the metal film (2) is used as a ground layer or a power supply layer of the strip line (3).
【請求項2】 上記金属基板(1)は、鉄とクロム10
〜15%を含み、その他の元素が約5%以下であるステ
ンレス鋼で構成されることを特徴とする請求項1に記載
の半導体実装基板。
2. The metal substrate (1) is made of iron and chromium.
The semiconductor mounting board according to claim 1, wherein the semiconductor mounting board is composed of stainless steel containing ˜15% and other elements of about 5% or less.
【請求項3】 上記金属基板(1)は、鉄とニッケル約
30〜50%を含み、その他の元素が約5%以下である
合金で構成されることを特徴とする請求項1に記載の半
導体実装基板。
3. The metal substrate (1) according to claim 1, wherein the metal substrate (1) is composed of an alloy containing about 30 to 50% of iron and nickel and about 5% or less of other elements. Semiconductor mounting board.
【請求項4】 上記金属基板(1)上の導体は、パター
ン形成が為されずに基板上全面に形成されて成ることを
特徴とする請求項1に記載の半導体実装基板。
4. The semiconductor mounting substrate according to claim 1, wherein the conductor on the metal substrate (1) is formed on the entire surface of the substrate without pattern formation.
【請求項5】 上記金属基板(1)は、その表面に硬質
めっきを施した後に研磨されて成ることを特徴とする請
求項1に記載の半導体実装基板。
5. The semiconductor mounting substrate according to claim 1, wherein the metal substrate (1) is formed by applying hard plating to the surface thereof and then polishing the surface.
JP5335063A 1993-12-28 1993-12-28 Semiconductor mounting board Withdrawn JPH07202365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5335063A JPH07202365A (en) 1993-12-28 1993-12-28 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5335063A JPH07202365A (en) 1993-12-28 1993-12-28 Semiconductor mounting board

Publications (1)

Publication Number Publication Date
JPH07202365A true JPH07202365A (en) 1995-08-04

Family

ID=18284347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5335063A Withdrawn JPH07202365A (en) 1993-12-28 1993-12-28 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH07202365A (en)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
JP2007157836A (en) * 2005-12-01 2007-06-21 Nitto Denko Corp Printed circuit board
JP2008060263A (en) * 2006-08-30 2008-03-13 Nitto Denko Corp Wiring circuit board and its manufacturing method
JP2008103745A (en) * 2007-11-12 2008-05-01 Nitto Denko Corp Method for manufacturing wired circuit substrate
JP2008109147A (en) * 2007-11-12 2008-05-08 Nitto Denko Corp Wiring circuit substrate
US8134080B2 (en) 2005-07-07 2012-03-13 Nitto Denko Corporation Wired circuit board
US8760815B2 (en) 2007-05-10 2014-06-24 Nitto Denko Corporation Wired circuit board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134080B2 (en) 2005-07-07 2012-03-13 Nitto Denko Corporation Wired circuit board
JP2007157836A (en) * 2005-12-01 2007-06-21 Nitto Denko Corp Printed circuit board
JP2008060263A (en) * 2006-08-30 2008-03-13 Nitto Denko Corp Wiring circuit board and its manufacturing method
US7723617B2 (en) 2006-08-30 2010-05-25 Nitto Denko Corporation Wired circuit board and production method thereof
US8266794B2 (en) 2006-08-30 2012-09-18 Nitto Denko Corporation Method of producing a wired circuit board
US8760815B2 (en) 2007-05-10 2014-06-24 Nitto Denko Corporation Wired circuit board
JP2008103745A (en) * 2007-11-12 2008-05-01 Nitto Denko Corp Method for manufacturing wired circuit substrate
JP2008109147A (en) * 2007-11-12 2008-05-08 Nitto Denko Corp Wiring circuit substrate

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