JPH07201198A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Static type R with redundant switching circuit
While stabilizing the operation of AM and the like, the average access time and cycle time are shortened. [Structure] A redundancy switching signal X is identified by identifying that a defective word line or defective bit line is designated by an address signal.
X selectively forming R0 to XR1 or YR0 to YR1
System redundancy switching circuit XR and Y system redundancy switching circuit YR
And a static RAM having an address transition detection circuit ATD which selectively detects the level transition of the address signal and selectively forms the address transition detection signals ATDX and ATD.
R0 to YR1 are input to the address transition detection circuit ATD to form the internal control signal even when the redundant word line or the like is in the selected state or the non-selected state to reactivate the internal circuit. , A redundant switching circuit XR and Y for selecting a normal word line without a failure.
The process proceeds without waiting for the result of the address identification operation by R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a static RAM having a redundant word line and a redundant bit line and an address transition detection circuit.
The present invention relates to a technology that is particularly effective when used for (random access memory).

[0002]

2. Description of the Related Art There is a static type RAM having a memory array in which static type memory cells are arranged in a lattice as a basic constituent element. Static RAM is
A redundant word line and a redundant bit line selectively assigned to the defective word line or defective bit line in which a failure is detected are provided, and the defective word line or defective bit line is designated by an externally supplied address signal. And a redundant switching circuit for selectively forming a redundant switching signal for identifying the redundant word line or the redundant bit line to bring it into a selected state. Further, the static RAM has a continuous mode in which a plurality of addresses can be continuously accessed by changing the address signal in the selected state, and includes an address transition detection circuit for identifying a level change of the address signal.

For a static RAM having a redundancy switching circuit and an address transition detection circuit, for example,
"IEEE JOURNAL OF SOLID ST
ATE CIRCUIT Oct. 1990, Vol.
25, No. 5, pp. 1049-1056 ".

[0004]

Prior to the present invention, the inventors of the present application have proposed the static type RA described above.
Based on M, we have developed a high-speed static RAM with a redundant switching circuit and address transition detection circuit. In this high-speed static RAM, the address transition detection circuit has an address signal AX0 as illustrated in FIG.
.About.AXi, AY0 to AYj and AZ0 to AZ1 and a chip selection signal CSB serving as a start control signal (here, so-called inverted signals etc. that are selectively brought to a low level when they are enabled are referred to by their names. B at the end
It is indicated by adding. The same applies to the following), and the falling transitions of these address signals and activation control signals are identified and the output signal thereof, that is, the address transition detection signal ATD, is temporarily set to the high level.

In the static RAM, word lines W0 to W are received in response to the high level of the address transition detection signal ATD.
The selection operation of m is started, and the address signals AX0 to AXi
The word line Wa designated by is brought into a selected state of high level. In addition, at a predetermined timing, the internal control signal BLE
Q and CDEQ are set to the low level, the equalization of the bit line and the common data line is stopped, and the internal control signal SD is set to the high level with a slight delay, and a sense amplifier for amplifying the read signal of the selected memory cell. Is activated. Corresponding complementary bit lines B0 * to B from a plurality of memory cells coupled to the selected word line
n * (Here, for example, the non-inverted bit line B0T and the inverted bit line B0B are combined to form a complementary bit line B0 *.
It is indicated by adding. Regarding so-called non-inverted signals, etc., which are selectively set to high level when it is enabled,
It is indicated by adding T to the end of the name. The same applies to the following), and the read signal is selectively transmitted from the Y switch to the sense amplifier via the read complementary common data lines CR0 * to CR7 *, and its output terminal, that is, the data input / output bus DB0 * to DB7 *. Is a high-level or low-level binary read signal. After being transmitted to the corresponding unit data output buffer of the data output buffer, the static type R is received from the corresponding data input / output terminals IO0 to IO7 in response to the high level of the output control signal DOC.
It is sent out of the AM.

By the way, the address signals AX0 to AXi,
The redundancy switching circuit compares AY0 to AYj and AZ0 to AZ1 with the address of the defective word line or defective bit line assigned to the redundant word line or redundant bit line. Then, when all the bits of these addresses match, as shown by the dotted line in FIG. 15, for example, the redundancy switching signal XR0 is set to the high level, and the redundant word line WR0 is selected instead of the designated word line Wa. It As is well known, the redundancy switching circuit includes an address comparing circuit having a relatively large number of logic stages, and it takes a relatively long time to determine the collation result, that is, the logic level of the redundancy switching signal XR0 or the like. Therefore, the time td from when the static RAM is activated until the internal control signal SD is set to the high level and the sense amplifier is driven.
Needs to be long enough to obtain a sufficient read signal amount .DELTA.V5 for the bit lines B0 * to Bn * even when the defect relief by the redundant word line WR0 or the like is performed, whereby the access time of the static RAM is high. Is limited.

On the other hand, in the continuous mode by detecting the address transition, for example, as shown in FIG.
X0-AXi, AY0-AYj and AZ0-AZ1
The address transition detection signal ATD is temporarily set to the high level in response to the change in the level of the signal.
Q and CDEQ are temporarily set to high level. Also,
After the internal control signal SD for driving the sense amplifier is set to the low level, it is set to the high level again at a predetermined timing. As described above, the redundancy switching circuit includes the address comparison circuit having a relatively large number of logical stages, and the redundancy switching signal X
It takes a relatively long time until the logic level such as R0 is determined. Further, the redundancy switching signal XR0 and the like are input to the first stage circuit as an inhibit signal for stopping the operation of the X address decoder and the like used for word line selection. Therefore, particularly when the selected word line is going to shift from the redundant word line WR0 or the like to the normal word line Wa or the like, it takes a relatively long time until the word line Wa or the like is selected instead of the redundant word line WR0 or the like. It takes a long time. As a result, the time td from when the static RAM is activated to when the internal control signal SD is set to the high level and the sense amplifier is driven is the bit line B0 * even when the selection operation of the word line Wa or the like is delayed. It is necessary to make the read signal amount .DELTA.V6 sufficient for .about.Bn * to be long, and this limits the speedup of the cycle time in the continuous mode of the static RAM.

An object of the present invention is to speed up the average access time and cycle time while stabilizing the read and write operations of a static RAM having a redundant word line and a redundant bit line. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a memory array including redundant word lines or redundant bit lines selectively assigned to the defective word line or defective bit line in which a failure is detected, and the defective word line or defective bit line is designated by an address signal. A redundant switching circuit for selectively forming a redundant switching signal for selecting a corresponding redundant word line or a redundant bit line and an internal activation signal by identifying a level change of an address signal or activation control signal. In a static RAM or the like, which includes an address transition detection circuit that selectively forms a signal and a timing generation circuit that selectively forms a predetermined internal control signal for receiving an internal startup signal and bringing the internal circuit into a startup state, The redundancy switching signal output from the redundancy switching circuit is input to the address transition detection circuit, and the redundancy word line or redundant When the bit line is selected or unselected, the internal circuit is activated again, and the selection operation related to the normal word line or normal bit line in which no fault is detected is selected by the redundancy switching circuit. Proceed without waiting for the result of.

[0011]

According to the above-mentioned means, the static RAM is provided only when the redundant word line or the redundant bit line is selected or in the continuous mode, the redundant word line or the redundant bit line is shifted to the selected state or the non-selected state. Since it is possible to speed up the selection operation for the normal word line and the normal bit line by redoing the operations such as, the average access time and cycle time while stabilizing the read and write operations of the static RAM and the like. Can be speeded up.

[0012]

1 is a block diagram of an embodiment of a static RAM to which the present invention is applied. An outline of the configuration and operation of the static RAM of this embodiment will be described first with reference to FIG. The circuit elements forming each block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

In FIG. 1, the static RAM of this embodiment has four memory arrays ARY0 to ARY3 divided in the word line extension direction as its basic constituent elements. To these memory arrays, corresponding mat selection signals M0 to M3 are respectively supplied from a mat selection circuit MS described later, and internal control signals WD and BLEQ (first internal control signal) are commonly supplied from the timing generation circuit TG. To be done.

The memory arrays ARY0 to ARY3 have m + 1 subword lines arranged in parallel in the horizontal direction of the figure, n + 1 sets of complementary bit lines arranged in parallel in the vertical direction, and these subword lines and And (m + 1) × (n + 1) static memory cells arranged in a grid pattern at the intersections of complementary bit lines. Each of memory arrays ARY0 to ARY3 includes m + 1 sub word line drive circuits provided corresponding to the sub word lines and n + 1 bit line load circuits provided corresponding to the complementary bit lines. Memory array ARY0 to ARY3
In the upper layer of the sub-word lines constituting the above, m + 1 main word lines are extended to skew these memory arrays, and the left end thereof is coupled to the X address decoder XD.

In this embodiment, the memory array ARY
0 to ARY3 each include, but are not particularly limited to, two redundant subword lines, and two redundant main word lines corresponding to the redundant subword lines are extended above the redundant subword lines. In addition, the memory arrays ARY0 and ARY1
Further includes eight sets of redundant bit lines, and memory arrays ARY2 and ARY3 do not include redundant bit lines. In FIG. 1, the two redundant sub word lines and the redundant main word lines are shown by dotted lines as redundant word lines WR0 and WR1, and eight sets of redundant bit lines are shown by dotted lines as redundant bit line groups BRG0 and BRG1. Has been done. In the following description, redundant word lines WR0 and WR1 may represent redundant sub word lines and redundant main word lines, and redundant bit line groups BRG0 and BRG1 may represent redundant bit lines.

The sub-word lines and redundant sub-word lines forming memory arrays ARY0 to ARY3 are coupled to corresponding sub-word line drive circuits. These sub-word line drive circuits are selectively operated in response to the high level of the internal control signal WD, the corresponding main word line or redundant main word line is set to the low level, and the corresponding mat selection signals M0 to M3 are set. On condition that it is set to the high level, the corresponding sub-word line or redundant sub-word line is selectively set to the high-level selected state.

The X address decoder XD has an i + 1 bit internal address signal X0 from the X address buffer XB.
~ Xi is supplied. Further, the internal control signal CS1 is supplied from the timing generation circuit TG, and the redundancy switching signals XR and XR0 and XR are supplied from the X system redundancy switching circuit XR.
R1 is supplied. On the other hand, the X-system redundancy switching circuit XR is supplied with the internal address signals X0 to Xi from the X address buffer XB and the internal control signals CS1B and CS2 from the timing generation circuit TG. Further, the X address buffer XB has X address signals AX0 to AXi via address input terminals AX0 to AXi.
Xi is supplied.

The X address buffer XB has an address input terminal A when the static RAM is selected.
X address signal AX0 supplied via X0 to AXi
.About.AXi are fetched and held, internal address signals X0 to Xi are formed based on these X address signals, and are supplied to X address decoder XD, X system redundancy switching circuit XR and address transition detection circuit ATD.

On the other hand, the X system redundancy switching circuit XR has a low level of the internal control signal CS1B and the internal control signal C.
The address of the defective word line assigned to the redundant word lines WR0 and WR1 and the internal address signals X0 to Xi are compared and collated bit by bit in response to the high level of S2. When all these bits match, the corresponding redundancy switching signal XR0
Alternatively, XR1 is selectively set to the high level, and the redundancy switching signal XR is also set to the high level. The specific configuration of the X system redundancy switching circuit XR will be described later in detail.

The X address decoder XD is selectively operated in response to the high level of the internal control signal CS1.
The internal address signals X0 to Xi supplied from the X address buffer XB are decoded, and the corresponding one main word line is selectively set to a low level selected state such as the ground potential of the circuit. When the redundancy switching signal XR is at a high level, the selection operation of the X address decoder XD for the normal main word line is prohibited, and instead, the redundant main word line corresponding to the redundancy switching signal XR0 or XR1 is alternatively selected. The low level is selected.

Next, the complementary bit lines and the redundant bit lines forming the memory arrays ARY0 to ARY3 are respectively coupled to corresponding bit line precharge circuits (not shown) above the Y-switch YS.
0-YS3 corresponding switch MOSFET (metal oxide semiconductor type field effect transistor. In this specification, M
The OSFET is collectively referred to as an insulated gate field effect transistor). Corresponding mat select signals M0 to M3 are commonly supplied to the bit line precharge circuit, and the internal control signal B is also supplied.
LEQ is commonly supplied. In addition, Y switch YS0
YS3 has corresponding Y address decoders YD0 to YD
A read bit line selection signal and a write bit line selection signal of a predetermined bit are supplied from 3.

Three bit line precharge circuits are provided between the non-inverted and inverted signal lines of the corresponding complementary bit line or redundant bit line and between these non-inverted and inverted signal lines and the power supply voltage of the circuit. P-channel type precharge MOSFET. These precharge MOSFETs are selectively turned on when the internal control signal BLEQ is set to the high level and the corresponding mat selection signals M0 to M3 are set to the high level, and the corresponding complementary bit line or redundant bit line The non-inverted or inverted signal line is equalized to a high level like the power supply voltage of the circuit.

On the other hand, the Y switches YS0 to YS3 respectively include N channel type and P channel type switch MOSFETs provided corresponding to the complementary bit lines of the memory arrays ARY0 to ARY3. Of these, the other of the N-channel type switch MOSFETs is not shown.
Every other pair of write complementary common data lines for writing is commonly connected in common. Further, the gates thereof are sequentially commonly connected in pairs of eight, and corresponding write bit line selection signals are commonly supplied from the Y address decoders YD0 to YD3. Similarly, the other of the P-channel type switch MOSFETs is sequentially and commonly coupled to the eight sets of complementary complementary common data lines for every eight pairs. Further, the gates thereof are sequentially commonly connected in pairs of eight, and corresponding read bit line selection signals are commonly supplied from the Y address decoders YD0 to YD3.

As a result, each of the N-channel type switch MOSFETs forming the Y switches YS0 to YS3 is selectively turned on by 8 pairs by setting the corresponding write bit line selection signal to the high level.
The eight complementary bit lines and the write complementary common data line designated in the corresponding memory arrays ARY0 to ARY3 are selectively connected. Similarly, Y switch YS
0-YS3 P-channel type switch MOS
The FETs are selectively turned on by 8 pairs each when the corresponding read bit line selection signal is set to a high level, and the 8 sets of complementary bit lines and complementary read lines designated in the corresponding memory arrays ARY0 to ARY3 are complemented. The connection with the common data line is selectively set.

The Y address decoders YD0 to YD3 include
Internal address signals Y0 to Yj of j + 1 bits are commonly supplied from Y address buffer YB, and internal control signal CS2 is commonly supplied from timing generation circuit TG. Further, the redundancy switching signal Y from the Y-system redundancy switching circuit YR
R is commonly supplied, and the corresponding mat selection signals M0 to M3 are supplied from the mat selection circuit MS. The Y address decoders YD0 and YD1 are further provided with corresponding redundancy switching signals YR0 from the Y system redundancy switching circuit YR.
And YR1 are respectively supplied. On the other hand, the Y-system redundancy switching circuit YR is supplied with the internal address signals Y0 to Yj from the Y address buffer YB and the 2-bit internal address signal Z from the Z address buffer ZB.
0 to Z1 are supplied, and the internal control signals CS1B and CS2 are supplied from the timing generation circuit TG. Further, the Y address buffer YB has address input terminals AY0 to AY.
Y address signals AY0 to AYj are supplied via Yj, and the Z address buffer ZB has an address input terminal A
Z address signals AZ0 to AZ1 are supplied via Z0 to AZ1. Further, in the mat selection circuit MS, the internal address signals Z0 to Z1 from the Z address buffer ZB are input.
And the internal control signal CS1B is supplied from the timing generation circuit TG.

The Z address buffer ZB has an address input terminal A when the static RAM is in the selected state.
Z address signal AZ0 supplied via Z0 to AZ1
To AZ1 are fetched and held, and internal address signals Z0 to Z1 are formed on the basis of these Z address signals to generate a mat selection circuit MS and an address transition detection circuit A.
Supply to TD. The mat selection circuit MS is selectively activated by receiving the low level of the internal control signal CS1B, and decodes the internal address signals Z0 to Z1 to selectively output the corresponding mat selection signals M0 to M3 at a high level. And

On the other hand, the Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied via the address input terminals AY0 to AYj when the static RAM is in the selected state, and at the same time, these Y addresses are stored. Internal address signals Y0 to Yj based on the address signal
To form Y address decoders YD0 to YD3, Y system redundancy switching circuit YR and address transition detection circuit ATD.
Supply to. Further, the Y-system redundancy switching circuit YR is selectively brought into an operating state in response to the low level of the internal control signal CS1B and the high level of the internal control signal CS2, and the defective bit lines assigned to the redundant bit line groups BRG0 and BRG1. The address and the internal address signals Y0 to Yj and Z0 to Z1 are compared and collated bit by bit. When all the bits of these addresses match, the corresponding redundancy switching signal YR0 or YR1 is selectively set to the high level, and the redundancy switching signal YR is also set to the high level. The specific configuration of the Y-system redundancy switching circuit YR will be described later in detail.

The Y address decoders YD0 to YD3 are selectively activated by setting the internal control signal CS2 to the high level and the corresponding mat selection signals M0 to M3 to the high level. The supplied internal address signals Y0 to Yj are decoded to selectively set the write or read bit line selection signal to a high level under a predetermined condition. When the redundancy switching signal YR is set to the high level, the bit line selecting operation by the Y address decoders YD0 to YD3 is selectively prohibited, and instead, the redundancy switching signal YR0 or YR1.
The redundant bit line group BRG0 or BRG1 corresponding to is selectively selected.

In the address transition detection circuit ATD, as described above, the internal address signals X0 to Xi, Y0 to Yj and Z0 to Z1 from the X address buffer XB, Y address buffer YB and Z address buffer ZB are used.
Is supplied, and the redundancy switching signal XR0 is supplied from the X-system redundancy switching circuit XR and the Y-system redundancy switching circuit YR.
To XR1 and YR0 to YR1, and an internal control signal CS2B from the timing generation circuit TG. The address transition detection circuit ATD discriminates the level changes of the internal address signal, the redundancy switching signal and the internal control signal, and selectively and temporarily sets the internal activation signal, that is, the address transition detection signals ATDX and ATD to the high level. To do. These address transition detection signals ATDX and ATD are supplied to the timing generation circuit TG. The specific configuration of the address transition detection circuit ATD will be described later in detail.

Memory array ARY in read mode
The eight sets of complementary common data lines for writing, to which the eight sets of complementary bit lines designated by 0 to ARY3 are selectively connected, are respectively coupled to the output terminals of the corresponding unit write amplifiers of the write amplifiers WA0 to WA3. To be done. Further, in the write mode, the eight complementary complementary common data lines for reading, which are selectively connected to the eight complementary bit lines designated in the memory arrays ARY0 to ARY3, are the sense amplifier S.
They are respectively coupled to the input terminals of the corresponding unit sense amplifiers of A0 to SA3.

The write amplifiers WA0 to WA3 each include eight unit write amplifiers provided corresponding to the write complementary common data lines. Input terminals of these unit write amplifiers correspond to corresponding data input / output buses DB0 * to D0.
B7 *, the output terminal of which is coupled to the corresponding write complementary common data line as described above. Each unit write amplifier of the write amplifiers WA0 to WA3 has a corresponding mat selection signal M0 to M from the mat selection circuit MS.
3 are respectively supplied, and an internal control signal WP (not shown) is commonly supplied from the timing generation circuit TG.

On the other hand, the sense amplifiers SA0 to SA3 each include eight unit sense amplifiers provided corresponding to the read complementary common data lines. The input terminals of these unit sense amplifiers are coupled to the corresponding read complementary common data lines as described above, and the output terminals thereof are coupled to the corresponding data input / output buses DB0 * to DB7 *, respectively. Each unit sense amplifier of the sense amplifier SA has an internal control signal CDEQ from the timing generation circuit TG.
(Second internal control signal) and SD (third internal control signal) are commonly supplied, and corresponding mat selection signals M0 to M3 are respectively supplied from the mat selection circuit MS. Data input / output buses DB0 * to DB7 * are coupled to the output terminals of the corresponding unit data input buffers of data input buffer IB and the input terminals of the corresponding unit data output buffers of data output buffer OB.
An internal control signal DOC is commonly supplied from the timing generation circuit TG to each unit data output buffer of the data output buffer OB.

Each unit data input buffer of the data input buffer IB has a corresponding data input / output terminal IO when the static RAM is selected in the write mode.
The write data supplied via 0 to IO7 is fetched and transmitted to the corresponding unit write amplifier of the write amplifiers WA0 to WA3 via the data input / output buses DB0 * to DB7 *. At this time, each of the unit write amplifiers of the write amplifiers WA0 to WA3 is selectively activated by setting the internal control signal WP to the high level and the corresponding mat selection signals M0 to M3 to the high level. The write data transmitted from the corresponding unit data input buffer of the input buffer IB via the data input / output buses DB0 * to DB7 * is converted into a predetermined complementary write signal, and then the corresponding write complementary common data line is switched to the Y switch YS.
Writing is performed on the selected eight memory cells of the memory arrays ARY0 to ARY3 via 0 to YS3.

On the other hand, in the unit sense amplifiers forming the sense amplifiers SA0 to SA3, when the static RAM is selected in the read mode, the internal control signal SD is set to the high level and the corresponding mat selection signals M0 to M are generated.
When 3 is set to a high level, the read signal output from the selected eight memory cells of the memory arrays ARY0 to ARY3 via the corresponding complementary complementary common data lines is amplified. After that, the data is transmitted to the corresponding unit data output buffer of the data output buffer OB via the data input / output buses DB0 * to DB7 *. At this time, each unit data output buffer of the data output buffer OB is selectively activated by receiving the high level of the output control signal DOC, and the sense amplifiers SA0-S0.
The read signal output from the unit sense amplifier corresponding to A3 is sent to the outside of the static RAM from the corresponding data input / output terminals IO0 to IO7.

In this embodiment, the sense amplifier SA0
Each unit sense amplifier of SA3 to SA3 includes eight common data line precharge circuits provided corresponding to the respective complementary common data lines for reading, and each of these common data line precharge circuits corresponds to the corresponding read. It includes three P-channel type precharge MOSFETs provided between the non-inverted and inverted signal lines of the complementary common data line for use and between the non-inverted and inverted signal lines and the power supply voltage of the circuit, respectively. These precharge MOSFE
T is selectively turned on when the internal control signal CDEQ is set to the high level and the corresponding mat selection signals M0 to M3 are set to the high level, and the non-inversion or inversion signal of the corresponding read complementary common data line is read. The line is equalized to a high level like the power supply voltage of the circuit.

The timing generation circuit TG has a chip selection signal CSB, a write enable signal WEB and an output enable signal OEB which are externally supplied as a start control signal.
And an internal activation signal supplied from the address transition detection circuit ATD, that is, the address transition detection signals ATDX and ATD.
Based on the above, the various internal control signals are selectively formed and supplied to each part of the static RAM.

FIG. 2 is a block diagram of an embodiment of the X system redundancy switching circuit XR included in the static RAM of FIG. Further, FIG. 3 shows an X system redundant address memory X included in the X system redundant switching circuit XR of FIG.
A circuit diagram of an embodiment of RM0 and X system redundancy enable circuit XEN0 is shown, and FIG. 4 shows an X system redundant address comparison circuit XRC0 included in the X system redundancy switching circuit XR of FIG.
A circuit diagram of one embodiment is shown. Based on these figures, the specific configuration and operation of the X-system redundancy switching circuit XR included in the static RAM of this embodiment will be described. In the circuit diagram below, the MOSFET with an arrow on its channel (back gate) is P
It is a channel type and is shown in distinction from an N-channel MOSFET without an arrow. Further, the following description regarding the X-system redundant address memory, the X-system redundant enable circuit, and the X-system redundant address comparison circuit is given in the redundant word line WR.
X system redundant address memory XRM provided corresponding to 0
0, X system redundant enable circuit XEN0 and X system redundant address comparison circuit XRC0 will be taken as an example, but redundant word line W
X system redundant address memory XR provided corresponding to R1
The M1, X system redundant enable circuit XEN1 and X system redundant address comparison circuit XRC1 have the same configuration as these circuits, and therefore, analogy should be made.

In FIG. 2, the X system redundancy switching circuit XR
Is an X system redundant address memory XRM0 and an X system redundant enable circuit XE provided corresponding to the redundant word line WR0.
N0 and X system redundant address comparison circuit XRC0, and X system redundant address memory XRM1 and X system redundancy enable circuits XEN1 and X provided corresponding to redundant word line WR1.
System redundant address comparison circuit XRC1. this house,
An internal control signal CS1B is commonly supplied to the X system redundant enable circuits XEN0 and XEN1, and an internal control signal C is supplied to the X system redundant address comparison circuits XRC0 and XRC1.
S2 is commonly supplied. Further, one of the address input terminals of the X system redundant address comparison circuits XRC0 and XRC1 has a corresponding X system redundant address memory XRM0 or XR.
Redundant address signals RX00 to R of 1 + 1 bits from M1
X0i and RX10 to RX1i are respectively supplied, and the other address input terminal receives the internal address signal X0 of i + 1 bit from the X address buffer XB.
~ Xi are commonly supplied. The X-system redundant address comparison circuits XRC0 and XRC1 further include output signals XEN0 of the corresponding X-system redundancy enable circuits XEN0 and XEN1.
, And XEN1 are respectively supplied. The output signals of the X system redundant address comparison circuits XRC0 and XRC1 are used as the redundancy switching signals XR0 and XR1 in the X address decoder X.
It is supplied to the D and address transition detection circuit ATD, and also becomes a redundancy switching signal XR via the OR gate OG1 and is supplied to the X address decoder XD.

Here, the X-system redundancy enable circuit XEN0
And XEN1 are X system redundancy enable circuits XEN of FIG.
As represented by 0, the fuse F1, P-channel MOSFETs P1 and P2, and the inverter V1.
And a fuse circuit FC composed of V2. this house,
The internal control signal CS1 is applied to the gate of the MOSFET P1.
B is provided and its source is coupled to the power supply voltage of the circuit. The drain is coupled to the circuit ground potential via the fuse F1 and is coupled to the circuit power supply voltage via the MOSFET P2.
1 input terminal. On the other hand, the gate of MOSFET P2 is coupled to the output terminal of inverter V1 and its source is coupled to the power supply voltage of the circuit. The output signal of the inverter V1 is inverted by the inverter V2 and then supplied to the X system redundant address comparison circuit XRC0 as the output signal XEN0 of the X system redundant enable circuit XEN0. It should be noted that the fuse F1 has a defective word line assigned to the corresponding redundant word line WR0 and is in use.
Selectively disconnected.

As a result, the X system redundancy enable circuit XE
The output signal XEN0 of N0 is used when the corresponding fuse F1 is not in the cut state, that is, the corresponding redundant word line WR0.
Is not in use, it is constantly set to a low level like the ground potential of the circuit, and when the corresponding fuse F1 is in a cut state, that is, the corresponding redundant word line WR0 is assigned to the defective word line in which a failure is detected. When in use, it is set to a high level like the power supply voltage of the circuit.
The cut state of the fuse F1 depends on the chip selection signal CS.
When the static RAM is brought into the selected state in response to the low level of B and the internal control signal CS1B is set to the low level, the determination is made, and the result is determined by the inverter V1 and the MOSF.
It is held in the latch circuit composed of ETP2.

On the other hand, the X system redundant address memories XRM0 and XRM1 are the X system redundant address memories XRM0 of FIG.
Typified by the above, the fuse circuit includes i + 1 fuse circuits FC provided corresponding to the internal address signals X0 to Xi, that is, the X address signals AX0 to AXi. When the corresponding bit of the defective address assigned to the line WR0 is set to the logic "1", the disconnection state is selectively established. As a result, the redundant address signals RX00 to RX0i output from the X system redundant address memory XRM0 are set to a high level when the corresponding bit of the defective address assigned to the corresponding redundant word line WR0 is logical "1". When it is set to logic "0", it is set to low level.

Next, the X system redundant address comparison circuit XRC0
And XRC1 are the X-system redundant address comparison circuits XR of FIG.
As represented by C0, i + 1 unit address comparison circuits UC each including two complementary gates G1 and G2 and output signals of the unit address comparison circuits UC at the third to i + 3th input terminals thereof. AND gate AG1 of substantially i + 3 input for receiving x0 to xi. Among them, the corresponding internal address signals X0 to Xi are supplied to the input terminals of the complementary gate G2, and the complementary gate G
Inverted signals from the inverter V3 are supplied to the input terminals of No. 1 respectively. Corresponding redundant address signals RX00 to RX0i are respectively supplied to the gates of the P-channel MOSFET forming the complementary gate G1 and the N-channel MOSFET forming the complementary gate G2, and the N-channel MOS forming the complementary gate G1.
An inverted signal from the inverter V4 is supplied to the gates of the FETs and the P-channel MOSFETs forming the complementary gate G2. Complementary gates G1 and G
The two output terminals are commonly coupled to form the corresponding internal nodes x0 to xi. The internal control signal CS2 and the output signal XEN0 of the X system redundancy enable circuit XEN0 are supplied to the first and second input terminals of the AND gate AG1, respectively, and the output signal becomes the redundancy switching signal XR0.

From these facts, the output signals x0 to xi of each unit address comparison circuit UC forming the X system redundant address comparison circuit XRC0 are the same as the corresponding internal address signal X0.
To Xi are at a high level, that is, a logical "1" and corresponding redundant address signals RX00 to RX0i are at a high level, that is, a logical "1", or the corresponding internal address signals X0 to Xi are at a low level, that is, a logical "0". And corresponding redundant address signals RX00 to RX0i
Is set to a low level, that is, a logical "0", that is, when the logical levels of the corresponding bits of the internal address signals X0 to Xi and the redundant address signals RX00 to RX0i match, the signal is selectively set to a high level. Then, output signals x0 to xi of these unit address comparison circuits UC
Are all set to a high level, in other words, the X address signal AX supplied from the outside at the time of access
When the defective addresses assigned to the redundant word line WR0 corresponding to 0 to AXi match all bits, the internal control signal CS2 is set to the high level and the output signal XEN0 of the X system redundant enable circuit XEN0 is set to the high level. On the condition that the static RAM is in the selected state and the corresponding redundant word line WR0 is in the used state, the output signal of the AND gate AG1, that is, the redundancy switching signal XR0 is selectively set to the high level. It

FIG. 5 is a block diagram showing an embodiment of the Y-system redundancy switching circuit YR included in the static RAM shown in FIG. Further, FIG. 6 shows a Y-system redundant address memory Y included in the Y-system redundant switching circuit YR of FIG.
A circuit diagram of an embodiment of RM0 and Y system redundancy enable circuit YEN0 is shown, and FIG. 7 shows a Y system redundancy address comparison circuit YRC0 included in the Y system redundancy switching circuit YR of FIG.
A circuit diagram of one embodiment is shown. Based on these figures, the specific configuration and operation of the Y-system redundancy switching circuit YR included in the static RAM of this embodiment will be described. In the following description of the Y-system redundant address memory, the Y-system redundant enable circuit, and the Y-system redundant address comparison circuit, the Y-system redundant address memory YRM0 and the Y-system redundant enable circuit YEN0 provided corresponding to the redundant bit line group BRG0. And Y-system redundant address comparison circuit YRC0
As an example, the Y-system redundant address memory YRM1, the Y-system redundant enable circuit YEN1 and the Y-system redundant address comparison circuit Y provided corresponding to the redundant bit line group BRG1.
Since RC1 has the same configuration as each of these circuits, analogy should be made. Further, since the Y-system redundant switching circuit YR has basically the same configuration as that of the X-system redundant switching circuit XR shown in FIGS. 2 to 4, description will be added only to the different parts.

In FIG. 5, the Y-system redundancy switching circuit YR
Is a Y-system redundant address memory YRM0, a Y-system redundant enable circuit YEN0 and a Y-system redundant address comparison circuit YRC0 provided corresponding to the redundant bit line group BRG0, and a Y-system redundancy provided corresponding to the redundant bit line group BGR1. Address memory YRM1, Y system redundancy enable circuit YEN
1 and a Y-system redundant address comparison circuit YRC1. Of these, the Y-system redundant enable circuits YEN0 and YEN1 are commonly supplied with the internal control signal CS1B, and the Y-system redundant address comparison circuits YRC0 and YRC1 are commonly supplied with the internal control signal CS2. Further, the redundant address signals RY00 to RY0j and RY10 to RY1j are respectively supplied from the corresponding Y system redundant address memory YRM0 or YRM1 to one address input terminal of the Y system redundant address comparison circuits YRC0 and YRC1 and the other address is supplied. The input terminal has the Y address buffer Y
Internal address signals Y0 to Yj are commonly supplied from B. Output signals YEN0 and YEN1 of the corresponding Y system redundancy enable circuits YEN0 and YEN1 are further supplied to the Y system redundant address comparison circuits YRC0 and YRC1, respectively. Y system redundant address comparison circuits YRC0 and Y
The output signal of RC1 is the redundancy switching signals YR0 and YR.
It is supplied to the Y address decoders YD0 and YD1 and the address transition detection circuit ATD as 1 and becomes the redundancy switching signal YR via the OR gate OG2, and Y
It is supplied to the address decoders YD0 to YD3.

Here, the Y-system redundancy enable circuit YEN0
And YEN1 are the Y-system redundancy enable circuits YEN of FIG.
As represented by 0, each includes a fuse circuit FC, and its output signal YEN0 is steady when the corresponding fuse F1 is not in a cut state, that is, when the corresponding redundant bit line group BRG0 is not in a used state. Is set to a low level like the ground potential of the circuit, and the corresponding fuse F
When 1 is in a disconnection state, that is, when the corresponding redundant bit line group BRG0 is assigned to a defective bit line in which a failure is detected, it is set to a high level like the power supply voltage of the circuit.

On the other hand, the Y system redundant address memories YRM0 and YRM1 are the Y system redundant address memories YRM0 of FIG.
Internal address signals Y0 to Y
j, that is, j + 1 fuse circuits FC provided corresponding to the Y address signals AY0 to AYj, and the output signal, that is, the redundant address signals RY00 to RY0j, corresponds to the defective address assigned to the corresponding redundant bit line group BRG0. When the bit to be set is logic "1", it is selectively set to high level.

Next, the Y-system redundant address comparison circuit YRC0
And YRC1 are the Y-system redundant address comparison circuits YR of FIG.
As represented by C0, j + 1 unit address comparison circuits UC, the internal control signal CS2 at the first and second input terminals thereof and the corresponding Y system redundancy enable circuit YEN0.
Output signal YEN0 of each of the third to jth
The input terminal of +3 includes a substantially j + 3 input AND gate AG2 which receives the output signals y0 to yj of each unit address comparison circuit UC, respectively. As a result, each unit address comparison circuit U forming the Y-system redundant address comparison circuit YRC0
The output signals y0 to yj of C are the internal address signals Y0 to Y.
When j and the corresponding bits of the redundant address signals RY00 to RY0j match, it is selectively set to the high level. When the output signals y0 to yj of these unit address comparison circuits UC are all set to a high level, in other words, the redundant bit line group B corresponding to the Y address signals AY0 to AYj externally supplied at the time of access.
When all bits of the defective address assigned to RG0 match, the internal control signal CS2 is set to the high level and the output signal YEN0 of the Y-system redundancy enable circuit YEN0 is set to the high level, that is, the static type. On condition that the RAM is in the selected state and the corresponding redundant bit line group BGR0 is in the used state, the output signal of the AND gate AG2, that is, the redundancy switching signal YR0 is selectively set to the high level.

FIG. 8 is a block diagram showing an embodiment of the address transition detection circuit ATD included in the static RAM shown in FIG. 9 and 10 are circuit diagrams of one embodiment of the unit address transition detection circuit TDX0 and the address transition detection signal generation circuit ATDG included in the address transition detection circuit ATD of FIG. 8, respectively. Based on these figures, the specific configuration and operation of the address transition detection circuit ATD included in the static RAM of this embodiment will be described. In the following description of the unit address transition detection circuit, the unit address transition detection circuit TDX0 will be taken as an example, but the other unit address transition detection circuits TDX1 to TDXi, TDX0B to TDX.
iB, TDY0 to TDYj, TDY0B to TDYjB,
TDZ0 to TDZ1, TDZ0B to TDZ1B, TDC
SB, TDXR0 to TDXR1, TDXR0B to TDX
R1B, TDYR0 to TDYR1 and TDYR0B
~ TDYR1B has the same configuration as this, so please analogize it.

In FIG. 8, the address transition detection circuit AT
D is an i + 1 unit address transition detection circuit TD which receives the internal address signals X0 to Xi at its input terminals.
Included are X0 to TDXi and unit address transition detection circuits TDX0B to TDXiB whose input terminals receive inverted signals of these internal address signals, respectively, and j + 1 which receives internal address signals Y0 to Yj at their input terminals.
Individual unit address transition detection circuits TDY0 to TDYj,
Unit address transition detection circuits TDY0B to TDY0B, which receive the inverted signals of these internal address signals at their input terminals
And TDYjB. Further, two unit address transition detection circuits TDZ0 to TDZ1 which receive the internal address signals Z0 to Z1 respectively at their input terminals, and unit address transition detection circuits TDZ0B to TDZ0B to which the inverted signals of these internal address signals are respectively received at their input terminals. TDZ1B and a unit address transition detection circuit TDCSB which receives the internal control signal CS2B at its input terminal. In this embodiment, the address transition detection circuit ATD further includes two unit address transition detection circuits TDXR0 to TDX that receive the redundancy switching signals XR0 to XR1 at their input terminals.
XR1 and a unit address transition detection circuit T for receiving an inversion signal of these redundancy switching signals at its input terminal, respectively.
DXR0B to TDXR1B, and two unit address transition detection circuits TDYR0 to TDYR1 which respectively receive the redundancy switching signals YR0 to YR1 at their input terminals.
A unit address transition detection circuit TDYR0B which receives the inverted signals of these redundancy switching signals at its input terminals.
To TDYR1B.

Output signals of each unit address transition detection circuit, that is, unit address transition detection signals TDX0 to TDXi, T
DX0B to TDXiB, TDY0 to TDYj, TDY0
B to TDYjB, TDZ0 to TDZ1, TDZ0B to T
DZ1B, TDCSB, TDXR0 to TDXR1, TD
XR0B to TDXR1B, TDYR0 to TDYR1 and TDYR0B to TDYR1B are respectively supplied to the corresponding input terminals of the address transition detection signal generation circuit ATDG. This address transition detection signal generation circuit ATDG
Is supplied to the timing generation circuit TG as an internal activation signal, that is, the address transition detection signals ATDX and ATD.

Here, the unit address transition detection circuits TDX0 to TDXi, which form the address transition detection circuit ATD,
TDX0B to TDXiB, TDY0 to TDYj, TDY
0B ~ TDYjB, TDZ0 ~ TDZ1, TDZ0B ~
TDZ1B, TDCSB, TDXR0 to TDXR1, T
DXR0B to TDXR1B, TDYR0 to TDYR1 and TDYR0B to TDYR1B are represented by the unit address transition detection circuit TDX0 of FIG.
NOR gate NO6 receiving internal address signal X0 corresponding to one of the input terminals is included. This NOR gate NO6
The other input terminal is supplied with the inverted delay signal DX0B of the internal address signal X0 through a delay circuit including an inverter V6, delay inverters DV1 to DV3, and NOR gates NO3 to NO5. Also, NOR gate NO
The output signal of 6 is supplied as a unit address transition detection signal TDX0 to the corresponding input terminal of the address transition detection signal generation circuit ATDG. The delay inverters DV1 to DV1
Five N-channel MOSFETs provided in series on the ground potential side of the DV3 circuit are selectively enabled by the master slice to meet the desired delay time.

As a result, the unit address transition detection circuit T
Output signal of DX0, that is, unit address transition detection signal TD
X0 is the inverter V6 and the delay inverter DV1 after the corresponding internal address signal X0 and the inverted delay signal DX0B are both set to the low level, in other words, after the corresponding internal address signal X0 is changed to the low level.
-DV3 and NOR gates NO3-NO5 are temporarily set to a high level until the delay time elapses. In short, the address transition detection circuit ATD
Each unit address transition detection circuit that constitutes a unit address transition detecting circuit detects a corresponding address signal, a redundancy switching signal, an internal control signal, or an inverted signal thereof from a high level to a low level, and outputs a unit address transition having a predetermined pulse width. The detection signal is selectively formed. Particularly, with respect to the redundancy switching signals XR0 to XR1 and YR0 to YR1, the rising edge thereof, that is, the time when the corresponding redundant word line or redundant bit line is in the selected state and its falling edge. That is, the corresponding unit address transition detection signal is temporarily set to the high level both when the redundant word line or the redundant bit line is released from the selected state.

Next, the address transition detection signal generation circuit AT
As shown in FIG. 10, the DG is the OR circuit ORC1.
~ ORC3 and OR gates OG3 and OG4. Of these, the OR circuit ORC1 includes the unit address transition detection circuits TDX0 to TDXi and TDX0B to TDX.
iB, TDZ0 to TDZ1 and TDZ0B to TDZ
1B to its output signal, that is, unit address transition detection signals TDX0 to TDXi, TDX0B to TDXiB, TDZ.
0-TDZ1 and TDZ0B-TDZ1B are supplied. The OR circuit ORC2 includes unit address transition detection circuits TDXR0 to TDXR1 and TDXR0B to T.
DXR1B, TDYR0 to TDYR1 and TDYR
0B to TDYR1B to output signals thereof, that is, unit address transition detection signals TDXR0 to TDXR1, TDXR0B
~ TDXR1B, TDYR0 to TDYR1 and TD
YR0B to TDYR1B are supplied to the OR circuit ORC
3 includes unit address transition detection circuits TDY0 to TDY.
j, TDY0B to TDYjB and TDCSB to output signals thereof, that is, unit address transition detection signals TDY0 to TDY0.
TDYj, TDY0B to TDYjB and TDCSB
Is supplied.

Here, OR circuits ORC1 to ORC3
Includes a plurality of N-channel MOSFETs provided in parallel between internal node n1 and the ground potential of the circuit, as represented by OR circuit ORC1 in FIG. The gates of these MOSFETs have corresponding unit address transition detection signals TDX0 to TDXi, TDX0B.
-TDXiB, TDZ0-TDZ1 and TDZ0B
~ TDZ1B or corresponding unit address transition detection signal T
DXR0 to TDXR1, TDXR0B to TDXR1B,
TDYR0 to TDYR1 and TDYR0B to TDY
R1B or corresponding unit address transition detection signal TD
Y0 to TDYj, TDY0B to TDYjB and TD
Each CSB is supplied. Hereinafter, the OR circuit ORC
1, the specific description of the OR circuits ORC1 to ORC3 will be continued.

The OR circuit ORC1 further includes two P-channel MOSFETs P3 and P4 provided in parallel between the power supply voltage of the circuit and the internal node n1. Of these, MOSFET P3 has a relatively small conductance, and its gate is coupled to the output terminal of the inverter V7. MOSFET P4 also has a relatively large conductance, and its gate is coupled to the output terminal of inverter V8. The input terminal of inverter V7 is coupled to internal node n1, and the input terminal of inverter V8 is coupled to the output terminal of inverter V7. The internal node n1 is further coupled to the input terminal of the inverter V9, and the output signal of the inverter V9 has an OR circuit O
It becomes the output signal of RC1, that is, the internal signal ATDX1.

Unit address transition detection signals TDX0 to TD
When Xi, TDX0B to TDXiB, TDZ0 to TDZ1 and TDZ0B to TDZ1B are all set to the low level, in the OR circuit ORC1, all parallel N-channel MOSFETs are turned off. Therefore, the internal node n1 is set to a high level like the power supply voltage of the circuit through the MOSFET P3 having a relatively small conductance, and the internal node n1 receives the high level to output the output signal of the OR circuit ORC1, that is, the internal signal ATD.
X1 is set to low level.

On the other hand, in response to the level change of the internal address signals X0 to Xi or Z0 to Z1, the unit address transition detection signals TDX0 to TDXi, TDX0B to TDXiB,
When any one of TDZ0 to TDZ1 and TDZ0B to TDZ1B is temporarily set to the high level, the corresponding parallel N-channel MOSFET is temporarily turned on. Therefore, the internal node n1 is set to the low level via the N-channel MOSFET, which causes the output signal of the OR circuit ORC1, that is, the internal signal ATD.
X1 is temporarily set to the high level. At this time, the MOS
The FET P3 is turned off in response to the high level of the output signal of the inverter V7. Instead, the MOSFET P4 having a relatively large conductance is turned on in response to the low level of the output signal of the inverter V8, thereby detecting the unit address transition. Signals TDX0 to TDXi, T
DX0B to TDXiB, TDZ0 to TDZ1 and T
The rise of the internal node n1 to the high level at the time when DZ0B to TDZ1B are returned to the low level is accelerated.

In this way, the OR circuits ORC1 to ORC
3 is a corresponding unit address transition detection signal TDX0 to TDX
DXi, TDX0B to TDXiB, TDZ0 to TDZ1
And TDZ0B to TDZ1B or unit address transition detection signals TDXR0 to TDXR1, TDXR0B to TD
XR1B, TDYR0 to TDYR1 and TDYR0
B to TDYR1B or unit address transition detection signal T
DY0 to TDYj, TDY0B to TDYjB and T
The output signals, that is, the internal signals ATDX, which substantially form OR gates for the DCSB, respectively.
1, ATDX2 and ATDY are selectively and temporarily set to the high level when any of the corresponding unit address transition detection signals is set to the high level.

The output signal of the OR circuit ORC1 or the internal signal ATDX1 is supplied to one input terminal of the OR gate OG3, and the output signal of the OR circuit ORC2 or the internal signal ATDX2 is supplied to the other input terminal.
The output signal of the OR gate OG3 is output as the address transition detection signal ATDX, and the OR gate OG4
Is supplied to one of the input terminals. The output signal of the OR circuit ORC3, that is, the internal signal ATDY is supplied to the other input terminal of the OR gate OG4, and the output signal is output as the address transition detection signal ATD.

As a result, the address transition detection signal ATD
X is such that when either the internal signal ATDX1 or ATDX2 is temporarily set to the high level, in other words, the logical level of either the internal address signal or the redundancy switching signal involved in the word line selecting operation is inverted. At this time, the high level is selectively and temporarily set. Also,
The address transition detection signal ATD is either the internal address signal or the redundancy switching signal involved in the word line or bit line selection operation when either the internal signal ATDX or ATDY is temporarily set to the high level. When the logic level of is inverted, it is selectively and temporarily set to the high level.

As described above, the address transition detection circuit AT
Address transition detection signals ATDX and A output from D
The TD is supplied to the timing generation circuit TG, and various internal control signals for controlling the operation of the internal circuit of the static RAM are selectively formed based on the TD. Also,
Among these internal control signals, the internal control signal BLEQ
And equalize the bit line or the common data line to the initial state like CDEQ or set the drive timing of the sense amplifiers SA0 to SA3 like the internal control signal SD, so to speak, to activate the internal circuit of the static RAM. Included for On the other hand, the conditions for forming the address transition detection signals ATDX and ATD include the redundancy switching signals XR0 to XR0 for defect relief as described above.
The level changes of XR1 and YR0 to YR1 are included. As a result, the static RAM of this embodiment
In this case, after the internal circuit is once activated in response to a normal activation factor due to the chip selection signal CSB being set to the low level or the address signal being changed, redundancy switching to the redundant word line or redundant bit line is performed. At that time, the internal circuit is activated again.

FIG. 11 shows the static RAM of FIG.
FIG. 12 shows a signal waveform diagram of one embodiment when the read mode is not repaired, and FIG. 12 shows a signal waveform diagram of one embodiment when the read mode is repaired. Further, FIG. 13 shows a signal waveform diagram of one embodiment in the case of shifting from the non-relief word line in the continuous read mode of the static RAM of FIG. 1 to the relief word line, and FIG.
A signal waveform diagram of one embodiment in the case of shifting from the rescue word line in the continuous read mode to the non-rescue word line is shown. Based on these figures, a specific operation and its characteristics at the time of starting the static RAM of this embodiment will be described. Note that the following description will proceed with an example in which the defect relief related to the word line is performed.
Please analogy about defect relief for bit lines. Furthermore, in the following signal waveform diagrams, memory arrays ARY0 to
The sub-word lines and main word lines forming ARY3 are referred to as word lines W0 to Wm, and the complementary bit lines are B0 * to
It is called Bn *.

In FIG. 11, the static RAM of this embodiment is brought into a non-selected state by setting the chip selection signal CSB to the high level. At this time, in the static RAM, the redundancy switching signals XR0 to XR1 are set to low level, and all word lines including the redundant word lines WR0 and WR1 are set to low level non-selected state. Further, the address transition detection signals ATDX and ATD are both set to the low level, and in response to this, the internal control signal BLEQ is received.
And CDEQ are set to high level, and the internal control signal SD is set to low level. As a result, the complementary bit line B0 *
The non-inverted and inverted signal lines of ~ Bn * are precharged to a high level like the power supply voltage of the circuit, and the non-inverted and complementary data lines CR0 * to CR7 * for reading and the data input / output buses DB0 * to DB7 *. The inverted signal line is also precharged to the high level. Furthermore, the internal control signal DO
C is set to the low level, and in response to this, all the data input / output terminals IO0 to IO7 are set to the high impedance state Hz.

Next, the static RAM is brought into a selected state by setting the chip selection signal CSB to the low level, and the write enable signal WEB (not shown) is set to the high level at the falling edge of the chip selection signal CSB. Therefore, the operation mode is set to the read mode. The address input terminals AX0 to AXi are supplied with a combination of the X address signals AX0 to AXi that specifies a normal word line Wa which does not have a failure, that is, does not require repair, prior to the low level change of the chip selection signal CSB. , Address input terminals AY0 to AYj and A
Z0 to AZ1 have Y address signals AY0 to AYj and Z address signal AZ0 in any desired combination.
~ AZ1 are supplied respectively.

In the static type RAM, each address signal is taken into the corresponding address buffer in response to the low level of the chip selection signal CSB, and the level change of the internal address signals X0 to Xi, Y0 to Yj and Z0 to Z1 and the chip change. In response to the low level change of the selection signal CSB itself, the address transition detection signals ATDX and ATD
Is temporarily set to a high level. The memory arrays ARY0 to ARY3 corresponding to the decoding results of the internal address signals X0 to Xi by the X address decoder XD are received.
The word line Wa is set to the selection level, and the internal control signals BLEQ and CDEQ are set to the low level at a predetermined timing in response to the high levels of the address transition detection signals ATDX and ATD. Then, the internal control signal SD is set to the high level with a slight delay, and the internal control signal DOC is set to the high level with a further delay.

As a result, n connected to the word line Wa
The read signal of +1 memory cell is the internal control signal B
When LEQ is set to the low level and the equalizing operation by the bit line precharge circuit is stopped, it is output to the corresponding complementary bit lines B0 * to Bn *. Then, a sufficient read signal amount ΔV for these complementary bit lines
When 1 is obtained, the internal control signal SD is set to the high level to activate the sense amplifiers SA0 to SA3, and the output terminals thereof, that is, the data input / output buses DB0 * to D0.
A full swing read signal amplified to B7 * is obtained. These read signals are output to the data output buffer O
B is transmitted to B and receives the high level of the internal control signal DOC and is transmitted from the data input / output terminals IO0 to IO7.

As described above, the operation of selecting the normal word line Wa or the like in the static RAM of this embodiment is X
The process proceeds without waiting for the result of the address identification operation by the system redundancy switching circuit XR, and the timings of the internal control signals BLEQ, CDEQ and SD are set in the required minimum time. Therefore, the access time of the static RAM in the non-relief mode is accelerated without being affected by the operation of the X-system redundancy switching circuit XR which requires a relatively large number of logic stages. Access time is shortened.

On the other hand, when the defective word line Ws requiring defect relief is designated by the X address signals AX0 to AXi, in the static RAM, first, as shown in FIG. The defective word line Ws is once brought into the selected state by the line selection operation, but when the address identification operation by the X-system redundancy switching circuit XR is completed, the corresponding redundancy switching signal XR0 is set to the high level, and the corresponding redundancy word. The line WR0 is selected. In addition, in response to the high level of the redundancy switching signal XR, the defective word line Ws is deselected, and the address transition detection circuit ATD temporarily sets the address transition detection signals ATDX and ATD to the high level. Receiving internal control signal BLE
Q, CDEQ, and SD are formed again at a predetermined timing. As a result, the complementary bit lines B0 * to Bn *
And read complementary common data lines CR0 * to CR7
* Is equalized again and a sufficient read signal amount ΔV is applied to these complementary bit lines and complementary common data lines for reading.
When 2 is obtained, the internal control signal SD is set to the high level and the sense amplifiers SA0 to SA3 are activated. As a result, the access time of the static RAM at the time of repair is slightly delayed, but the signal margin is expanded and the read operation is stabilized.

Next, as shown in FIG. 13, the static RAM is set to the read mode in the continuous mode, that is, the continuous read mode by changing the address signal while the chip selection signal CSB is kept at the low level. . At this time, when the word line to be selected is transferred from the non-relief word line Wa to the relief word line Ws, in the static RAM, the X address signals AX0 to AXi are used.
The word line Wa is brought into the non-selected state in response to the change of the above, and the defective word line Ws is put into the selected state instead. But X
Since the redundancy switching signal XR0 is set to the high level at the end of the address identification operation by the system redundancy switching circuit XR, the defective word line Ws is immediately deselected and the redundant word line WR0 is selected instead. .

In the address transition detection circuit ATD, the address transition detection signals ATDX and ATD are temporarily set to the high level in response to the level changes of the X address signals AX0 to AXi, and further the high level of the redundancy switching signal XR0 is received and the signal is detected again. The address transition detection signals ATDX and ATD are temporarily set to high level. Further, in response to the high level of the address transition detection signal, the internal control signals BLEQ and CDEQ are temporarily set to the high level twice, and the internal control signal SD is set to a predetermined level from the second rise of the address transition detection signals ATDX and ATD. It is set to a high level when time passes. As a result, complementary bit lines B0 * to B0
n * and read complementary common data lines CR0 * to C
In R7 *, a sufficient read signal amount ΔV3 is obtained at the time when the internal control signal SD is set to the high level and the sense amplifiers SA0 to SA3 are activated, which makes the cycle time of the static RAM somewhat slower. The continuous read operation is stabilized.

On the other hand, the word lines to be selected in the continuous read mode are the relief word line Ws to the non-relief word line Wa.
14 is used in the static RAM,
As shown in (1), the address transition detection signals ATDX and ATD are temporarily set to the high level in response to the level changes of the X address signals AX0 to AXi. Further, since the redundancy switching signal XR0 is returned to the low level at the time when the address identification operation by the X system redundancy switching circuit XR is completed, the address transition detection signal A is received in response to this level change.
TDX and ATD are temporarily set to the high level again.
As a result, the redundant word line WR0 is brought into a non-selected state,
Instead, the non-relief word line Wa is selected. Further, the internal control signals BLEQ and CDEQ are temporarily set to the high level twice upon receiving the high levels of the address transition detection signals ATDX and ATD, and the internal control signal SD is changed from the second rising edge of the address transition detection signals ATDX and ATD. The high level is set when a predetermined time has elapsed. As a result, the internal control signal SD is set to the high level on the complementary bit lines B0 * to Bn * and the complementary complementary common data lines CR0 * to CR7 *, and the sense amplifier SA0 is set.
Sufficient read signal amount ΔV4 is obtained at the time when SA3 is brought into the operating state, whereby the static RAM
The continuous read operation of is stabilized.

When the selected word line shifts from the non-relief word line to the non-relief word line in the continuous read mode, the level change of the redundancy switching signals XR0 to XR1 does not occur, and therefore the address transition detection signals ATDX and ATD.
Are formed only once. At this time, as described above, the selection operation for the non-relief word line is performed without waiting for the result of the address identification operation by the X-system redundancy switching circuit XR, so that the average cycle time of the static RAM is appropriate. It will be faster.

On the other hand, in the above embodiment, the static RA
Although the M read mode has been taken as an example, regarding the write mode, the internal control signals BLEQ and CDEQ for equalizing the bit lines and the common data lines and the internal control signal WP for driving the write amplifiers WA0 to WA3 are described. By performing the same timing setting, the write operation in the write mode of the static RAM can be stabilized and the average access time and cycle time can be shortened.

The operational effects obtained from the above embodiments are as follows. That is, (1) a memory array including redundant word lines or redundant bit lines selectively assigned to a defective word line or defective bit line in which a failure is detected, and a defective word line or defective bit line are designated by an address signal. A redundant switching circuit for selectively forming a redundant switching signal for selecting the corresponding redundant word line or redundant bit line and identifying a level change of the address signal or the start control signal. A static RA including an address transition detection circuit that selectively forms an internal activation signal, and a timing generation circuit that selectively forms a predetermined internal control signal for receiving the internal activation signal and bringing the internal circuit into an activated state.
In M or the like, the redundancy switching signal output from the redundancy switching circuit is input to the address transition detection circuit to restart the internal circuit when the redundancy word line or the redundancy bit line is selected or deselected. By setting the state, it is possible to obtain the effect that the bit line and the common data line can be sufficiently equalized and a sufficient read signal amount can be secured even when the defect relief by the redundant word line or the redundant bit line is performed.

(2) According to the above item (1), it is possible to obtain an effect that the writing and reading operations of the static RAM can be stabilized. (3) In the above items (1) and (2), the redundant word is selected by advancing the selection operation for the normal word line or the normal bit line in which no failure is detected without waiting for the result of the address identification operation by the redundancy switching circuit. Line or redundant bit line is in the selected state, or the redundant word line or redundant bit line is transferred to the selected state or the non-selected state in the continuous mode, the operation of the static RAM is restarted and the normal word line The effect that the selection operation for the normal bit line can be speeded up is obtained. (4) According to the above items (1) to (3), the average access time and cycle time can be shortened while stabilizing the operation of the static RAM or the like.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the static RAM can include an arbitrary number of redundant word lines and redundant bit lines, and their arrangement is also arbitrary. Further, the memory array can be divided into an arbitrary number in the extending direction of the word lines, and can also be divided in the extending direction of the bit lines.
The Z address signals AZ0 to AZ1 may be regarded as a part of the Y address signal, and the number of bits thereof also changes according to the number of divisions of the memory array. The static RAM can have an arbitrary bit configuration, and its block configuration, a combination of a start control signal and an internal control signal, and the like can take various embodiments.

2 to 10, the block configuration of the X-system redundant switching circuit XR, the Y-system redundant switching circuit YR, and the address transition detection circuit ATD, the specific configuration of each part thereof, and the polarity of the power supply voltage are variously implemented. It can take any form. Further, in FIGS. 11 to 14, the logical levels and names of the activation control signal and the internal control signal, the specific timing relationship, and the like are not restricted by these embodiments. Further, the static RAM does not necessarily include the address transition detection circuit ATD, and directly outputs the redundancy switching signals XR0 to XR1 and YR0 to YR1 output from the X system redundancy switching circuit XR and the Y system redundancy switching circuit YR. Similar effects can be obtained by inputting to the timing generation circuit TG.

In the above description, the case where the invention made by the present inventor is mainly applied to the static type RAM which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to various memory integrated circuit devices such as dynamic RAMs and logic integrated circuit devices including the same. The present invention can be widely applied to a semiconductor memory device including at least a redundancy switching circuit, and an apparatus and system including such a semiconductor memory device.

[0080]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a memory array including redundant word lines or redundant bit lines selectively assigned to a defective word line or defective bit line in which a failure is detected,
A redundancy switching circuit for selectively forming a redundancy switching signal for identifying that the defective word line or the defective bit line is designated by the address signal and for setting the corresponding redundant word line or the redundant bit line, and an address. Address transition detection circuit that identifies a level change of a signal or a start control signal and selectively forms an internal start signal, and a predetermined internal control signal that receives the internal start signal and sets the internal circuit to a start state selectively. In a static RAM or the like having a timing generation circuit formed in the above, a redundant switching signal output from the redundant switching circuit is input to an address transition detection circuit, and a redundant word line or redundant bit line is selected or unselected. If this occurs, the internal circuit is restarted, and a normal word line or normal A redundant word line or a redundant bit line is brought into a selected state or a redundant word line or a redundant bit line is brought into a selected state in a continuous mode by advancing the selection operation for the selected line without waiting for the result of the address identification operation by the redundant switching circuit. Or, re-execute the operation of static RAM etc. only when shifting to the non-selected state,
The selection operation for the normal word line and the normal bit line can be speeded up. As a result, it is possible to speed up the average access time and cycle time while stabilizing the read and write operations of the static RAM and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

2 is a block diagram showing an embodiment of an X-system redundancy switching circuit included in the static RAM of FIG.

3 is a circuit diagram showing an embodiment of an X system redundant address memory and an X system redundant enable circuit included in the X system redundant switching circuit of FIG.

4 is a circuit diagram showing an embodiment of an X system redundant address comparison circuit included in the X system redundancy switching circuit of FIG.

5 is a block diagram showing an embodiment of a Y-system redundancy switching circuit included in the static RAM of FIG.

6 is a circuit diagram showing an embodiment of a Y-system redundant address memory and a Y-system redundant enable circuit included in the Y-system redundant switching circuit of FIG.

7 is a circuit diagram showing an embodiment of a Y-system redundant address comparison circuit included in the Y-system redundant switching circuit of FIG.

8 is a block diagram showing an embodiment of an address transition detection circuit included in the static RAM of FIG.

9 is a circuit diagram showing an embodiment of a unit address transition detection circuit included in the address transition detection circuit of FIG.

10 is a circuit diagram showing an embodiment of an address transition detection signal generation circuit included in the address transition detection circuit of FIG.

11 is a signal waveform diagram showing an embodiment of the static RAM of FIG. 1 in a non-relief mode in a read mode.

FIG. 12 is a signal waveform diagram showing an embodiment at the time of repairing the read mode of the static RAM of FIG.

FIG. 13 is a signal waveform diagram showing an example of a case where the static RAM of FIG. 1 shifts from a non-relief word line in a continuous read mode to a relief word line.

FIG. 14 is a signal waveform diagram showing an example of the case where the repair word line in the continuous read mode of the static RAM of FIG. 1 is shifted to the non-repair word line.

FIG. 15 is a signal waveform diagram showing an example of a conventional static RAM in a non-relief mode in a read mode.

FIG. 16 is a signal waveform diagram showing an example of transition from a rescue word line in a continuous read mode of a conventional static RAM to a non-relief word line.

[Explanation of symbols]

ARY0 to ARY3 ... Memory array, WR0 to WR
1 ... Redundant word line (redundant main word line and redundant sub word line), BRG0 to BRG1 ... Redundant bit line group, XD ... X address decoder, XR ... X system redundant switching circuit, XB ... X address buffer, YS
0-YS3 ... Y switch, YD0-YD3 ... Y
Address decoder, YR ... Y system redundancy switching circuit,
YB ... Y address buffer, ZB ... Z address buffer, MS ... mat selection circuit, WA0-WA3
... write amplifier, SA0-SA3 ... sense amplifier, IB ... data input buffer, OB ... data output buffer, ATD ... address transition detection circuit, T
G: Timing generation circuit. XEN0 to XEN1 ...
・ X system redundancy enable circuit, XRM0 to XRM1 ...
X system redundant address memory, XRC0 to XRC1 ... X
System redundant address comparison circuit, YEN0 to YEN1 ... Y
System redundancy enable circuit, YRM0 to YRM1 ... Y system redundant address memory, YRC0 to YRC1 ... Y system redundant address comparison circuit, FC ... Fuse circuit, UC.
..Unit address comparison circuit TDX0 to TDXi, TD
X0B to TDXiB, TDY0 to TDYj, TDY0B
~ TDYjB, TDZ0 to TDZ1, TDZ0B to TD
Z1B, TDXR0-TDXR1, TDXR0B-TD
XR1B, TDYR0-TDYR1, TDYR0B-T
DYR1B, TDCSB ... Unit address transition detection circuit, ATDG ... Address transition detection signal generation circuit, O
RC1 to ORC3 ... Logical sum circuit. P1-P4 ... P
Channel MOSFET, F1 ... Fuse, G1
G2 ... Complementary gate, V1-V9 ... Inverter,
DV1 to DV3 ... Delay inverters, OG1 to OG4
... OR gates, AG1 to AG2 ... AND gates, NO1 to NO6 ... NOR gate (NO)
R) Gate.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/04 21/822 H01L 27/04 M (72) Inventor Masayoshi Kuroiwa 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Within Hitachi Hokkai Semiconductor Co., Ltd. (72) Inventor Mitsuhiro Higuchi 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Within Hitachi, Ltd. Semiconductor Division

Claims (5)

[Claims] 1. A memory array including a redundant word line or a redundant bit line selectively assigned to a defective word line or a defective bit line in which a failure is detected, and the defective word line or the defective bit line according to an address signal. A redundant switching circuit for selectively forming a redundant switching signal for identifying the designated and setting the corresponding redundant word line or redundant bit line in a selected state, and an internal circuit for receiving a predetermined internal start signal. A semiconductor memory device, comprising: a timing generation circuit that selectively forms a predetermined internal control signal for bringing into an activated state, wherein the internal activation signal is formed based on at least the redundancy switching signal. . 2. The semiconductor memory device has a continuous mode in which a plurality of addresses can be continuously accessed by changing the address signal in the selected state, and the address signal or the start control signal or the redundancy switching is performed. 2. The semiconductor memory device according to claim 1, further comprising an address transition detection circuit that identifies a level change of a signal and selectively forms the internal activation signal. 3. The address transition detection circuit selectively forms the internal activation signal in response to both a high level change and a low level change of the redundancy switching signal. Semiconductor memory device. 4. A selection operation for bringing a normal word line or a normal bit line in which a failure is not detected in response to the internal activation signal into a selected state is proceeded without waiting for the result of the address identification operation by the redundancy switching circuit. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 5. The first and second internal control signals are for equalizing a bit line and a common data line, respectively.
Internal control signal and a third for driving the sense amplifier
5. The semiconductor memory device according to claim 1, wherein the internal control signal is included.