JPH0720097B2 - F / S bit synchronization establishment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a signal transmission system in which time-division multiplexed signals transmitted via a plurality of digital lines are concentrated and transmitted as new time-division multiplexed signals. Regarding the F / S bit synchronization establishment method when the F / S bits on each time division multiplexed signal are multiplexed to a new time division multiplexed signal, the establishment of the F / S bit synchronization at the terminating equipment is Each first time division multiplexed signal has a predetermined time division unit for the purpose of realizing an F / S bit synchronization establishment method that can reduce the burden on synchronization establishment without having to perform it for each division signal. F / S that is inserted in the frame and forms one information unit with predetermined multiple bits
F / S bit extracting means provided for each of the first time division multiplexed signals for extracting bits, and each of the first and the second capable of temporarily storing the extracted F / S bits and independently controlling writing and reading. One buffer means provided for each time-division multiplexed signal and the F / S bits stored in each buffer means are synchronously read in the above-mentioned information unit and multiplexed with the second time-division multiplexed signal. And F / S bit multiplexing means.

[Industrial application field]

The present invention relates to a signal transmission system for concentrating and multiplexing a time division multiplexed signal transmitted via a plurality of digital lines and transmitting it as a new time division multiplexed signal, and more specifically to each time division multiplexed signal. The present invention relates to an F / S bit synchronization establishment method when the above F / S bits are multiplexed into a new time division multiplexed signal.

[Conventional technology]

In a digital switching system for transmitting / switching PCM signals, normally, a plurality of low-speed PCM multiplexed signals are concentrated and multiplexed to medium / high-speed PCM multiplexed signals, and switching connection is performed to connect to another station or another station. It is transmitted to the terminal device.

FIG. 5 shows the overall configuration of a digital exchange system that performs the above operation. The transmission rate transmitted from each of the other stations A to E by the PCM24 system is 1.5 M (mega) bit / s multiplexed signal 1-1.
1 to 5 are digital terminals (hereinafter referred to as DT)
The digital switching module (hereinafter referred to as DSM), which is an exchange, receives the signals at 2-1 to 2-5, concentrates and multiplexes them into an 8Mbit / s multiplexed signal 6 under the control of a digital terminal common (hereinafter referred to as DTC) 3. ) 4 is transmitted. The 8 Mbit / s multiplexed signal 6 exchange-connected by the DSM 4 is directly received by the terminating device 5, for example.

FIG. 6 shows the 1.5M bit / s multiplexed signals 1-1 to 1- of FIG.
5 shows a format of 5. These signals are PCM24
According to the method, one channel has bits 1 to 1 as shown in FIG.
The audio data 8 of 1 sample is stored in 8 bits of bit 8, and this is stored in channel 0 to channel 23 as shown in the figure.
24 channels are time division multiplexed. In addition, at the beginning of the frame synchronization and multi-frame synchronization (described later) 1
A frame with the bit F / S bit 7 added is called a frame. Here, the time width of one frame is 125 μ (micro) sec. That is, the audio data 8 of each channel
Is transmitted every 125 μsec, and 8-bit audio data with a sampling frequency of 8 kHz can be transmitted in real time for 24 people. As a result, the transmission rate per second is 1.5M bit / s (strictly speaking, 1.544M bit / s).

Next, in FIG. 7, 8 Mbit / s output from DTC3 in FIG.
The format of the multiplexed signal 6 is shown. Now, 1.5M in Fig. 5
Since the bit / s multiplexed signals 1-1 to 1-5 each have 24 channels of voice channels per frame as shown in FIG. 6, there are 120 channels in five. As shown in FIG. 7 for the 8 Mbit / s multiplexed signal 6, these voice channels are 1 frame time slot (hereinafter referred to as TS) 4
~ TS63 and TS68 ~ TS127 are time-division multiplexed on 120 channels. Naturally, each channel has an 8-bit structure corresponding to FIG.

Next, each F / S bit 7 (see FIG. 6) of the 1.5 M bit / s multiplexed signals 1-1 to 1-5 has 1 bit per frame common to each channel, and 5 bits have 5 bits. Each of these 1.
Assuming that the F / S bits corresponding to the 5M bit / s multiplexed signal 1-1 to 1-5 are 7-1 to 7-5, the 8M bit / s multiplexed signal 6 is TS0 as shown in FIG. ~ 4 control channels of TS3
It is stored in 5 bits of bit 2 to bit 6 of TS3. Control information such as failure information is stored in the DTC 3 of FIG. 5 in TS0 to TS2 of the control channel 10.

In addition, in the case of 8M bit / s multiplexed signal 6, TS64 of FIG.
Signaling channel 11 of TS67 is 1.5M bit in Fig. 5.
/ s Signaling bits (not shown in FIG. 6) for call control that are multiplexed in the multiplexed signals 1-1 to 1-5 are stored.

The time width of one frame of the 8M bit / s multiplexed signal 6 shown in FIG. 7 is 125 μsec. That is, the audio data 8 of each channel is transmitted every 125 μsec, and the 8-bit audio data with a sampling frequency of 8 kHz is recorded in real time for 120 persons, that is, the 1.5 M bit / s multiplexed signal is 1-1 to 1 -5 (fifth
5) can be transmitted. Then, the voice channel 9, control channel 10 and signaling channel 11 of FIG.
In total, 128 channels can be transmitted. As a result, the transmission rate per second is 8M bit / s (strictly speaking, 8.192M bit /
s).

Here, in the F / S bit 7 (Fig. 6) added to the beginning of each frame of the 1.5M bit / s multiplexed signal, the F / S bit of the frame with an odd frame number as shown in Fig. 8 is used. 7
The (F bit) has a bit pattern for frame synchronization as shown in “101010”, for example. Therefore, each DT2-1 to 2-5 in FIG. 5 has a 1.5M bit / s multiplexed signal 1-1.
By extracting the above patterns from 1 to 5, the frame delimiter timing is detected and frame synchronization is established. On the other hand, the F / S of the frame with an even frame number
Bit 7 (S bit) has a bit pattern for identifying each multi-frame as shown in, for example, “001011” for each predetermined plurality of frames (hereinafter, referred to as multi-frame), for example, for every 12 frames. Here, each 1.5M bit / s stored in the signaling channel 11 shown in FIG.
Although not specifically shown, the signaling bits of the multiplexed signals 1-1 to 1-5 form one piece of call information and the like in each multiframe unit. Therefore, each device in FIG.
After the frame synchronization is established, the S-bit pattern for each frame is detected to detect the timing of multi-frame delimitation, whereby multi-frame synchronization is established and the calling information and the like are detected. .

Also, the terminating device 5 and the like shown in FIG. 5 are each 1.5M bit / s multiplexed signals 1-1 to 1M multiplexed with the 8M bit / s multiplexed signal 6.
Since each of the calling information 1-5 may be required, it is necessary to establish multi-frame synchronization of each multiplexed signal. In this case, the F / S bits 7-1 to 7 of each 1.5M bit / s multiplexed signal 1-1 to 1-5 multiplexed on TS3 of the 8M bit / s multiplexed signal 6 in FIG. When -5 is viewed in the frame direction, it becomes as shown in FIG. 9, for example. In the figure, the part delimited by the single line is the frame delimiter, and 2
The part delimited by the double line is the delimiter of the multiframe.

[Problems to be Solved by the Invention]

In FIG. 9, the delimiter position of the multiframe for each F / S bit 7-1 to 7-5 is different. This is because the 1.5M bit / s multiplexed signals 1-1 to 1-5 in FIG.
This is because they are processed by different stations A to E and are not synchronized with each other.

Therefore, in order for the terminating device 5 of FIG. 5 to establish the multi-frame synchronization of each 1.5M bit / s multiplexed signal 1-1 to 1-5, the 8M bit / s multiplexed signal 6 of FIG. Each F / S bit 7-1 to be multiplexed in TS3 as shown in FIG. 7 and FIG.
It is necessary to individually perform multi-frame synchronization for each of 7-5, so that there is a problem in that the circuit scale for establishing synchronization in the terminating device 5 becomes large, resulting in an increase in processing time and cost. is doing.

It is an object of the present invention to realize an F / S bit synchronization establishment method capable of reducing the burden on the synchronization establishment without having to establish the synchronization of the F / S bits in each terminating device for each multiplexed signal. And

[Means for Solving the Problems]

FIG. 1 is a block diagram of the present invention. The present invention is premised on a signal transmission system in which a plurality of first time division multiplexed signals 12-1 to 12-N are line-concentrated and transmitted as a second time division multiplexed signal 13. Here, the first time division multiplexed signal 12
Is a 1.5M bit / s multiplexed signal obtained by time-division-multiplexing 24 audio channels of the PCM system, and the second time-division multiplexed signal 13 is, for example, N = 5, and the 5th 1 time division multiplexed signals 12-1 to 12-5 are concentrated and multiplexed
It is an 8M bit / s multiplexed signal that stores 120 audio channels.

In FIG. 1, each of the first time division multiplexed signals 12-1 to 12-
F / S bit extraction means 15-1 to 15-N provided for each N
Is inserted into each of the first time division multiplexed signals 12-1 to 12-N for each predetermined time division unit, for example, for each frame (24 channels), and for a predetermined plural bits, that is, for example, plural frames (multiframe). The F / S bits 14-1 to 14-N forming one information unit are extracted. The same means, for example, means for extracting a clock from each of the first time division multiplexed signals 12-1 to 12-N and a synchronization pattern of each F / S bit 14-1 to 14-N are detected and synchronized. It is means for establishing and means for extracting each F / S bit 14-1 to 14-N based on it.

Next, the buffer means 16-1 to 16-N provided for each of the first time division multiplexed signals 12-1 to 12-N are the F / S bit extracting means 15-1 to 15-N. F / S bit 14 extracted
Temporarily store -1 to 14-N. In this case, writing and reading can be controlled independently. The means is, for example, an elastic store memory.

Further, the F / S bit multiplexing means 17 includes the buffer means 1 described above.
F / S bits 14-1 to 14- stored in 6-1 to 16-N
Each N is read in synchronization with the information unit and multiplexed with the second time division multiplexed signal 13. The same means synchronizes, for example, the delimiters of the multi-frame, and each buffer means
It is a means for reading out the respective F / S bits 14-1 to 14-N from 16-1 to 16-N and multiplexing them into a predetermined time slot of the second time division multiplexed signal 13.

In addition to the above-mentioned means, when each F / S bit 14-1 to 14-N is multiplexed by the F / S bit multiplexing means 17 into the second time division multiplexed signal 13, The delimiter information 19 common to the F / S bits 14-1 to 14-N is added to. For example, the same means is used for each of the F / Fs on the second time division multiplexed signal 13.
It is a means for setting a logical "1" bit for each head frame of the multiframe in the empty bit of the time slot in which the S bits 14-1 to 14-N are multiplexed.

Incidentally, in FIG. 1, each first time division multiplexed signal 12-
The voice channel portions 1 to 12-N are mutually phase-synchronized with each other by, for example, a buffer means (not shown).
Are multiplexed as the time-division multiplexed signal 13.

[Action]

In FIG. 1, each of the first time division multiplexed signals 12-1 to 12
Since -N is often transmitted from different exchanges, the F / S bits 14-1 to 14-N are not synchronized with each other in a predetermined multiple-bit information unit (for example, a multiframe unit). .

These F / S bits 14-1 to 14-N are respectively buffer means 16-1 via the F / S bit extracting means 15-1 to 15-N.
To 16-N are temporarily stored.

Then, the F / S bit multiplexing means 17 causes each buffer means 16
F / S bits 14-1 to 14 temporarily stored in -1 to 16-N
For -N, the delimiters of the information units (multiframe units) are made to coincide with each other and read out, and multiplexed into the second time division multiplexed signal 13.

As a result, the terminating device or the like (not shown) that receives the second time division multiplexed signal 13 receives each of the first time division multiplexed signals.
When establishing synchronization of 12-1 to 12-N, if synchronization is established only for the F / S bit relating to any one of the first time division multiplexed signals, all the first time division multiplexed signals 12 −
Synchronization can be established for 1-12-N.

In particular, when the above F / S bits 14-1 to 14-N are multiplexed with the second time division multiplexed signal 13, delimiter information adding means
18 adds the delimiter information 19 for each delimiter of the information unit, so that the terminating device or the like only monitors the delimiter information 19 so that all the first time division multiplexed signals 12-1 to 12-
Synchronization can be established for N and F / S bit 14-
It is not necessary to perform the synchronization establishing operation for any of 1 to 14-N. As a result, it becomes possible to carry arbitrary information (inter-station control information, etc.) on the F / S bits 14-1 to 14-N in addition to the pattern for establishing synchronization.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

First, the overall configuration of the digital exchange system is the same as that shown in FIG. 5 already described.

Next, FIG. 2 is a diagram showing a configuration of an embodiment of the present invention relating to the portions of DT2-1 to 2-5 and DTC3 in FIG.

Fig. 5 1.5M bit / s multiplexed signals from other stations A to E 1-
1 to 1-5 are input to DT2-1 to 2-5, respectively. DT2-
Since 1 to 2-5 have the same configuration, only 2-1 will be described.

First, the clock extraction unit 20 determines the 1.5M bit / s multiplexed signal 1-
Extract the clock signal from 1.

The synchronization establishing unit 21 establishes synchronization on a frame-by-frame and multi-frame basis for the 1.5 M bit / s multiplexed signal 1-1.

The audio signal extraction unit 22 extracts only the audio channel portion from the 1.5M bit / s multiplexed signal 1-1 based on the clock signal extracted by the clock extraction unit 20.

The elastic store (hereinafter, referred to as ES-A) 23 is output from the audio signal extraction unit 22 according to the write signal generated from the ES-A write signal generation unit 24 based on the clock signal from the clock extraction unit 20. Extracted 1.5M bit / s multiplexed signal 1-
Buffer 1 voice channel portion. And
This stored content is stored in the read timing signal generator 30 in the DTC3.
Is read out according to the read signal generated from the ES-A read signal generating section 25 based on the read timing signal from, and multiplexed with the outputs of the other DTs 2-2 to 2-5 to the multiplexing circuit 33 in the DTC 3. input. The writing operation and the reading operation for the ES-A23 can be performed independently.

The F / S bit extraction unit 26 extracts the F / S bit 7-1 based on the clock signal from the clock extraction unit 20 and the frame synchronization signal from the synchronization establishment unit 21.

The elastic store (hereinafter, referred to as ES-B) 27 is based on the clock signal from the clock extraction unit 20 and according to the write signal generated from the ES-B write signal generation unit 28, the F / S.
1.5M bit / s multiplexed signal 1 extracted from the bit extraction unit 26
Buffer the F / S bit 7-1 of -1. Then, this stored content is read according to the read signal generated from the ES-B read signal generating unit 29 based on the read timing signal from the read timing signal generating unit 30 in the DTC 3, and the other DTs 2-2 to 2-2. It is multiplexed with the output of -5 and input to the F / S bit addition unit 31 in the DTC3. The writing operation and the reading operation for the ES-B27 can be independently performed as in the case of the ES-A23.

Next, the configuration of DTC3 will be described.

As described above, the read timing signal generating unit 30
A read timing signal is supplied to the ES-A read signal generator 25 and the ES-B read signal generator 29 in -1 to 2-5.

The F / S bit addition unit 31 is provided for each ES-B2 in each DT2-1 to 2-5.
Each of the F / S bits 7-1 to 7-5 output from 7 is multiplexed into an 8M bit / s multiplexed signal 6 via a multiplexing circuit 33 as described later. Further, the head bit adding unit 32 receives the information indicating the multiframe delimiter from the F / S bit adding unit 31, and as described later, the multiplexing circuit 33
The first bit 34 is multiplexed to the 8M bit / s multiplexed signal 6 via.

The 8M bit / s multiplexed signal 6 obtained by being multiplexed by the multiplexing circuit 33 as described above is output to the DSM 4 in FIG.

The operation of the embodiment having the above configuration will be described below.

First, the format of each of the 1.5M bit / s multiplexed signals 1-1 to 1-5 is the same as that of FIG. 6 already described, and the 8-bit audio data 8 of FIG. 6 is as shown in FIG. Time division multiplexing for 24 channels, 1 bit F / S bit 7 at the beginning
Is added to make one frame.

Next, FIG. 3 shows the format of the 8 Mbit / s multiplexed signal 6 output from the DTC 3 of FIG. 2 according to this embodiment. This format is almost the same as the case of the conventional example of FIG.
As shown in FIG. 3, one frame is composed of 120 voice channels 9, 128 control channels 10 and 4 signaling channels 11, and 128 channels. However, the difference is that the leading bit 34 is inserted into bit 7 of TS3 of the control channel 10. This will be described later.

Now, the 24 audio channels of the 1.5M bit / s multiplexed signal 1-1 are extracted by the audio signal extraction unit 22, and then the ES-A23
, And the voice channels from other DTs 2-2 to 2-5 are combined and multiplexed as 120 voice channels 9 shown in FIG. In this case, since the 1.5M bit / s multiplexed signals 1-1 to 1-5 are respectively transmitted from the different stations A to E, the clock extractor 20 in each DT2-1 to 2-5.
The clocks extracted from are also not synchronized with each other. Therefore, the audio channels of each of the 1.5M bit / s multiplexed signals 1-1 to 1-5 are temporarily held in each ES-A23 in DT2-1 to 2-5, and then read timing signal in DTC3. Each generation unit 30
The ES-A read signal generators 25 in the DT2-1 to 2-5 are operated in synchronization to perform the read operation of each ES-A23, thereby synchronizing and multiplexing the phases of the respective voice channels. This makes it possible to absorb the phase shift between the lines. In the read operation described above, the read timing signal generator 30 in the DTC3 changes from the DSM in FIG.
If you operate based on the clock extracted from the 8M bit / s multiplexed signal (not shown),
Synchronization with DSM4 in the figure is guaranteed.

Next, F / S bits 7-1 to 7-5 directly related to the present invention
The multiplexing method will be described.

First, in FIG. 2, the F / S bit extraction unit 26 in DT2-1 is shown.
Then, based on the clock signal from the clock extraction unit 20 and the frame synchronization signal from the synchronization establishment unit 21, 1.5M bit / s
From the multiplexed signal 1-1, F / at the beginning of each frame in FIG.
S bit 7-1 is extracted.

In this case, as described with reference to FIG. 8, the F / S bit 7-1 (F bit) of the frame with an odd frame number has a bit pattern for frame synchronization as shown in “101010”, for example. The F / S bit 7-1 (S bit) of the frame having an even frame number has a bit pattern for identifying each multi-frame as shown in, for example, "001011" in units of multi-frame.

The F / S bit 7-1 is held in the ES-B 27, but in this case, the ES-B write signal generation unit 28 uses the multi-frame synchronization signal from the synchronization establishment unit 21 for multi-frame synchronization. The write signal is generated so that the F / S bit 7-1 consecutive from the F / S bit 7-1 of the first frame is sequentially stored from a specific address of the ES-B27.

The above F / S bit holding operation is performed for each DT 2-1 to 2-5.

On the other hand, the read timing signal generator 30 in the DTC3
Operates the ES-B read signal generators 29 in the DTs 2-1 to 2-5 in synchronization with each other and sets the F / S bits 7-1 to 7-5 from the specific address of each ES-B27 to each other. Reads in sync. That is, in each F / S bit 7-1 to 7-5 read from each ES-B27, the delimiters of each multiframe are completely synchronized. In this read operation, as in the case of the operation for the ES-A23, the read timing signal generation unit 30 in the DTC3 is, for example, the DSM4 shown in FIG.
If the clock is extracted on the basis of the clock extracted from the 8M bit / s multiplexed signal (not shown) coming down to DTC3, the synchronization with DSM4 in FIG. 5 is guaranteed.

The F / S bits 7-1 to 7 read out as described above
-5 is input to the F / S bit addition unit 31 in the DTC3. Then, the addition unit 31 passes the F / S bits 7-1 to 7-5 to the 8M bit / s multiplexed signal 6 shown in FIG. 3 via the multiplexing circuit 33.
Of the TS3 in the control channel 10 of FIG.

The contents of TS3 based on the above operation are viewed in the frame direction, for example, as shown in FIG. In the same figure, the part delimited by a single line is a frame delimiter, and the part delimited by a double line is a multi-frame delimiter. As can be seen from the figure, the delimiters of the multiframes are completely synchronized for each F / S bit 7-1 to 7-5.

Along with the above operation, the F / S bit addition unit 31 in the DTC 3 shown in FIG.
Is each F / S bit 7- of the first frame of the multi-frame
Every time 1 to 7-5 is read, the head bit addition unit 32 is notified of that fact, so that the head bit addition unit 32 causes the multiplexing circuit to operate.
Via 33, every 3rd frame
In the 8M bit / s multiplexed signal 6 in the figure, the head bit 34 is added to the bit 7 of TS3 in the control channel 10. This is shown in FIG.

8M bit / s multiplexed signal 6 multiplexed as above
Is transmitted to the terminating device 5 via the DSM 4 in FIG. When the terminating device 5 establishes the synchronization of the respective 1.5M bit / s multiplexed signals 1-1 to 1-5 multiplexed with the 8M bit / s multiplexed signal 6, the control channel of FIG. Only by monitoring the head bit 34 added to the bit 7 of the TS3 of 10, it is possible to simultaneously establish multi-frame synchronization between the 1.5M bit / s multiplexed signals 1-1 to 1-5.

Therefore, the F / S of each 1.5M bit / s multiplexed signal 1-1 to 1-5
Bits 7-1 to 7-5 are used as signals for establishing synchronization in DT2-1 to 2-5 in FIG. 5 from DTC to DS.
For the M4 and the terminating device 5, the F / S bits 7-1 to 7-5 multiplexed in the 8M bit / s multiplexed signal 6 are not required for establishing synchronization. Meanwhile, each DT2
Also in -1 to 2-5, F / S bits 7-1 to 7-2
Does not necessarily require a pattern for establishing synchronization for each multiframe, and may include a pattern for establishing synchronization every few multiframes. Therefore, F / S bit 7
In -1 to 7-5, for example, control information or the like between exchanges can be placed at the position indicated by "*" of the S bit in FIG. Therefore, by multiplexing each F / S bit 7-1 to 7-5 on the 8M bit / s multiplexed signal 6, the DS of FIG.
The M4 or the terminating device 5 can be provided with a function of transmitting the control information.

〔The invention's effect〕

According to the present invention, when a terminating device (not shown) which receives the second time division multiplexed signal establishes synchronization of each of the first time division multiplexed signals, any one of the first times is used. If the synchronization is established only for the F / S bits related to the division multiplexed signal, the synchronization can be established for all the first time division multiplexed signals.

In particular, when each F / S bit is multiplexed in the second time division multiplexed signal, by adding delimiter information, the terminating device or the like only monitors this delimiter information so that all the first
The synchronization can be established with respect to the time division multiplexed signal, and it is not necessary to perform the synchronization establishing operation for any of the F / S bits.

As a result, the circuit scale for establishing synchronization in the terminating device or the like can be reduced, and the processing speed can be improved and the cost can be reduced.

Further, as a result of eliminating the need to put a pattern for establishing synchronization on the F / S bit, it becomes possible to put arbitrary information (inter-station control information etc.) on them.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a block diagram of an embodiment of DT and DTC according to the present invention, and FIG. 3 shows an 8M bit / s multiplexed signal format in the embodiment of the present invention. FIG. 4 is a diagram showing the contents of TS3 of an 8M bit / s multiplexed signal in the embodiment of the present invention, FIG. 5 is a block diagram of a digital switching system, and FIG. 6 is a 1.5M bit. FIG. 7 is a diagram showing a / s multiplexed signal format, FIG. 7 is a diagram showing an 8M bit / s multiplexed signal format in a conventional example, FIG. 8 is an explanatory diagram of F / S bits, and FIG. 9 is FIG. 7 is a diagram showing the contents of TS3 of an 8M bit / s multiplexed signal in a conventional example. 12-1 to 12-N ... First time division multiplexed signal, 13 ... Second time division multiplexed signal, 14-1 to 14-N ... F / S bit, 15-1 to 15- N ... F / S bit extraction means, 16-1 to 16-N ... buffer means, 17 ... F / S bit multiplexing means, 18 ... delimiter information adding means, 19 ... delimiter information.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Kakuma 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Naoyuki Izawa 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yuzo Okuyama 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Within Fujitsu Daiichi Communication Software Co., Ltd.

Claims (2)

[Claims] 1. A signal transmission system for concentrating and multiplexing a plurality of first time division multiplexed signals (12) to transmit as a second time division multiplexed signal (13), wherein each of the first time division multiplexed signals is used. Each of the first time division multiplexed signals (12) for extracting F / S bits (14) which are inserted into the encoded signal (12) for each predetermined time division unit and which form one information unit with a predetermined plurality of bits. F / S bit extraction means (1
5) and buffer means (16) provided for each of the first time division multiplexed signals (12) capable of temporarily storing the extracted F / S bit (14) and independently controlling writing and reading And the F / S bit (1
4) F / S bit multiplexing means (17) for synchronously reading in the information unit and multiplexing with the second time division multiplexed signal (13) Synchronization establishment method. 2. The F / S bit multiplexing means (17) converts each of the F / S bits (14) into the second time division multiplexed signal (1).
When it is multiplexed in 3), it has a delimiter information adding means (18) for adding delimiter information (19) common to each F / S bit (14) for each information unit. F / S bit synchronization establishment method described.