JPH07200404A - Cache memory using dram - Google Patents

Abstract

PURPOSE: To constitute a secondary cache which can operate with zero weight against a processor by using a DRAM and a system having a small area and small power consumption. CONSTITUTION: A data memory of a secondary cache is constituted by means of a DRAM and integrated on a single chip together with a control logic and a tag memory. At the same time, four words which are continuously accessed are interleaved in different rows and stored in the data memory. Thus, a DRAM access operation is attained at an apparently very high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to speeding up a secondary cache memory connected to a high performance microprocessor. In particular, it relates to means for realizing this using a DRAM memory.

[0002]

2. Description of the Related Art The access speed from a high performance microprocessor to a main memory is generally considerably slower than the operating speed (clock speed) of the processor. For example, the access time of the DRAM main memory viewed from the main clock is about 120 to 150 ns, while the clock speed of the processor is often 15 ns (66 MHz) or higher. If such a difference in speed is left as it is, the use efficiency of the processor is reduced and the system performance is obviously lowered. Therefore, the cache memory that can be accessed at a higher speed between the processor and the main memory is used, and frequently used data is accessed from the cache memory to shorten the data access time and fully utilize the processor performance. This has been widely done in the past. Therefore,
Achieving a high-speed cache memory is an important factor in achieving the full performance of the processor.

For this reason, in recent years, it has been generally practiced to mount a cache memory on the same chip as the processor to increase the speed. However, mounting the cache memory on the same chip in this way is limited by the problem of the chip area. In other words, it is difficult to mount a large capacity cache memory, and it is currently possible to mount a cache memory of about 4 to 32 kB. Note that mounting on the same chip in this manner is called "on-chip", and the cache memory directly mounted and connected to the processor in this way is called a primary cache.

In order to solve the capacity restriction associated with the implementation of the on-chip cache, the cache memory is constructed in about two stages according to the access frequency of the data, and the most frequently accessed data is stored in the primary cache ( L2) is frequently stored in the secondary cache (L2) with respect to data that is frequently accessed next. That is, as shown in FIG. 1, 4 to 32 are usually mounted on the same chip as the microprocessor (CPU).
A primary cache of about kB is implemented, and 12 external caches are installed.
The system is configured by connecting a secondary cache of 8 to 512 kB. Here, FIG. 1 shows an example of a two-way set associative cache having a cache line length of 128 bits. As the tag information, 18 bits per cache line are assumed.

Here, in order to make full use of the performance of the processor, it is necessary to use a high speed memory having an access time comparable to the cycle time of the processor even in the secondary cache. If the processor is 5
In the case of operating at 0 MHz, it is general to configure this by a high speed SRAM having an access time of about 10 to 20 ns.

The cache memory is composed of a cache tag memory and a cache data memory. The former has a function of processing the accessed contents by a logic circuit to judge cache hit / miss. Therefore, a memory faster than the cache data memory is required, but the information for the determination is stored by being represented by only the address bit for each cache line and a few status bits, and therefore a relatively small capacity. Memory is enough. On the other hand, the latter is a part that actually stores data and requires a large capacity. Based on the difference in the required characteristics between the two, the former is integrated in the cache controller, and the latter is realized by using several independent high-speed SRAM chips, or the former is also realized by using independent and higher-speed SRAM chips. It

In this case, the number of SRAM chips used for the cache data memory is, for example, eight 32 kB high-speed SRAM chips when forming a 256 kB cache.

However, according to the method of using a plurality of SRAM chips, some problems are raised.
First, there is a mounting area problem. According to this method, CP
One cache controller that requires the same number of I / O pins as U and 4 to 8 high-speed SRAMs are required. This often requires a mounting area several times that of the CPU body.

Secondly, there is a problem of power consumption. A large number of high-speed SRAMs are active at the same time, which consumes a large amount of power. The generation of heat associated therewith also poses a problem.

The third problem is the limit of the number of ways. Generally, as a method of improving the hit rate of the cache memory without increasing its capacity, a method of assigning several ways to the same address (set associative cache) is used. The greater the number of ways, the higher the hit rate. However, in order to realize, for example, a 4-way associative cache, four times as many data bits as the data width of the processor must be simultaneously accessible. In order to realize a configuration corresponding to the SRAM by using an SRAM chip having a large bit width, it is conceivable to use a large number of small-capacity chips.
Both have cost problems.

Further, in consideration of wiring delay in the cache area, signal skew, etc., it is necessary to design in consideration of the timing margin. That is, since the operation of the SRAM is substantially delayed due to such a cause, it is required to use the SRAM having an access time several ns faster than the original target of 15 ns to compensate for this delay. A design for suppressing such wiring delay, signal skew, etc. is required, but this is a very difficult problem.

Finally, the cost problem is unavoidable. This is because the use of a plurality of high speed SRAM chips makes them very expensive.

Next, the conditions necessary for the 0-wait secondary cache will be described from the viewpoint of its operation. Here, "0 wait" means a mode in which continuous access is possible without consuming wasteful waiting clock cycles. This is the goal of the present invention, because the processor's capabilities can be fully utilized when operating in this manner. Figure 2
Shows the operation in this case. This figure shows 486Dx2 / 66
This is a description for the case of MHz. When the read access of the CPU misses in the L1 cache, the data is read from the outside by the burst transfer of 32 bits each to the primary cache (on-chip) of the cache line length of 128 bits (16 bytes) by 32 bits. In this situation, in order for the secondary cache to supply data to the L1 cache in the 0 wait operation, the first word transfer must be completed with 2 bus clocks, and the transfer of the following 3 words must be completed with 1 bus clock each. There is. That is, the former (called a read-off cycle) needs to operate at 60 ns, and the latter (called a burst cycle) needs to operate at 30 ns.

It should be noted that these values do not directly represent the required access time characteristics. This is because a signal delay for starting the address cycle of the CPU and a data setup time for the CPU are required for the read-off cycle, and a data set-up time for the CPU is required for the burst cycle. Therefore, it is eventually necessary to realize the access time as shown in Table 1.

[Table 1] Cycle time Access time Read-off cycle 60 30 Burst cycle 30 15 (Unit: ns)

One of the constraints is that the access time required for each cycle is different. For example, if the secondary cache is configured to use the SRAM so as to conform to this, it is necessary to select the high-speed SRAM based on the faster access time of 15 ns. This means that over-spec is acceptable, considering the access time of the read-off cycle.

In order to prevent the waste caused by the difference in access time between the read-off cycle and the burst cycle, it is possible to use a DRAM memory chip. In the DRAM memory chip, the data for one row selected by the row address is buffered in the sense amplifier, and for the word to be accessed thereafter, this is done only by changing the column address in the row. Therefore, a relatively long time is required for the first word access, but an extremely short time is sufficient for the subsequent access by changing the column address. This type of access is called page access. This is very compatible with the access time ratio of the read-off cycle and the burst cycle shown in Table 1, and it is considered that the use of DRAM has a great advantage as compared with the case of using SRAM.

However, if a DRAM memory chip is used, the following two problems will occur. First, the DRAM memory chip has a large absolute value of access time and does not satisfy required characteristics. That is, in the DRAM memory chip, the access time of the first word and the page access time after that are 60 and 30 ns, respectively.
However, the time required is about twice the required characteristics.
Next, there is the data width problem. If a general-purpose DRAM is used, even if a cache memory having a number of ways of about 2 ways is realized, many modules need to be arranged in parallel. The adverse effects such as mounting area and power consumption due to this have been described.

As described above, when the DRAM memory chip is simply used, the secondary cache for realizing 0-wait access cannot be constructed at a practical level by the conventionally known method.

[0019]

As is clear from what has been described above, an object of the present invention is to realize a secondary cache sufficient to fully bring out the performance of the processor.

Then, this realization method needs to be practical. That is, it is desirable that the mounting area required for the cache data memory be significantly reduced and that the power consumption and the amount of heat generated be small.

[0021]

In view of the above problems, the present invention integrates a DRAM memory on a logic chip and has the advantage of a small area and low power consumption of the DRAM and the cycle of row address access of the DRAM memory. Utilizing the fact that the cycle time of page mode access is different, it was a problem when simply using a general-purpose DRAM memory chip.
By improving the absolute value of the access time viewed from U, a secondary cache capable of 0 wait operation is realized.

The cache memory originally appeared for the purpose of compensating for the delay of the main memory which is originally composed of DRAM. From such a background, there was no idea to configure the cache memory with the DRAM (generally considered to be slow) configuring the main memory. The present invention intends to divert the DRAM memory to various features such as a low area and a low cost, and intends to divert it to the cache memory. In this respect, the idea is reversed from the flow of the conventional technique, and this is completely different. It is a thing.

Further, in the set associative cache, the number of banks of the cache data memory is increased by interleaving and storing data in units of the data bit width of the CPU between a plurality of cache lines selected as the same set. Without this, the apparent access time and cycle time of the DRAM memory are increased, and at the same time concealment of the precharge time of the DRAM memory is realized.

[0024]

EXAMPLE FIG. 3 shows an example according to the present invention. In this embodiment, four SRAM blocks having a 4kx36b structure are used as a cache tag memory, and a DRA having a 64kx18b structure is used as a cache data memory.
Each of them is configured by using four M blocks. With this configuration, a 2-way set associative 512 KB secondary cache with a line length of 128 bits is realized.

Next, the contents of the tag memory and the data memory are shown in FIGS. 4-A and 4-B, respectively. As shown in FIG. 4-A, tag information corresponding to two cache lines of the same set is arranged at the same address in the SRAM of the tag memory. Two cache lines of this same set are shown in FIG.
As shown in -B, the data is arranged in units of 36 bits (32 bits for data + 4 bits for parity) on four consecutive addresses of the DRAM block. These four consecutive addresses are physically present in the same row of the DRAM, and the page mode enables high-speed access. The use of the page mode is premised because this mode matches the tendency of the access time in each cycle of read-off and burst as shown in Table 1.

It is assumed that such a secondary cache is constructed, a cache miss occurs in the primary cache, and a hit occurs in the secondary cache. At this time, the data resulting from the hit is line-filled in the primary cache by a 32-bit x 4 burst transfer. The timing chart at this time is shown in FIG. In this example, the processor bus clock is assumed to be 33 MHz and the secondary cache operating clock is assumed to be 66 MHz. Explaining according to this figure, access to the tag memory and cache data memory is started in the latter half of the T1 bus cycle of the processor.
The cache data memory simultaneously reads the corresponding word positions of two cache lines of the same set. In this example, the first word DA1, of cache lines A and B
Leading DB1. After determining which cache line is hit, the remaining words (DA2, DA3, DA4) of the corresponding cache line are read from the DRAM block using the page mode. In this example, the access time of the first word and the access time of the subsequent words of the block of the DRAM memory are 3 respectively.
Since it is 0,15 ns, it meets the required characteristics.

As described above, by using the technique of mounting the DRAM memory on the chip, it is possible to realize a high-speed secondary cache adapted to the required characteristics. For example, by integrating the DRAM memories on the same chip, the signal delay between the chips, which is necessary when these memories are configured on different chips, is omitted. Address signals and control signals given to the cache data DRAM and the DRAM memory are given from the control circuit. However, in the case of another chip configuration, these signals are I / O of the control circuit.
Delay time of O driver (for example, about 5 ns) and DRA
Delay time of the I / O receiver of the M memory chip (for example, 2
ns) is added. If they are integrated on the same chip, these are obviously unnecessary, so that high-speed access can be realized.

This point will be specifically described with reference to FIG. 8 in the case of reading data from the secondary cache. In this description, a read operation for a cache using a DRAM memory chip in which a conventional data memory is not mounted on the same chip will be considered. First, the address and command to be read by the control logic is generated. This is the DRA via the I / O driver and I / O receiver.
M data cache. Next, the data is found in the DRAM data cache, and it is returned to the logic circuit via the I / O driver / I / O receiver again. Then, the data is finally transferred to C through the I / O driver.
Output to PU. According to the present invention, when the cache is integrated on the same chip, the I / O
Since the driver / receiver has a total of five passes, which is reduced to only one pass of the final I / O driver, the delay of 10 to 20 ns is eliminated when the above delay time is taken into consideration.

Another reason for improving the access performance of the DRAM when mounted on the same chip is that the DRAM memory integrated on the logic chip is a general-purpose DRA.
It can also be mentioned that the restrictions on the capacity / chip area are not as severe as for M memory chips. For example, even when finally configuring a 16 Mbit DRAM memory, 1 Mb
The following blocks can be implemented as a unit. As a result, the load on the word line driver, the sense amplifier, etc. is reduced, and as a result, the characteristics of the original general-purpose DRAM can be improved considerably.

Further, the problem of the bit width, which is a problem when using the general-purpose DRAM, can be solved by integrating the DRAM memory on the logic chip. When integrating in a logic chip, it is not necessary to take all data bits out through the I / O cells.
In other words, only the number of bits required for data transfer with the processor need be taken out through the I / O cell. As a result, it is possible to freely use a considerably wide bit width, and it becomes easy to realize a set associative cache.

Further, if the data memory is not mounted on the same chip, a large number of bits will be driven through the I / O driver, but this is difficult due to power supply noise restrictions. Further, in the case of a general-purpose DRAM chip, it is not appropriate to use an unnecessarily wide data bit width due to package cost restrictions.

Next, the access time of the DRAM memory is L
This section describes a device that effectively demonstrates the performance of the processor when the speed is slower than the speed required to realize the 2-cache. In this case, a special data arrangement in the cache data memory is used as shown in FIG. Such a method of "alternating" is called interleaving. In this embodiment, two cache lines of the same set are interleaved on a word-by-word basis, and two adjacent words of the same cache line are placed in independent DRAM blocks that can be accessed simultaneously.

Although this arrangement has a DRAM memory access time suitable for the read-off cycle of the first word,
It is particularly effective as a solution when the page mode access time is too slow to realize the burst cycle of the second word and thereafter without waiting.

Specifically, two words DA1 and DB1 are accessed from the DRAM memory in the read-off cycle of the first word. Assuming now that a cache hit occurs in set A, in the subsequent burst cycle, DA
Although 3 words of 2, DA3 and DA4 need to be accessed, it is possible to access DA3 in parallel with the access of DA2. As a result, the same effect as shortening the page mode access time of the DRAM memory is realized.

The interleave method itself has been known for a long time, and can be easily realized by preparing memory banks for the number of ways of interleaving. However, the particularly excellent point of this method is that it is used for the set associative cache. Using multiple memory banks already prepared,
By interleaving a plurality of cache lines to which the same set belongs, it is not necessary to newly divide the memory bank.

By adopting such a system, the DRA
The problem of precharge time, which is a problem peculiar to M, can also be solved. The precharge time is a quiescent period required after the DRAM is accessed until the next access can be accepted. In a situation where the processor continuously accesses the secondary cache, the precharge time itself becomes the pause time of the entire cache, which causes the processor performance to be insufficient. By adopting this method, the access time is apparently shortened, so that the preceding access becomes possible, and the precharge time can be secured while the previously accessed word is returned to the processor.

Now, as described above, not the SRAM but the DR
The disadvantage of using AM memory is that DRAM requires memory refresh. The refresh operation is typically for one memory row,
It is necessary in a cycle of about 16 ms, and the required time is 10
It is about 0 ns. Since it is necessary to perform the refresh for each row, in the case of the DRAM memory having 1024 rows, the refresh operation is sequentially performed 1024 times within the 16 ms time. Since the secondary cache cannot service the processor while refreshing, the accumulated unserviceable time is 10
0nsx1024 = 0.1ms or so, which is 16
It occupies about 0.6% of the ms refresh period. Such a refresh operation does not immediately degrade the performance of the processor by the ratio of the time occupied in the refresh cycle. However, in the environment where the secondary cache is frequently accessed, some deterioration of the processor performance may occur, so it is desirable to effectively prevent this.

In the present invention, this adverse effect resulting from the adoption of the DRAM memory is solved by the method of executing the refresh operation during the period in which it is guaranteed that no activity will occur in the secondary cache. Here, the “period in which no activity occurs” is specifically a secondary cache miss or I / O.
A situation in which both the processor and the secondary cache are waiting for a termination signal from the outside due to access or the like.

FIG. 7 is a timing chart when the secondary cache misses and the refresh operation is performed during the data access to the main memory. As described above, data access to the main memory requires a considerably long time, and when the data access is completed, the RDY signal is issued from the main memory to the processor. A refresh cycle is set in the period until the generation of the RDY signal. Since this refresh is performed for each memory row, a refresh address counter for specifying which address row is refreshed is provided. Then, this counter is incremented by +1 every time the refresh operation is completed for one row. When the counter does not indicate the last row after the lapse of 16 ms, which is the refresh cycle, there is a memory row that has not been refreshed. Therefore, in this case, the remaining memory rows are collectively refreshed. By adopting such a scheme, the refresh cycle can be concealed, so that the deterioration of the performance of the processor can be minimized.

Here, how much the refresh cycle can be hidden by this method will be shown by calculation. According to the present invention, in the state where the secondary cache is line-filling the primary cache with 0 wait,
The line fill of the primary cache is completed once in 150 ns. That is, it has the ability to execute the primary cache line fill about 166000 times during the refresh period of 16 ms. Even if it is assumed that access from the primary cache to the secondary cache occurs at about 1/5 of this maximum capacity (this is an extremely small assumption),
The number of times is 3000 during the refresh cycle of 16 ms.
It will be about 0 times. Therefore, if the secondary cache miss occurs 1024 times or more during the access to the secondary cache of 30,000 times, all the memory rows can be refreshed during the refresh cycle. Usually, the hit rate of the secondary cache is at most about 90%, which means that 3000 secondary cache misses will occur during the refresh period, which is necessary.
Greatly exceeded four times. Therefore, according to this method, the refresh cycle can be hidden almost completely.

Focusing on the point that the cache memory is composed of a DRAM memory, for example, in a remote processing system, when a delay caused by a large physical distance between a central large capacity memory and each processor node becomes a problem, A method is conceivable in which a private cache memory for storing data frequently exchanged with the processor nodes is configured by a DRAM memory in addition to the central large capacity memory and installed near each processor node. In this case, the delay is mostly due to the physical distance between the central mass memory and the processor node,
Even if the private cache memory configured by the DRAM memory is not very high speed, it can contribute to the improvement of access speed. Of course, it is obvious that the access speed can be further improved by using the present invention for such an application.

[0042]

According to the present invention, a cache memory which cannot be constructed by a conventional DRAM memory can be constructed by using a DRAM memory. And this would allow the cache memory to be very small and inexpensive.

Further, according to the present invention, the secondary cache which can operate with 0 wait for the processor can be realized by the DRAM memory having a small area and low power consumption. When the page mode is used, the storage in the cache data memory is interleaved between a plurality of cache lines belonging to the same set, so that the 0 wait operation can be performed using the DRAM memory that is substantially slower than the cycle time of the processor. Become. Furthermore, the refresh overhead inherent to the DRAM memory is almost completely eliminated by the method of refreshing the DRAM memory during the period in which it is guaranteed that no activity will occur with respect to the secondary cache. Then, by combining these, it becomes possible to construct a secondary cache that can fully utilize the performance of the processor.

[Brief description of drawings]

FIG. 1 is a diagram showing a general connection between a processor, a primary cache, and a secondary cache.

FIG. 2 is a timing chart when line filling is performed on the primary cache in a 0 wait operation.

FIG. 3 is an example of second level cache implementation.

FIG. 4 is a diagram showing an arrangement of data in a tag memory and a data memory of a secondary cache.

FIG. 5 is a timing diagram of secondary cache access related to 0 wait operation according to the present invention.

FIG. 6 is an embodiment in which data is stored in an interleaved arrangement in cache lines of the same set.

FIG. 7 is a timing diagram of DRAM refresh according to the present invention.

FIG. 8 shows an I / O driver and an I / O with an external DRAM.
It is a figure at the time of exchanging data via a receiver.

Claims (8)

[Claims] 1. A processor, a primary cache that is connected to the processor and transfers data to each other, and has a larger capacity than the primary cache, is connected to the primary cache, and is requested by the processor in the primary cache. In a data processing system including a secondary cache that is accessed when data does not exist, the secondary cache has a control logic circuit which controls the control, a tag memory which stores address information of the secondary cache,
A data processing system, comprising a data memory for storing data requested by a processor, wherein the data memory is a DRAM memory and is integrated on the same chip as the control logic circuit and the tag memory. 2. The data processing system according to claim 1, wherein the data memory is composed of cells of a unit of 2 Mb or less. 3. The data processing system according to claim 1, wherein the data memory stores interleaved data of several words to be continuously read. 4. The data processing system according to claim 1, wherein the data memory performs a refresh operation by selecting a time when there is no external activity to the secondary cache. 5. The refresh operation is performed based on an instruction from a counter that identifies an address row to be refreshed, and the refresh is completed when the counter does not indicate the last address row after a refresh cycle has elapsed. Refresh all memory rows,
The data processing system according to claim 4. 6. A cache memory connected between a processor and a main memory, in which at least a control logic circuit for controlling the control, a tag memory for storing address information, and a data memory requested by the processor are on the same chip. A cache memory, wherein the data memory comprises a DRAM. 7. A remote data processing system in which a DRAM is applied as a cache data memory in the vicinity of each processor node in addition to a central large capacity main memory, and a private cache memory for storing frequently transferred data is installed. 8. The private cache memory is configured by integrating at least a control logic circuit for controlling the control, a tag memory for storing address information, and a data memory requested by a processor on the same chip. 7. Remote data processing system.