JPH07193148A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a drain region with an optimum structure for writing characteristics and a source region with an optimum structure for improving erasure characteristics by further implanting impurities into the other impurity region which should become a source region while one impurity region which should become a drain region is covered with a mask. CONSTITUTION:This semiconductor device is provided with a first conductive type semiconductor substrate 301, an electrode layer 309 formed on the main surface, and the regions of a source 313 and a drain 310 formed on the main surface of the semiconductor substrate 301 with a spacing so that a channel region can be formed below an electrode layer 309. The drain region 310 includes a second conductive type impurity layer 310a and a first conductive type impurity layer 310b surrounding it. The source region 310 includes a second conductive type impurity layer 313a, a second conductive type low-concentration impurity layer 313b with a lower concentration than it and located below it, and a first conductive type impurity layer 324 with a lower concentration than the drain region while being positioned between the channel region and the second conductive type impurity layer 313a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrode layer, a source region and a drain region, and more particularly to a structure and a manufacturing method of a semiconductor device capable of reducing the number of manufacturing steps. More specifically, the present invention relates to improvements in the structure and manufacturing method of a flash memory that can be electrically written and erased.

[0002]

2. Description of the Related Art There is known a flash memory in which data can be freely written and information charges written can be electrically erased.

FIG. 10 is a block diagram showing a general structure of a flash memory. The flash memory includes a memory matrix 100 arranged in a matrix and X
It includes an address decoder 200, a Y gate 300, a Y address decoder 400, an address buffer 500, a write circuit 600, a sense amplifier 700, an input / output buffer 800, and a control logic 900.

The memory cell matrix 100 has a plurality of memory transistors arranged in a matrix therein. An X address decoder 200 and a Y gate 300 for selecting rows and columns of the memory cell matrix 100.
And are connected. The Y-gate 300 is connected to a Y-address decoder 400 which gives column selection information. X address decoder 200 and Y address decoder 4
An address buffer 500 for temporarily storing address information is connected to 00.

A write circuit 600 for performing a write operation at the time of data input and a sense amplifier 700 for determining "0" or "1" from the current value flowing at the time of data output are connected to the Y gate 300. There is. An input / output buffer 800 for temporarily storing input / output data is connected to each of the writing circuit 600 and the sense amplifier 700. A control logic 900 for controlling the operation of the flash memory is connected to the address buffer 500 and the input / output buffer 800. The control logic 900 performs control based on the chip enable signal, the output enable signal and the program signal.

FIG. 11 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. Referring to FIG. 11, a plurality of word lines WL extending in the row direction
_1, WL _2, ..., and WL _i, a plurality of bit lines BL _1, BL ₂ extending in the column direction, ..., are arranged such that the BL _j are orthogonal to each other to form a matrix. Memory transistors Q ₁₁ , Q ₁₂ , ..., Q _ij each having a floating gate are arranged at the intersections of each word line and each bit line. The drain of each memory transistor is
It is connected to each bit line. The sources of the memory transistors are connected to the respective source lines S ₁ , S ₂ , ..., S _i . The sources of the memory transistors belonging to the same row are connected to each other as shown.

FIG. 12 is a block diagram 1 showing a flash memory.
The cross-sectional structure of two memory transistors is shown. The illustrated flash memory is called a stack gate type. FIG. 13 shows a planar arrangement of a conventional stack gate type flash memory. In the figure, a first conductive layer 26 and an interlayer insulating film 1 which will be described later for convenience.
6, the bit line 18 is not shown. 14 is the same as FIG.
It is sectional drawing seen along the WW line in the inside. The structure of the conventional flash memory will be described with reference to these drawings.

SiO _{2 is} formed on the main surface of the p-type semiconductor substrate 1.
Floating gates 3 made of (m × n) polysilicon arranged in a matrix of m rows and n columns are arranged through a first insulating film 2 made of. An element isolation region 9 is formed between each column of the floating gates 3 that extends over two adjacent columns. A second insulating film 4 made of SiO ₂ or the like is formed on the floating gate 3.
Control gates 25 made of polysilicon, which extend in the row direction, are formed for each row via the.

On the main surface of the semiconductor substrate 1 in the region surrounded by the element isolation region 9 and the floating gate 3, the impurity concentration is 5 × 10 ¹⁹ / c over a predetermined depth.
An n-type drain region 13 composed of m ³ and a sheet resistance of 80Ω / □ is formed. In addition, this drain region 13
On the main surface of the semiconductor substrate 1 in the region outside the floating gate 3 with the impurity concentration of 1 × over a predetermined depth.
An n-type source region 14 of 10 ²¹ / cm ³ and a sheet resistance of 50Ω / □ is formed.

A third portion is formed to cover the floating gate 3 and the control gate 25 and partially overlap the drain region 13 and the source region 14.
The insulating film 7 and the fourth insulating film 15 are formed.

A fourth insulating film 1 is formed on the drain region 13.
A first wiring layer 2 made of polysilicon and formed along the side wall of 5 and electrically connected to the drain region 13.
6 is provided. In the first wiring layer 26, a refractory metal material formed on the drain region 13 so as to extend further upward, for example, tungsten (W).
The second wiring layer 27 made of, for example, is connected. Second
The wiring layer 27 is connected to n bit lines 18 formed on the interlayer insulating film 16. The interlayer insulating film 16 includes the third insulating film 7, the fourth insulating film 15, and the first wiring layer 2.
It is formed so as to cover 6.

Next, regarding the operation of the flash memory,
This will be described with reference to FIG. First, in the write operation,
A voltage V _{D of} about 3 to 7 V is applied to the n-type drain region 13, and a voltage V _{G of} about 9 to 13 V is applied to the control gate 25. Further, the n-type source region 14 and the p-type semiconductor substrate 1 are kept at the ground potential. At this time, a current of several hundred μA flows in the channel of the memory transistor. Among the electrons flowing from the source region 14 to the drain region 13, the electrons accelerated in the vicinity of the drain region 13 become electrons having high energy in this vicinity, that is, channel hot electrons. Some of these electrons cross the energy barrier at the interface between the oxide film and the silicon substrate and are injected into the floating gate 3 as indicated by arrow A in the figure. When electrons are accumulated in the floating gate 3 in this manner, the threshold voltage V _{th of the} memory transistor is
Becomes higher. A state in which the threshold voltage V _th is higher than a predetermined value is written, which is called "0".

Next, in the erase operation, a voltage V _{s of} about 7 to 13 V is applied to the n-type source region 14, and the control gate 25 and the p-type semiconductor substrate 1 are held at the ground potential. The n-type drain region 13 is opened. Due to the electric field generated by the voltage V _s applied to the n-type source region 14, the electrons in the floating gate 3 pass through the thin gate oxide film 2 due to the tunnel phenomenon, as shown by the arrow B in the figure. In this way, the electrons in the floating gate 3 are extracted, so that the threshold voltage V _th of the memory transistor is lowered. This threshold voltage V _th
Is lower than the specified value, the erased state is "1"
Called. The source of each memory transistor is shown in FIG.
Since they are connected as shown in FIG. 5, it is possible to erase all memory cells at once by this erase operation.

In the read operation, the control gate 25 has a voltage V _{G of} about 5 V and the n-type drain region 13 has a voltage of 1 V.
A voltage V _{D of} about 2 V is applied. At this time, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory transistor, that is, whether the memory transistor is in the on state or the off state.

Next, the manufacturing process of the stack gate type flash memory having the above structure will be described with reference to FIGS.
Will be described with reference to. 15 to 30 sequentially show manufacturing steps of the stack gate type flash memory until the sectional structure shown in FIG. 14 is obtained.

Referring to FIG. 15, a memory cell region and a peripheral circuit region are located on the main surface of p type silicon substrate 1. First, 100 is formed on the entire main surface of the p-type silicon substrate 1.
A first insulating film 2 made of an oxide film having a thickness of about Å is formed. A first polysilicon layer 3 having a thickness of about 1000Å is deposited on the first insulating film 2 by the CVD method. Then, the polysilicon 3 is etched using the resist patterned at a predetermined pitch as a mask. At this time, the polysilicon layer on the peripheral circuit region is removed.

Next, a second film is formed on the entire surface of the p-type silicon substrate 1.
The insulating film 4 is formed. The second insulating film 4 is a three-layer laminated film. Specifically, first, an oxide film with a film thickness of about 100 Å is formed, a nitride film with a film thickness of about 100 Å is formed thereon by a CVD method, and an oxide film with a film thickness of about 100 Å is further formed thereon. , The second insulating film 4 is formed. After that, the second insulating film 4 on the peripheral circuit region is removed except the memory cell region.

After that, a second polysilicon layer 25 having a thickness of about 2500 Å is formed on the entire surface of the substrate, and a third insulating film 7 is further formed thereon. A resist 28 is formed on the third insulating film 7 so as to cover the entire memory cell region and be patterned in a predetermined shape on the peripheral circuit region. By performing etching using this resist 28 as a mask, the gate electrode 25 of the transistor in the peripheral circuit region is formed.

Referring to FIG. 16, after removing the resist 28, a resist 29 is formed on the third insulating film 7 so as to cover the entire peripheral circuit region and have a predetermined pattern as shown in FIG. To do. Anisotropic etching is performed using the resist 29 as a mask to sequentially etch the third insulating film 7, the second polysilicon layer 25, the second insulating film 4, and the first polysilicon layer 3 to cause floating. The gate 3 and the control gate 25 are formed. Then, the resist 29 is removed, and the state shown in FIG. 17 is obtained.

FIG. 18 is a plan view schematically showing the shape of the resist mask shown in FIG.

Referring to FIG. 19, a resist 30 is formed on the main surface of silicon substrate 1 serving as a source region. Using the laminated structure of the floating gate 3 and the control gate 25 and the resist 30 as a mask, arsenic (As) in the silicon substrate 1 is 35 keV, 5.0 × 10 ¹⁴ / c.
Introduced under the condition of m ² to form the drain region 13 composed of an n-type impurity region having a concentration of 5 × 10 ¹⁹ / cm ³ and a sheet resistance of 80Ω / □.

Referring to FIG. 20, after removing resist 30, the surface of drain region 13 is covered with resist 31.
Using the laminated structure of the floating gate 3 and the control gate 25 and the resist 31 as a mask, arsenic (As) in the silicon substrate 1 is 35 keV, 1 × 10 ¹⁶ / c.
Introduced under the condition of m ² and having a concentration of 1 × 10 ²¹ / cm ³ and a sheet resistance of 50 Ω / □, a source region 1 made of an n-type impurity region.
4 is formed.

Referring to FIG. 21, resist 31 is removed and then fourth insulating film 15 is formed on the entire surface of silicon substrate 1. Then, by etching the fourth insulating film 15 by anisotropic etching, as shown in FIG. 22, the floating gate 3 and the control gate 25 are removed.
A sidewall insulating film 15 is formed on the side surface of the laminated structure of.

Referring to FIG. 23, a fifth insulating film 32 is formed on the entire surface of silicon substrate 1. Then, referring to FIG. 24, a resist 33 having an opening is formed only above the drain region 13, and the fifth insulating film 32 located on the drain region 13 is removed by etching using this resist as a mask.

Referring to FIG. 25, a polysilicon layer 26 is deposited on the entire surface of silicon substrate 1. Further, a resist 34 formed so as to cover the drain region 13 is formed on the polysilicon layer 26.

Referring to FIG. 26, polysilicon layer 26 is anisotropically etched using resist 34 as a mask to form a first region connected to drain region 13.
The wiring layer 26 is formed. Referring to FIG. 27, an interlayer insulating film 16 such as TEOS is deposited on the entire surface of silicon substrate 1,
After performing wet reflow for 30 minutes at about 900 ° C., the surface is flattened. Thus, the interlayer insulating film 16 shown in FIG. 28 is formed.

Referring to FIG. 29, a patterned resist 35 having holes above drain region 13 is formed on interlayer insulating film 16. The contact hole 27a is formed by anisotropically etching the interlayer insulating film 16 using the resist 35 as a mask.

Referring to FIG. 30, contact hole 27
A second wiring layer 27 made of a refractory metal such as tungsten (W) is formed inside a, and then a bit line 18 is formed to complete the stack gate type flash memory.

[0029]

Problems of the prior art will be described with reference to FIGS. 31 to 39.

31 to 34 illustrate a NOR type flash memory. In NOR flash memory,
A write operation is performed by injecting part of channel hot electrons generated near the drain into the floating gate. Further, the erase operation is performed by drawing electrons from the floating gate to the source by utilizing the FN (Fowler Nordheim) tunnel phenomenon.

Referring to FIG. 31, element isolation regions 101 are arranged in an island shape on the main surface of the semiconductor substrate. The element isolation region 101 and the floating gate 102
The region surrounded by and becomes the drain region 103,
The other area becomes the source area 104. The control gate 105 continuously extends on the floating gate 102. A bit line (not shown) is connected to the drain region 103 at the contact portion 106. The memory transistor is composed of an electrode layer in which a floating gate and a control gate are laminated, a source region, and a drain region.

FIG. 32 is a sectional view taken along the line XX in FIG. Illustrated memory transistor 107
Is the electrode layer 130 in which the floating gate 102 and the control gate 105 are stacked, and the drain region 1
03 and a source region 104.

The drain region 103 includes an n-type (n ⁺ ) impurity layer 103a and a p-type (p ⁺ ) impurity layer 103b surrounding the impurity layer. The n-type impurity layer 103a is set to an optimum concentration for improving writing characteristics. When the concentration is set to the optimum, electric field concentration is likely to occur due to the steep concentration gradient, and channel hot electrons are easily generated. The purpose of forming the p-type impurity layer 103b is to
This is for suppressing the leak current and improving the breakdown voltage.

The source region 104 is an n-type high concentration (n ⁺ )
An impurity layer 104a and an n-type low concentration (n ⁻ ) impurity layer 104b surrounding the impurity layer and having a lower concentration than the impurity layer are included. The n-type high-concentration impurity layer 104a is configured to partially overlap the floating gate 102. The n-type high concentration impurity layer 104a is set to have an optimum concentration for improving the erasing characteristics. n-type high concentration impurity layer 1
If 04a partially overlaps the floating gate 102 and is set to have an optimum concentration, the coupling between the source region 104 and the floating gate 102 becomes high, and it becomes easy to extract electrons by the FN tunnel phenomenon. The n-type low-concentration impurity layer 104b is formed for the purpose of preventing a leak current in the source line and improving the breakdown voltage of the source line.

N-type impurity layer 103 in the drain region 103
The value a is set to the optimum concentration so that channel hot electrons can be easily generated to improve the writing characteristics. On the other hand, the n-type high-concentration impurity layer 104a in the source region 104
Is set to an optimum concentration that effectively causes the FN tunnel phenomenon to improve the erasing characteristics. Since the drain region 103 and the source region 104 both have different purposes, the optimum concentrations are also different. Generally, the n-type high-concentration impurity layer 104a of the source region 104 is formed.
Has a higher concentration than the n-type impurity layer 103a in the drain region 103.

Next, a method for obtaining the memory transistor 107 having the structure shown in FIG. 32 will be described.

Referring to FIG. 33, p-type semiconductor substrate 110.
An electrode layer 130 in which the floating gate 102 and the control gate 105 are laminated is formed on the main surface of the with a space. In this state, the resist 111
Is deposited on the entire surface, and then the main surface of the semiconductor substrate 110 to be the drain region is exposed by patterning.

In the state shown in FIG. 33, arsenic (As) is added to the semiconductor substrate 110 at 35 keV, 5 × 10 ¹⁴ cm ^-2 , 0 °.
Inject under rotating conditions. Furthermore, bromine (B) is added to 50 ke
V, 3 × 10 ¹³ cm ⁻² , and 45 ° rotation.
As a result, as shown in FIG. 34, the n-type impurity layer 103
drain region 10 composed of a and p-type impurity layer 103b
3 is formed.

After that, the resist 111 shown in FIG. 33 is removed, and the resist 112 is deposited on the entire surface again. As shown in FIG. 34, this resist 112 is patterned so as to expose the main surface of semiconductor substrate 110 to be the source region. In this state, arsenic (As) is implanted into the semiconductor substrate 110 under the conditions of 35 keV, 5 × 10 ¹⁵ cm ⁻² and 7 ° rotation. Further, phosphorus (P) is set to 50 keV, 5
Implantation is performed under the conditions of × 10 ¹⁴ cm ^-2 and 0 ° rotation. As a result, as shown in FIG. 32, the n-type high concentration impurity layer 104a is formed.
Source region 1 composed of and n-type low-concentration impurity layer 104b
04 is formed.

In the conventional manufacturing method as described above, a mask aligning step and a photoengraving step are required to perform ion implantation for forming the drain region, and in addition to that,
A mask alignment step and a photolithography step are required for ion implantation for forming the source region. Therefore, the number of masks increases and the number of steps increases, resulting in higher manufacturing cost.

35 to 39 show a DINOR type flash memory. In the DINOR type flash memory, the writing operation is performed by drawing electrons from the floating gate to the drain by utilizing the FN tunnel phenomenon. The erase operation is performed by injecting electrons from the entire surface of the channel into the floating gate by utilizing the FN tunnel phenomenon.

Referring to FIG. 35, element isolation regions 210 and active regions 211 are alternately arranged on the main surface of the semiconductor substrate. The active region surrounded by the element isolation region 210 and the floating gate 212 becomes the drain region 213 and the source line region 214 alternately.

36 and 37 show YY in FIG.
It is sectional drawing seen along the line. 38 and 39 show
It is sectional drawing seen along the ZZ line in FIG.

Referring to FIG. 38, p-type semiconductor substrate 217
An electrode layer 216, in which a floating gate 212 and a control gate 215 are stacked, is formed on the main surface of the with a space. In this state, the source line region 214
Resist 21 exposing the main surface of the semiconductor substrate to be
8 is formed. Using the resist 218 as a mask, the field oxide film in the element isolation region 210 is etched. By this etching, as shown in FIGS. 36 and 37, field oxide film 219 located in source line region 214 is removed, and the active region is exposed.

Next, the resist 218 is removed, and the electrode layer 2 is removed.
16 is used as a mask, and arsenic (A
s) is injected under the conditions of 35 keV, 5 × 10 ¹⁵ cm ⁻² and 7 ° rotation. By this arsenic implantation, as shown in FIG. 39, drain region 213 and source line region 214 are simultaneously formed.

In the manufacturing method shown in FIGS.
Since the drain region 213 and the source line region 214 are simultaneously formed by performing the ion implantation once, the number of steps can be reduced. However, when the drain region 213 and the source line region 214 have different structures or different concentrations, the above method cannot be adopted.

An object of the present invention is to provide a semiconductor device provided with a drain region having a structure optimal for improving write characteristics and a source region having a structure optimal for improving erase characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the mask aligning step and the photolithography step.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device provided with a drain region having a structure optimal for improving write characteristics and a source region having a structure optimal for improving erase characteristics. That is.

[0050]

A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type having a main surface, an electrode layer formed on the main surface of the semiconductor substrate, and an electrode layer below the electrode layer. Source and drain regions formed on the main surface of the semiconductor substrate at intervals to form a channel region. The electrode layer has a structure in which a floating gate and a control gate are stacked.

The drain region has a second conductivity type impurity layer,
A first conductivity type impurity layer surrounding the second conductivity type impurity layer is included. The source region includes a second conductivity type impurity layer, a second conductivity type low concentration impurity layer located below the second conductivity type impurity layer and having a lower concentration than the second conductivity type impurity layer, the channel region and the second region. A first conductive type low concentration impurity layer located between the conductive type impurity layers and having a lower concentration than the first conductive type impurity layer in the drain region.

In the method of manufacturing a semiconductor device according to the present invention, first, an electrode layer is formed on the main surface of a semiconductor substrate with an insulating film interposed therebetween. Next, using this electrode layer as a mask, impurities are simultaneously implanted into the main surface of the semiconductor substrate to be the source and drain regions to form a pair of impurity regions. Next, with one of the impurity regions to be the drain region covered with a mask, impurities are further implanted into the other impurity region to be the source region.

In the above method, the impurity implantation for forming the pair of impurity regions is preferably performed under conditions suitable for forming the drain region. Further, the impurity implantation into the other impurity region to be the source region is performed under the conditions suitable for forming the source region.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, a semiconductor device of the first conductivity type is provided on the main surface thereof.
An electrode layer is formed by stacking a floating gate and a control gate. Next, by using the electrode layer as a mask, the first conductivity type impurity and the second conductivity type impurity are simultaneously implanted into the main surface of the semiconductor substrate to be the source and drain regions under conditions suitable for forming the drain region. A pair of impurity regions including a second conductivity type impurity layer and a first conductivity type impurity layer surrounding the second conductivity type impurity layer are formed. next,
In a state where one impurity region to be the drain region is covered with a mask, a second conductivity type impurity is implanted into the other impurity region to be the source region under conditions suitable for forming the source region, and further the first conductivity type is added. Impurities of the second conductivity type are implanted under conditions suitable to cancel the type impurity layer.

[0055]

In the semiconductor device according to the present invention, the drain region has the optimum structure for improving the writing characteristics. The second conductivity type impurity layer is set to have an optimum concentration that facilitates generation of channel hot electrons due to electric field concentration. The first conductivity type impurity layer contributes to suppression of leak current and improvement of breakdown voltage.

The source region has an optimum structure for improving erase characteristics. The second-conductivity-type impurity layer is set to an optimum concentration that enhances the coupling between the source and the floating gate and makes it easier to draw electrons by the FN tunnel phenomenon.
The second-conductivity-type low-concentration impurity layer contributes to prevention of leak current in the source line and improvement of withstand voltage of the source line. further,
The first-conductivity-type low-concentration impurity layer located between the channel region and the second-conductivity-type impurity layer contributes so that the overlapping width of the source region and the floating gate can be accurately set. It is possible to accurately control the amount of electron withdrawal due to the tunnel phenomenon.

In the method of manufacturing the semiconductor device according to the present invention, the source region is not covered with the mask when the drain region is formed. Therefore, the number of mask alignment steps and photolithography steps can be reduced.

In the manufacturing method of another aspect of the present invention, the drain region having the optimum structure is formed by simultaneously implanting the impurities into both the drain region and the source region. After that, the source region having the optimum structure is formed by implanting impurities into the semiconductor substrate with the drain region covered with a mask. Therefore, while reducing the number of mask aligning processes and the number of photoengraving processes,
It is possible to obtain a semiconductor device having excellent writing characteristics and erasing characteristics.

[0059]

1 to 5 show a NOR type flash memory. As described above, in the NOR flash memory, a write operation is performed by injecting a part of the channel hot electrons generated in the vicinity of the drain into the floating gate, and the FN tunnel phenomenon is used to discharge electrons from the floating gate to the source. The erase operation is performed by pulling out.

Referring to FIG. 1, on the main surface of p-type semiconductor substrate 301, a first insulating film 302, a first polysilicon layer 303 to be a floating gate, a second insulating film 304, a control layer are formed in this order from the bottom. A second polysilicon layer 305 to be a part of the gate, a metal silicide layer 306 to be a part of the control gate, and a third insulating film 307 are formed. In this state, using the resist 308 patterned into a predetermined shape as a mask, the third
The insulating film 307 is etched. Then resist 308
Of the metal silicide layer 306, the second polysilicon layer 305, the second insulating film 304, and the first polysilicon layer 3 using the patterned third insulating film 307 as a mask.
03 are sequentially etched to make the floating gate 303
An electrode layer 309 in which the control gates 305 and 306 are stacked is formed.

Next, as shown in FIG. 2, using the electrode layer 309 as a mask, arsenic (As) is implanted into the active region of the entire surface of the memory cell array under the conditions of 35 keV, 5 × 10 ¹⁴ cm ^-2 and 0 ° rotation. , Bromine (B) at 50 keV, 3 × 1
Implantation is performed under the conditions of 0 ¹³ cm ^-2 and 45 ° rotation. The impurity implantation conditions are set under conditions suitable for forming a drain region that can improve the writing characteristics.

By the above-mentioned impurity implantation, a pair of impurity regions 310 and 311 are formed sandwiching the electrode layer 309 as shown in FIG. One impurity region 310 is to be a drain region, and has an n-type (n ⁺ ) impurity layer 310a and a p-type (p ⁺ ) impurity layer 310b surrounding this impurity layer. Similarly, the other impurity region 3
11 also includes an n-type impurity layer 311a and a p-type impurity layer 311b surrounding this impurity layer.

Next, referring to FIG. 4, a resist 31 exposing the main surface of the semiconductor substrate 301 to be the source region is exposed.
No. 2 is formed, and using this resist 312 as a mask, arsenic (As) is added to the semiconductor substrate 301 at 35 keV, 5 × 10 ¹⁵
Implantation is carried out under the conditions of cm ⁻² and 7 ° rotation, and phosphorus (P) is further implanted under the conditions of 50 keV, 5 × 10 ¹⁴ cm ⁻² and 0 ° rotation. The impurity implantation conditions are set to be optimum for forming a source region that is optimum for improving the erase characteristic. By this impurity implantation, the influence of the n-type impurity layer 311a (FIG. 3) formed by implanting arsenic immediately after forming the electrode layer 309 can be ignored. In addition, the p-type impurity layer 311b formed by implanting bromine (B)
(FIG. 3) almost disappears due to the implantation of the n-type impurity, but remains just below the electrode layer 309.

Therefore, in the state shown in FIG. 4, phosphorus (P) is further added to the semiconductor substrate 301 at 130 keV, 3 × 10 ^13.
p − type impurity layer 31 is implanted under the conditions of cm ⁻² and 45 ° rotation.
Completely eliminate 1b. The phosphorus implantation conditions are set so as to be suitable for offsetting the p-type impurity layer 311b. Therefore, the dose amount and the rotation angle are the same. Since phosphorus has a smaller mass than bromine, the implantation energy is set high so that the implantation depth is the same.

Then, the resist 312 is removed to obtain the structure shown in FIG. The drain region 313 includes an n-type impurity layer 313a and an n-type low-concentration impurity layer 313b surrounding the impurity layer and having a lower concentration.

The n-type impurity layer 310 in the drain region 310
a is set to an optimum concentration that facilitates generation of channel hot electrons. Further, the p-type impurity layer 310b of the drain region 310 contributes to suppression of leak current and improvement of breakdown voltage. The n-type impurity layer 313a of the source region 313 is set to have an optimum concentration that enhances the coupling between the source and the floating gate and facilitates the extraction of electrons by the FN tunnel phenomenon. The n-type low-concentration impurity layer 313b in the source region 313 contributes to preventing a leak current in the source line and improving the withstand voltage of the source line.

In the above method, phosphorus is implanted into the semiconductor substrate under a predetermined condition in order to erase the p-type impurity layer 311b left immediately below the floating gate. What if p
If the type impurity layer 311b remains without disappearing, the coupling between the source and the floating gate is extremely increased, and it becomes difficult to control the amount of electron withdrawn by the FN tunnel phenomenon. Therefore, there is a high possibility that the erase operation will be over-erased. Therefore, it is necessary to perform impurity implantation for eliminating the high-concentration p-type impurity layer 311b.

According to the method shown in FIGS. 1 to 5, the mask aligning step and the photolithography step for forming the drain region are unnecessary. Further, a semiconductor device having excellent writing characteristics and erasing characteristics can be obtained.

In the above manufacturing method, the high concentration p-type impurity layer 311b immediately below the floating gate is erased, but it may be left as a low concentration p-type impurity layer. In that case, phosphorus (P) is added to the semiconductor substrate at 130 keV and 2.5 × 10 ^{13 in the} state shown in FIG.
Inject under the condition of cm ^-2 and 45 ° rotation. Since the dose amount of phosphorus (P) is slightly smaller than the dose amount of bromine (B) immediately after the formation of the electrode layer 309, as shown in FIG. 6, a low concentration p-type impurity layer 31 is formed immediately below the floating gate.
4 remains.

In the structure shown in FIG. 6, the low-concentration p-type impurity layer 314 is located between the n-type impurity layer 313a in the source region and the channel region. Therefore, the overlapping width of the source and the floating gate can be accurately controlled, and the amount of electron withdrawal due to the FN tunnel phenomenon can be accurately controlled. Thus, according to the structure shown in FIG. 6, the erase characteristic can be further improved.

7 to 9 illustrate the manufacturing process of the DINOR type flash memory. As mentioned above, DI
In the NOR flash memory, writing operation is performed by drawing electrons from the floating gate to the drain by using the FN tunnel phenomenon, and erased by injecting electrons from the entire surface of the channel to the floating gate by using the FN tunnel phenomenon. It is operating.

Referring to FIG. 7, electrode layers 402 are formed at intervals on the main surface of p-type semiconductor substrate 401. The electrode layer 402 has a structure in which a floating gate 403 and a control gate 404 are stacked. Using the electrode layer 402 as a mask, the p-type semiconductor substrate 401
Arsenic (As) in the inside, 35 keV, 5 × 10 ¹⁵ cm ^-2 ,
Inject under the condition of 7 ° rotation. The conditions for this impurity implantation are
It is set to optimize the structure of the drain region. The implantation of arsenic forms impurity regions 405 and 406 on both sides of the electrode layer 402. One impurity region 405 becomes a drain region.

Next, as shown in FIG. 8, the resist 4 exposing the main surface of the semiconductor substrate 401 to be the source region.
07 is formed and the field oxide film in the element isolation region is removed by etching using this resist 407 as a mask.

Next, as shown in FIG. 9, a resist 407 is formed.
Using as a mask, impurities are implanted into the semiconductor substrate 401 under conditions that optimize the source region. By this impurity implantation, the source region 408 having excellent erasing characteristics can be obtained.

The method shown in FIGS. 7 to 9 does not require a mask aligning step and a photolithography step for forming the drain region. Further, impurity implantation can be performed under optimum conditions for forming the drain region and the source region.

7 to 9 are DINOR type flash memos.
Although it showed the manufacturing process of the
You may change the conditions. For example, forming the electrode layer 402
Immediately thereafter, phosphorus (P) is added to the semiconductor substrate 401 in an amount of 30 to 4
0 keV, (1-10) x 10¹⁴cm^-2Injection under the conditions
In addition, arsenic (As) is added at 30-40 keV, (1-1
0) x 10¹⁵cm^-2By injecting under the conditions of
A pair of impurity regions may be formed on both sides of the layer. This article
In some cases, the structure of the drain region can be optimized and leakage
It becomes possible to suppress the current and improve the breakdown voltage. It
In addition, the writing characteristics can be improved. Then the element
Etching away the field oxide in the isolation region
Immediately after forming the source line by
30-40k of phosphorus (P) in the main surface of the semiconductor substrate to be
eV, (1-10) x 10¹³/ Cm ²Inject under the conditions
It This phosphorus injection improves the withstand voltage of the source line
However, the leak current can be suppressed.

In the above description, the flash memory is given as an example of the semiconductor device. However, from the viewpoint of reducing the mask alignment process and the photolithography process, and optimizing the drain region and the source region, a field effect transistor is selected. Is also applicable.

[0078]

As described above, according to the present invention, it is possible to obtain a semiconductor device having excellent write characteristics and erase characteristics.

Further, according to the present invention, the number of mask aligning steps and photolithography steps can be reduced.

Further, according to the present invention, the structure of the drain region and the structure of the source region can be optimized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a state before an electrode layer is formed.

FIG. 2 is a cross-sectional view showing a state after forming an electrode layer.

FIG. 3 is a sectional view showing a state after impurity implantation.

FIG. 4 is a cross-sectional view showing a state in which ion implantation is performed to eliminate the high-concentration p-type impurity layer.

FIG. 5 is a sectional view of a memory transistor obtained through the steps shown in FIGS.

FIG. 6 is a cross-sectional view of a memory transistor having a low-concentration p-type impurity layer immediately below a floating gate.

FIG. 7 is a cross-sectional view showing a state where impurities are implanted using the electrode layer as a mask.

FIG. 8 is a cross-sectional view showing a state where a field oxide film in an element isolation region is removed by etching.

FIG. 9 is a cross-sectional view showing a state where impurities are implanted into the main surface of a semiconductor substrate to be a source region.

FIG. 10 is a block diagram showing a general configuration of a conventional flash memory.

11 is an equivalent circuit diagram showing a schematic configuration of the memory cell matrix 100 shown in FIG.

FIG. 12 is a cross-sectional view showing the structure of a flash memory taken as an example of the related art.

FIG. 13 is a schematic plan view showing a conventional flash memory.

FIG. 14 is a cross-sectional view taken along the line WW in FIG.

FIG. 15 is a diagram showing a first step in a method for manufacturing a nonvolatile semiconductor memory according to a conventional technique.

FIG. 16 is a diagram showing a second step in the method for manufacturing a nonvolatile semiconductor memory in the conventional technique.

FIG. 17 is a diagram showing a third step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 18 is a schematic plan view showing the shape of a resist mask in the second step of the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 19 is a diagram showing a fourth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 20 is a diagram showing a fifth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 21 is a diagram showing a sixth step in the method for manufacturing a nonvolatile semiconductor memory in the prior art.

FIG. 22 is a diagram showing a seventh step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 23 is a diagram showing an eighth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 24 is a diagram showing a ninth step in the method for manufacturing a nonvolatile semiconductor memory in the conventional technique.

FIG. 25 is a diagram showing a tenth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 26 is a diagram showing an eleventh step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 27 is a diagram showing a twelfth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 28 is a diagram showing a thirteenth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 29 is a diagram showing a fourteenth step in the method for manufacturing a nonvolatile semiconductor memory in the prior art.

FIG. 30 is a diagram showing a fifteenth step in the method for manufacturing a nonvolatile semiconductor memory according to the conventional technique.

FIG. 31 is a plan layout view of a NOR flash memory.

FIG. 32 is a cross-sectional view of a memory transistor.

FIG. 33 is a cross-sectional view showing a state where impurities are implanted to form a drain region.

FIG. 34 is a cross-sectional view showing a state where impurities are implanted to form a source region.

FIG. 35 is a plan layout view of a DINOR type flash memory.

36 is a sectional view taken along line YY in FIG. 35.

FIG. 37 is a cross-sectional view showing a state after the field oxide film is removed.

38 is a sectional view taken along line ZZ in FIG. 35.

FIG. 39 is a cross-sectional view showing a state where impurities are implanted for forming source and drain regions.

[Explanation of symbols]

301 p-type semiconductor substrate 303 first polysilicon layer to serve as floating gate 305 second polysilicon layer to serve as control gate 306 metal silicide layer to serve as control gate 309 electrode layer 310 drain region 310a n-type impurity layer 310b p-type Impurity layer 311 Impurity region 311a n-type impurity layer 311b p-type impurity layer 313 Source region 313a n-type impurity layer 313b n-type low-concentration impurity layer 314 Low-concentration p-type impurity layer

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/115

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type having a main surface, an electrode layer formed on the main surface of the semiconductor substrate, in which a floating gate and a control gate are stacked, and a channel region below the electrode layer. And a source and drain region formed on the main surface of the semiconductor substrate at intervals to form a second conductivity type impurity layer and the second conductivity type impurity layer.
A first conductivity type impurity layer surrounding the conductivity type impurity layer, the source region being located below the second conductivity type impurity layer and below the second conductivity type impurity layer; A low-concentration second-conductivity-type low-concentration impurity layer and a first-conductivity-type low-concentration located between the channel region and the second-conductivity-type impurity layer and lower in concentration than the first-conductivity-type impurity layer in the drain region. A semiconductor device including an impurity layer. 2. A step of forming an electrode layer on a main surface of a semiconductor substrate with an insulating film interposed therebetween, and impurities are simultaneously implanted into the main surface of the semiconductor substrate to be a source and drain region using the electrode layer as a mask. A step of forming a pair of impurity regions; and a step of further implanting an impurity into the other impurity region to be the source region while covering one impurity region to be the drain region with a mask. For manufacturing a semiconductor device. 3. The impurity implantation for forming the pair of impurity regions is performed under conditions suitable for forming the drain region, and the impurity implantation for the other impurity region to be the source region is performed for the source region. Under conditions suitable for the formation of
The method for manufacturing a semiconductor device according to claim 2. 4. A main surface of a semiconductor substrate of the first conductivity type,
A step of forming an electrode layer in which a floating gate and a control gate are laminated, and a first conductivity type under conditions suitable for simultaneously forming a drain region on a main surface of a semiconductor substrate to be a source and drain region using the electrode layer as a mask By implanting impurities and impurities of the second conductivity type, a second conductivity type impurity layer,
A step of forming a pair of impurity regions including a first conductivity type impurity layer surrounding the impurity region; and a step of forming one of the impurity regions to be the drain region with a mask and the other of the impurity regions to be the source region. Implanting a second conductivity type impurity into the impurity region under a condition suitable for forming a source region, and further implanting a second conductivity type impurity under a condition suitable for offsetting the first conductivity type impurity layer; A method for manufacturing a semiconductor device, comprising: