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JPH07183165A - Thin-film capacitor - Google Patents

Thin-film capacitor

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Publication number
JPH07183165A
JPH07183165A JP32348593A JP32348593A JPH07183165A JP H07183165 A JPH07183165 A JP H07183165A JP 32348593 A JP32348593 A JP 32348593A JP 32348593 A JP32348593 A JP 32348593A JP H07183165 A JPH07183165 A JP H07183165A
Authority
JP
Japan
Prior art keywords
film
layer
dielectric layer
grain size
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32348593A
Other languages
Japanese (ja)
Inventor
Yumi Mizusawa
由美 水澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP32348593A priority Critical patent/JPH07183165A/en
Publication of JPH07183165A publication Critical patent/JPH07183165A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the leakage current density of a thin-film capacitor to a practical level while maintaining large capacitance by providing multiple inorganic polycrystalline dielectric layer of different average grain sizes between electrodes. CONSTITUTION:A thin-film capacitor comprises a lower electrode 2 formed on a substrate 1, a dielectric layer 3 on the lower electrode 2, and an upper electrode on the dielectric layer. The dielectric layer includes a first layer 4 of large average grain size and a second layer 5 of small average grain size. The layer 5 is preferably thinner than 1/10 of the total thickness of the layer 3. When the capacitor is constituted in such a way, the leakage current density the capacitor can be reduced to a practical level while the capacitance of the capacitor is maintained at a high level.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、DRAMのメモリセル
や移動体通信用MMIC等に用いられる薄膜キャパシタ
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor used in DRAM memory cells, mobile communication MMICs and the like.

【0002】[0002]

【従来の技術】電子デバイスの高性能化・大容量化に伴
い、SrTiO3 及び(BaSr)TiO3 等のペロブ
スカイト構造を有する複合酸化物薄膜は、従来のSiO
2 に比して2桁大きな誘電率を有する点から、DRAM
のメモリセルや移動体通信用MMIC等に用いられる薄
膜キャパシタへの応用が進められている。これらの薄膜
キャパシタに求められる特性は、大容量・低リーク電流
・高耐圧及び低誘電損失等が挙げられる。
2. Description of the Related Art With the increase in performance and capacity of electronic devices, complex oxide thin films having a perovskite structure such as SrTiO 3 and (BaSr) TiO 3 have been replaced by conventional SiO
From the viewpoint of having a two-digit large dielectric constant as compared with 2, DRAM
Are being applied to thin film capacitors used in memory cells and MMICs for mobile communication. The characteristics required for these thin film capacitors include large capacity, low leakage current, high breakdown voltage, low dielectric loss, and the like.

【0003】これらの薄膜キャパシタは、誘電体膜を誘
電体膜からなる電極で挟み込んだ構造をなしており、前
記特性に影響を及ぼす因子として上部または下部の電極
の膜材料・素子構造(各層の層厚・電極形状)に加え、
誘電体膜の膜質が重要であり、高比誘電率・低誘電損失
・低リーク電流密度等の特性が所望の温度領域で得られ
る、高品質な膜が求められている。
These thin film capacitors have a structure in which a dielectric film is sandwiched between electrodes made of a dielectric film. As factors that affect the characteristics, the film material and element structure of the upper or lower electrode (of each layer). Layer thickness and electrode shape)
The film quality of the dielectric film is important, and a high-quality film that can obtain characteristics such as high relative permittivity, low dielectric loss, and low leakage current density in a desired temperature range is required.

【0004】SrTiO3 等の複合酸化物薄膜の膜質と
前記特性との相関は未だ研究段階であり未解明な部分が
多いものの、得られている見解の一つに多結晶膜の結晶
粒径と比誘電率或いはリーク電流密度との相関がある。
すなわち、結晶粒径の小さい膜ほどリーク電流密度は小
さく、微結晶膜を得ることで膜のリーク電流密度を抑え
ることができる。しかしながら、リーク電流密度の減少
だけでなく、膜の比誘電率も結晶粒径の小さな膜ほど小
さくなってしまうという問題がある。この膜の比誘電率
とリーク電流密度とのトレードオフの関係は、結晶粒径
の他に膜組成等を変えた際にも認められており、膜特性
向上の点で大きな問題となってきている。
Although the correlation between the film quality of a complex oxide thin film such as SrTiO 3 and the above characteristics is still in the research stage and there are many unclear points, one of the obtained views is the crystal grain size of a polycrystalline film. There is a correlation with the relative dielectric constant or the leakage current density.
That is, the smaller the crystal grain size, the smaller the leak current density, and by obtaining the microcrystalline film, the leak current density of the film can be suppressed. However, there is a problem that not only the leakage current density decreases but also the relative dielectric constant of the film becomes smaller as the crystal grain size becomes smaller. The trade-off relationship between the relative permittivity of the film and the leakage current density has been confirmed when the film composition and the like are changed in addition to the crystal grain size, and this has become a major problem in improving the film characteristics. There is.

【0005】[0005]

【発明が解決しようとする課題】本発明は、上記事情を
考慮してなされたもので、大容量を保持しつつ、実用的
に満足し得る程度にリーク電流密度の低減化が図られた
薄膜キャパシタを提供しようとするものである。
SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and is a thin film in which the leakage current density is reduced to a practically satisfactory level while maintaining a large capacity. It is intended to provide a capacitor.

【0006】[0006]

【課題を解決するための手段】本発明に係わる薄膜キャ
パシタは、膜厚方向に平均結晶粒径の小さい層が存在す
る無機質多結晶誘電体層を有することを特徴とするもの
である。前記無機質多結晶誘電体としては、例えばSr
TiO3 、BaTiO3 、(BaSr)TiO3 、Pb
TiO3 、Pb(ZnTi)O3 、CaTiO3 などの
ペロブスカイト構造を有する複合酸化物、またはルチル
構造を有するTiO2 等を挙げることができる。
A thin film capacitor according to the present invention is characterized by having an inorganic polycrystalline dielectric layer having a layer having a small average crystal grain size in the film thickness direction. Examples of the inorganic polycrystal dielectric include Sr
TiO 3 , BaTiO 3 , (BaSr) TiO 3 , Pb
Examples thereof include complex oxides having a perovskite structure such as TiO 3 , Pb (ZnTi) O 3 , and CaTiO 3, and TiO 2 having a rutile structure.

【0007】前記無機質多結晶誘電体層における平均粒
径が大きい層は、その平均粒径が60nm以上であるこ
とが好ましい。前記平均結晶粒径の小さい層は、その平
均粒径が前記平均粒径が大きい層の1/2以下ににする
ことが好ましい。
The layer having a large average particle diameter in the inorganic polycrystalline dielectric layer preferably has an average particle diameter of 60 nm or more. The layer having a small average crystal grain size preferably has an average grain size of 1/2 or less of that of the layer having a large average grain size.

【0008】前記平均結晶粒径の小さい層は、その厚さ
が前記誘電体層自体の厚さの1/10以下にすることが
好ましい。前記無機質多結晶誘電体層の成膜方法は、特
に限定されず、蒸着・スパッタリング等の真空プロセス
の他、陽極酸化・ゾル・ゲル法等の湿式法を採用するこ
とができる。特に、前記無機質多結晶誘電体層の結晶粒
径を高精度で制御する上では真空プロセスが望ましい。
The thickness of the layer having a small average crystal grain size is preferably 1/10 or less of the thickness of the dielectric layer itself. The method for forming the inorganic polycrystalline dielectric layer is not particularly limited, and a vacuum method such as vapor deposition or sputtering, or a wet method such as anodic oxidation, a sol-gel method, or the like can be employed. In particular, a vacuum process is desirable for controlling the crystal grain size of the inorganic polycrystalline dielectric layer with high accuracy.

【0009】前記無機質誘電体層の結晶粒径の制御方法
としては、幾つか挙げることができる。例えばRFスパ
ッタ法で成膜する場合には、成膜速度が小さいほど、ま
た成膜時の基板温度が高いほど結晶粒径の大きな誘電体
層が得られるため、投入パワー・ガス圧等の成膜条件を
変化させて成膜中の成膜速度を経時的変化させる、或い
は基板温度を成膜中に経時的変化させることにより、平
均粒径の小さい層が存在する誘電体層を形成できる。こ
の方法では、膜厚方向に結晶粒径の勾配を有する誘電体
層を形成することが可能である。
There are several methods for controlling the crystal grain size of the inorganic dielectric layer. For example, in the case of forming a film by the RF sputtering method, a dielectric layer having a larger crystal grain size can be obtained as the film forming speed becomes lower and the substrate temperature during film forming becomes higher. By changing the film conditions to change the film formation rate during film formation with time, or by changing the substrate temperature with time during film formation, it is possible to form a dielectric layer having a layer with a small average grain size. With this method, it is possible to form a dielectric layer having a gradient of crystal grain size in the film thickness direction.

【0010】[0010]

【作用】本発明に係わる薄膜キャパシタによれば、電極
間に挟まれた無機質多結晶誘電体層の膜厚方向に平均結
晶粒径の小さい層を存在させることによって大容量を保
持しつつ、実用的に満足し得る程度にリーク電流密度の
低減化を図ることができる。
According to the thin film capacitor of the present invention, a layer having a small average crystal grain size is provided in the film thickness direction of the inorganic polycrystalline dielectric layer sandwiched between the electrodes, thereby maintaining a large capacity and practical use. It is possible to reduce the leakage current density to the extent that it is satisfactory.

【0011】すなわち、無機質多結晶誘電体層の膜厚方
向に平均結晶粒径の小さい層を存在させることにより、
同一誘電体層中に平均結晶粒径の大きな層、即ち比誘電
率及びリーク電流密度の大きな層(以下、これを第1層
と記す)と、平均結晶粒径の小さな層、即ち比誘電率及
びリーク電流密度の小さな層(以下、これを第2層と記
す)とを混在させることができる。その結果、前記第1
層による比誘電率の向上と前記第2層によるリーク電流
密度の低減化が図られ、誘電体層全体として前記特性を
満たす薄膜キャパシタを得ることができる。
That is, by providing a layer having a small average crystal grain size in the thickness direction of the inorganic polycrystalline dielectric layer,
A layer having a large average crystal grain size in the same dielectric layer, that is, a layer having a large relative permittivity and a leakage current density (hereinafter referred to as the first layer), and a layer having a small average crystal grain size, that is, a relative permittivity. And a layer having a small leak current density (hereinafter, referred to as a second layer) can be mixed. As a result, the first
The relative permittivity is improved by the layer and the leakage current density is reduced by the second layer, and a thin film capacitor satisfying the above characteristics can be obtained as the entire dielectric layer.

【0012】具体的な薄膜キャパシタを図1を参照して
説明する。基板1上には下部電極2が配置されている。
誘電体層3は、前記下部電極2上に配置され、前記下部
電極2側から配置される前述した平均結晶粒径の大きな
層である第1層4および前述した平均結晶粒径の小さな
層である記第2層5から形成されている。上部電極6
は、前記誘電体層3上に配置されている。
A specific thin film capacitor will be described with reference to FIG. The lower electrode 2 is arranged on the substrate 1.
The dielectric layer 3 is disposed on the lower electrode 2 and includes the first layer 4 which is a layer having a large average crystal grain size and which is disposed from the lower electrode 2 side and the layer having a small average crystal grain size described above. It is formed from a certain second layer 5. Upper electrode 6
Are arranged on the dielectric layer 3.

【0013】このような構成の薄膜キャパシタにおい
て、第1層の膜厚、比誘電率及びリーク電流密度をそれ
ぞれd1 ,εr1,J1 、同様に第2層の膜厚、比誘電率
及びリーク電流密度をそれぞれd2 ,εr2,J2 、誘電
体層全体の膜厚、・比誘電率及びリーク電流密度をd,
εr ,Jとすると、前記誘電体層の容量は第1層と第2
層の直列であると考えられるから次式(1)により求め
られる。、 1/C=1/C1 +1/C2 …(1) ここで、C1 ,C2 ,Cはそれぞれ第1層,第2層及び
誘電体層全体の容量である。
In the thin film capacitor having such a structure, the film thickness, relative permittivity and leakage current density of the first layer are respectively d 1 , ε r1 and J 1 , as well as the film thickness, relative permittivity and the dielectric constant of the second layer. Leakage current densities are d 2 , ε r2 and J 2 , respectively, the thickness of the entire dielectric layer, relative permittivity and leak current density are d,
If ε r , J, the capacitance of the dielectric layer is equal to that of the first layer and the second layer.
Since it is considered that the layers are in series, it is obtained by the following equation (1). , 1 / C = 1 / C 1 + 1 / C 2 (1) Here, C 1 , C 2 , and C are the capacitances of the first layer, the second layer, and the entire dielectric layer, respectively.

【0014】前記式(1)の関係を用いて、前記誘電体
層全体の比誘電率は次式(2)により求められる。 εr =dεr1εr2/(εr12 +εrd1) …(2) 従って、第2層を十分に薄くする、例えば第1層の1/
10の厚さにするとεr はεr1にほぼ近似した値にな
る。一方、前記誘電体層全体のリーク電流密度Jは、前
記第2層がバリア層として働くため、JはJ2 にほぼ近
似した値になる。このようなことから、既述したように
前記第1層による比誘電率の向上と前記第2層によるリ
ーク電流密度の低減化が図られ、大容量で低リーク電流
密度の薄膜キャパシタを実現できる。
Using the relation of the equation (1), the relative permittivity of the entire dielectric layer is obtained by the following equation (2). ε r = d ε r1 ε r2 / (ε r1 d 2 + ε r 2 d1 ) (2) Therefore, the second layer is made sufficiently thin, for example, 1 / th of the first layer.
With a thickness of 10, ε r has a value approximately close to ε r1 . On the other hand, the leakage current density J of the entire dielectric layer is a value approximately J to J 2 because the second layer acts as a barrier layer. As described above, the dielectric constant of the first layer is improved and the leakage current density of the second layer is reduced as described above, and a thin film capacitor having a large capacity and a low leakage current density can be realized. .

【0015】[0015]

【実施例】以下、本発明の実施例を詳細に説明する。 (実施例1)Al23 基板上に、下部電極として厚さ
50nmのPt膜をRFマグネトロンスパッタ法により
室温成膜した後、RFマグネトロンスパッタ法により、
SrTiO3 をAr/O2 5mTorr、RF入力パワー4
00Wで成膜した。その際、基板温度を180分の成膜
時間中170分間では400℃、残り10分は250℃
とした。
EXAMPLES Examples of the present invention will be described in detail below. Example 1 A Pt film having a thickness of 50 nm was formed as a lower electrode on an Al 2 O 3 substrate at room temperature by the RF magnetron sputtering method, and then by the RF magnetron sputtering method.
SrTiO 3 Ar / O 2 5 mTorr, RF input power 4
The film was formed at 00W. At that time, the substrate temperature was 400 ° C. for 170 minutes during the film formation time of 180 minutes, and 250 ° C. for the remaining 10 minutes.
And

【0016】こうして成膜したSrTiO3 膜の膜厚を
α−step profeler で測定したところ約200nmであ
り、X線回折及び電子線回折による分析より、SrTi
3膜全体は(111)配向の多結晶になっていること
が分かった。さらに、膜の断面をFE−SEMで観察し
た結果、下部電極側190nm厚の領域の結晶粒径が7
0nm前後、上部電極側10nm厚の領域の結晶粒径が
30nm前後となっていた。
The film thickness of the SrTiO 3 film thus formed was about 200 nm as measured by α-step profiler, and the SrTi 3 film was analyzed by X-ray diffraction and electron diffraction.
It was found that the entire O 3 film was a (111) -oriented polycrystal. Furthermore, as a result of observing the cross section of the film by FE-SEM, the crystal grain size in the 190 nm thick region on the lower electrode side was 7
The crystal grain size in the region of 0 nm and the thickness of 10 nm on the upper electrode side was around 30 nm.

【0017】次いで、前記SrTiO3 膜上に、上部電
極として厚さ100nmのNiをRFマグネトロンスパ
ッタ法により350℃で成膜し、PEP工程によるレジ
ストパターンの形成及び前記レジストパターンをマスク
としたNi膜のエッチングにより100μm×100μ
mの上部電極パターンを形成した。
Then, a 100 nm thick Ni film was formed as an upper electrode on the SrTiO 3 film by an RF magnetron sputtering method at 350 ° C., a resist pattern was formed by a PEP process, and the Ni film was masked with the resist pattern. 100μm × 100μ by etching
m upper electrode pattern was formed.

【0018】得られたキャパシタの特性評価を四端子法
により行ったところ、測定周波数100kHzにおいて
容量約88.5nF、誘電正接tanδ=0.01であ
り、これは比誘電率εr に換算して約200であり、4
00℃で成膜したSrTiO3 膜とほぼ同等な値であっ
た。また、I−V特性を測定したところ、リーク電流密
度JはDC電圧VDCが±10V以内の領域で10-8A/
cm2 以下の値を示し、250℃で成膜したSrTiO
3 膜とほぼ同等な値であった。
When the characteristics of the obtained capacitor were evaluated by the four-terminal method, the capacitance was about 88.5 nF and the dielectric loss tangent tan δ = 0.01 at the measurement frequency of 100 kHz, which was converted into the relative permittivity ε r. About 200 and 4
The value was almost the same as that of the SrTiO 3 film formed at 00 ° C. Moreover, when the IV characteristics were measured, the leakage current density J was 10 −8 A / in the region where the DC voltage V DC was within ± 10V.
cm 2 or less, SrTiO formed at 250 ° C.
The value was almost the same as that of the three films.

【0019】(実施例2)AlN基板上に、下部電極と
して厚さ50nmのPt膜をRFマグネトロンスパッタ
法により室温成膜した後、SrTiO3 をO2 雰囲気中
(5mTorr)、基板温度400℃でRFマグネトロンス
パッタ成膜した。その際、RF投入パワーを400分の
成膜時間中380分までは400W、残り20分は60
0Wとした。
(Example 2) A Pt film having a thickness of 50 nm was formed as a lower electrode on an AlN substrate at room temperature by an RF magnetron sputtering method, and then SrTiO 3 was placed in an O 2 atmosphere (5 mTorr) at a substrate temperature of 400 ° C. An RF magnetron sputter film was formed. At that time, the RF input power was 400 W during the film formation time of 400 minutes up to 380 minutes, and the remaining 20 minutes was 60 W.
It was set to 0W.

【0020】こうして成膜したSrTiO3膜全体は、
膜厚205nmの(111)配向多結晶膜になってお
り、膜の断面FE−SEM観察より下部電極側190n
m厚の領域が結晶粒径70nm前後、上部電極側15n
m厚の領域が結晶粒径30nm前後となっていた。
The entire SrTiO3 film thus formed is
The film is a (111) oriented polycrystalline film having a film thickness of 205 nm, and 190 n of the lower electrode side from the cross section FE-SEM observation of the film.
The region of m thickness has a crystal grain size of around 70 nm and the upper electrode side is 15 n
The region of m thickness had a crystal grain size of about 30 nm.

【0021】次いで、前記SrTiO3 膜上に、上部電
極としてNi100nmをRFマグネトロンスパッタ法
により350℃で成膜し、PEP工程によるレジストパ
ターンの形成及び前記レジストパターンをマスクとした
Ni膜のエッチングにより100μm×100μmの上
部電極パターンを形成した。
Next, on the SrTiO 3 film, a 100 nm Ni film was formed as an upper electrode by RF magnetron sputtering at 350 ° C., a resist pattern was formed by a PEP process, and the Ni film was etched using the resist pattern as a mask to a thickness of 100 μm. An upper electrode pattern of × 100 μm was formed.

【0022】得られたキャパシタは、測定周波数100
kHzにおいて容量約86.5nF、誘電正接tanδ
=0.01であり、これは比誘電率εr に換算して約2
00であり、400Wで成膜したSrTiO3 膜(成膜
速度0.5nm/min)とほぼ同等な値であった。ま
た、I−V特性を測定したところ、リーク電流密度Jは
DC電圧VDCが±10V以内の領域で10-8A/cm2
以下の値を示し、600Wで成膜したSrTiO3
(成膜速度0.75nm/min)とほぼ同等な値であ
った。
The obtained capacitor has a measurement frequency of 100.
Capacitance: about 86.5nF, dielectric loss tangent tan δ at kHz
= 0.01, which is about 2 in terms of relative permittivity ε r
The value was 00, which was almost the same as that of the SrTiO 3 film formed at 400 W (film formation rate 0.5 nm / min). Also, when the IV characteristic was measured, the leakage current density J was 10 −8 A / cm 2 in the region where the DC voltage V DC was within ± 10 V.
The following values were shown, which were almost the same as those of the SrTiO 3 film formed at 600 W (film formation rate 0.75 nm / min).

【0023】(実施例3)まず、MgO(100)単結
晶上にPtを400℃にてRFマグネトロンスパッタ法
により成膜し、厚さ50nmのPt(100)単結晶膜
を形成した。その上にRFマグネトロンスパッタ法によ
り、SrTiO3 をAr/O2 5mTorr、RF入力パワ
ー400Wで成膜した。その際、基板温度を180分の
成膜時間中175分までは400℃、残り5分は250
℃とした。
Example 3 First, Pt was deposited on a MgO (100) single crystal at 400 ° C. by an RF magnetron sputtering method to form a 50 nm thick Pt (100) single crystal film. A SrTiO 3 film was formed thereon by RF magnetron sputtering with Ar / O 2 5 mTorr and RF input power of 400 W. At that time, the substrate temperature was 400 ° C. for 175 minutes during the film formation time of 180 minutes, and 250 for the remaining 5 minutes.
℃ was made.

【0024】こうして得られたSrTiO3 膜は、膜厚
約190nmであり、膜断面のFE−SEM観察の結
果、下部電極側175nm厚の領域は単結晶膜、上部電
極側15nm厚の領域は粒径30nm前後の多結晶膜に
なっていることが分かった。さらに、X線回折パターン
より、SrTi03 膜は単結晶部分・多結晶部分共に
(100)配向であった。
The SrTiO 3 film thus obtained had a film thickness of about 190 nm. As a result of FE-SEM observation of the film cross section, the 175 nm thick region on the lower electrode side was a single crystal film, and the 15 nm thick region on the upper electrode side was a grain. It was found that the film was a polycrystalline film with a diameter of around 30 nm. Further, from the X-ray diffraction pattern, the SrTiO 3 film was (100) oriented in both the single crystal portion and the polycrystalline portion.

【0025】次いで、前記SrTiO3 膜上に上部電極
として厚さ100nmのNiをRFマグネトロンスパッ
タ法により350℃で成膜し、PEP工程によるレジス
トパターンの形成及び前記レジストパターンをマスクと
したNi膜のエッチングにより100μm×100μm
の上部電極パターンを形成した。
Next, a 100 nm-thick Ni film was formed as an upper electrode on the SrTiO 3 film by an RF magnetron sputtering method at 350 ° C., a resist pattern was formed by a PEP process, and the Ni film was formed using the resist pattern as a mask. 100μm × 100μm by etching
The upper electrode pattern of was formed.

【0026】得られたキャパシタの特性評価を四端子法
により行ったところ、測定周波数100kHzにおいて
容量約140nF、誘電損失tanδ=0.008であ
り、これは比誘電率εr に換算して約300であり、S
rTiO3 単結晶膜とほぼ同等な値であった。また、I
−V特性を測定したところ、リーク電流密度Jは−10
V≦VDC≦−10Vで10-8A/cm2 以下の値を示
し、SrTiO3 多結晶膜とほぼ同等な値であった。
When the characteristics of the obtained capacitor were evaluated by the four-terminal method, the capacitance was about 140 nF and the dielectric loss tan δ = 0.008 at a measurement frequency of 100 kHz, which was about 300 in terms of the relative permittivity ε r. And S
The value was almost the same as that of the rTiO 3 single crystal film. Also, I
When the −V characteristic was measured, the leakage current density J was −10.
When V ≦ V DC ≦ −10 V, the value was 10 −8 A / cm 2 or less, which was almost the same as that of the SrTiO 3 polycrystalline film.

【0027】(実施例4)熱酸化膜付きSi基板上に下
部電極として厚さ50nmのPt膜を成膜した後、Sr
TiO3 をO2 雰囲気中(5mTorr)、基板温度400
℃でRFマグネトロンスパッタ成膜した。その際、基板
温度を400分の成膜時間中360分までは400℃、
残り40分間で200℃まで徐冷した。
Example 4 A Pt film having a thickness of 50 nm was formed as a lower electrode on a Si substrate with a thermal oxide film, and then Sr was formed.
TiO 3 in O 2 atmosphere (5 mTorr), substrate temperature 400
An RF magnetron sputter film was formed at ° C. At that time, the substrate temperature was 400 ° C. during the film formation time of 400 minutes until 360 minutes,
It was gradually cooled to 200 ° C. in the remaining 40 minutes.

【0028】こうして得られたSrTiO3 膜全体は、
膜厚200nmの(111)配向多結晶膜になってお
り、下部電極から膜厚方向180nmまでは結晶粒径7
0nmの一様な領域で、それより上部電極側では結晶が
膜厚方向に徐々に微細になり上部電極との界面では粒径
25nmとなっていた。
The entire SrTiO 3 film thus obtained is
It is a (111) oriented polycrystalline film with a film thickness of 200 nm, and the crystal grain size is 7 from the lower electrode to the film thickness direction of 180 nm.
In the uniform region of 0 nm, the crystal gradually became finer in the film thickness direction on the side of the upper electrode, and the grain size was 25 nm at the interface with the upper electrode.

【0029】次いで、前記SrTiO3 膜上に上部電極
として厚さ100nmのNiをRFマグネトロンスパッ
タ法により350℃で成膜し、PEP工程によるレジス
トパターンの形成及び前記レジストパターンをマスクと
したNi膜のエッチングにより100μm×100μm
の上部電極パターンを形成した。
Next, a 100 nm-thick Ni film was formed as an upper electrode on the SrTiO 3 film by an RF magnetron sputtering method at 350 ° C., a resist pattern was formed by a PEP process, and the Ni film was formed using the resist pattern as a mask. 100μm × 100μm by etching
The upper electrode pattern of was formed.

【0030】得られたキャパシタは、測定周波数100
kHzにおいて容量約97.8nF(換算比誘電率εr
〜210)、誘電正接tanδ=0.009、リーク電
流密度J<10-8A/cm2 (−10V≦VDC≦−10
V)と良好な特性を示した。
The obtained capacitor has a measurement frequency of 100.
Capacity of about 97.8 nF (converted relative permittivity ε r
˜210), dielectric loss tangent tan δ = 0.09, leakage current density J <10 −8 A / cm 2 (−10V ≦ V DC ≦ −10).
V) and good characteristics were exhibited.

【0031】[0031]

【発明の効果】以上詳述したように本発明によれば、誘
電体層の比誘電率を低下させることなく、リーク電流密
度を低減させることができ、大容量・高性能の薄膜キャ
パシタを提供することができる。
As described above in detail, according to the present invention, it is possible to reduce the leak current density without lowering the relative permittivity of the dielectric layer, and to provide a large capacity and high performance thin film capacitor. can do.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係わる薄膜キャパシタの断
面図。
FIG. 1 is a sectional view of a thin film capacitor according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…基板、2…下部電極、3…誘電体層、4…第1層、
5…第2層、6…上部電極。
1 ... Substrate, 2 ... Lower electrode, 3 ... Dielectric layer, 4 ... First layer,
5 ... second layer, 6 ... upper electrode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電極間に挟まれた誘電体層中に、前記電
極間の膜厚方向に平均結晶粒径の小さい層が存在する無
機質多結晶誘電体層を有することを特徴とする薄膜キャ
パシタ。
1. A thin film capacitor comprising an inorganic polycrystalline dielectric layer in which a layer having a small average crystal grain size exists in a film thickness direction between the electrodes in a dielectric layer sandwiched between the electrodes. .
JP32348593A 1993-12-22 1993-12-22 Thin-film capacitor Pending JPH07183165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32348593A JPH07183165A (en) 1993-12-22 1993-12-22 Thin-film capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32348593A JPH07183165A (en) 1993-12-22 1993-12-22 Thin-film capacitor

Publications (1)

Publication Number Publication Date
JPH07183165A true JPH07183165A (en) 1995-07-21

Family

ID=18155222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32348593A Pending JPH07183165A (en) 1993-12-22 1993-12-22 Thin-film capacitor

Country Status (1)

Country Link
JP (1) JPH07183165A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016662A (en) * 2006-07-06 2008-01-24 Fujitsu Ltd Capacitor structure and manufacturing method thereof
US20150211942A1 (en) * 2012-10-19 2015-07-30 Okazaki Manufacturing Company Cryogenic temperature measuring resistor element
JP2017183320A (en) * 2016-03-28 2017-10-05 Tdk株式会社 Dielectric thin film element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016662A (en) * 2006-07-06 2008-01-24 Fujitsu Ltd Capacitor structure and manufacturing method thereof
US20150211942A1 (en) * 2012-10-19 2015-07-30 Okazaki Manufacturing Company Cryogenic temperature measuring resistor element
US9464947B2 (en) * 2012-10-19 2016-10-11 Okazaki Manufacturing Company Cryogenic temperature measuring resistor element
JP2017183320A (en) * 2016-03-28 2017-10-05 Tdk株式会社 Dielectric thin film element

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