JPH07182853A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a pattern area of a register part in a semiconductor integrated circuit device for holding image data. CONSTITUTION:A memory cell array is constituted so that respective DRAM memory cells constituted of MOS transistors are connected to respective intersected positions of plural word lines WL and plural bit line pairs BL, BL/intersecting with the word lines. The write data or read out data for the memory cell array are held temporarily in the DRAM memory cell in the register part 70. The DRAM memory cell in the register part 70 is constituted of all NMOSs 71-74 of the same channel type, and the data held by the DRAM memory cell in the register part 70 are re-written in the DRAM memory cell by receiving a refresh signal from a refresh counter 23. Since all NMOSs 71-74 are the same channel type, for instance, element separation, etc., is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a video memory used for video signal processing.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional semiconductor integrated circuit device. The semiconductor integrated circuit device of FIG. 2 is a video memory that stores image data, and includes, for example, the data bus DT1 and its data bus DT.
1 stores image data from the data bus DT1 / for complementary data transmission. The semiconductor integrated circuit device further stores the stored image data in the data bus DT.
2 and the data bus DT2 output from the data bus DT2 / for complementary data transmission, and also the data bus DT
3 and the data bus DT3 are also configured to output to the outside from the data bus DT3 / which transmits complementary data. This semiconductor integrated circuit device has a data bus DT1,
Register unit 1 for temporarily holding data from DT1 /
0, the DRAM unit 20 in which the data held in the register unit 10 is written, the register unit 30 that reads out the data stored in the DRAM unit 20 and temporarily holds the data, and the register unit 30. Similarly, the DRAM section 20
And a register section 40 for reading out the data stored in and temporarily holding it. The register unit 10 is D
The register is a register that holds write data for the RAM section 20, and has a plurality of bit line pairs including a bit line BL and a bit line BL / that transmits a complementary signal to the bit line BL. A static memory cell 11 is connected to each bit line pair. DRA
The M section 20 includes a dynamic memory cell (hereinafter referred to as a DRAM memory cell) 21 and 22 formed of MOS transistors at each intersection of a plurality of word lines WL and a plurality of bit line pairs BL and BL / intersecting with the word lines WL. , Are connected to each other and have a memory cell array arranged in a matrix. The register units 30 and 40 are the DRA
This is a register that holds read data for the M section 20, and, like the register section 10, includes a plurality of bit line pairs including a bit line BL and a bit line BL / that transmits a complementary signal to the bit line BL. I have each. A static memory cell 3 is provided for each bit line pair.
1, 41 are connected respectively.

Data buses DT1, DT1 / to DT3, D
T3 /, each register unit 10, 30, 40, and DRAM
Between the sections 20, the first transfer gates for controlling data input / output to the DRAM section 20 or the data buses DT1 and D
It is connected by a second transfer gate which controls data input / output to / from T1 / to DT3 and DT3 /. Data bus D
Between T1 and DT1 / and the register unit 10, a plurality of second
Of the MOS transistors 51 and 52 which are simultaneously opened and closed based on the bit line pair selection signal. When the MOS transistors 51 and 52 are turned on, the data buses DT1 and DT1 / are connected to the bit line pairs BL and BL / in the register unit 10. MOS transistors 53 and 54 are provided between the register unit 10 and the DRAM unit 20.
A plurality of first transfer gates configured by are provided corresponding to the memory cell array. These MOS transistors 53 and 54 open and close based on the control signal, and the plurality of bit line pairs of the register unit 10 are connected to the respective bit line pairs BL and BL / of the memory cell array in the DRAM unit 20. A plurality of first transfer gates composed of MOS transistors 55 and 56 are provided between the DRAM unit 20 and the register unit 30, and these two MOS transistors 55 and 56 simultaneously open and close based on a control signal. To do. Accordingly, the plurality of bit line pairs BL and BL / of the register unit 30 are connected to the respective bit line pairs BL and BL / of the memory cell array in the DRAM unit 20.
Between the data buses DT2, DT2 / and the register unit 30, a plurality of second lines that are opened and closed based on the bit line pair selection signal.
Transfer gates are provided. Each second transfer gate is composed of MOS transistors 57 and 58, and these MOS transistors 57 and 58 are connected to the data bus DT.
2, DT2 / and the bit line pair BL, B in the register unit 30
It is configured to control conduction between L /. The register unit 40 has the same configuration as the register unit 30, and each bit line pair of the register unit 30 has a MOS transistor 5
It is connected to the register unit 30 via a plurality of first transfer gates composed of 9, 60. Data bus DT
A plurality of second transfer gates that are opened and closed based on the bit line pair selection signal are provided between 3, DT3 / and the register section 40. Each of the second transfer gates is composed of MOS transistors 61 and 62, and these MOS transistors 61 and 62 conduct between the data buses DT3 and DT3 / and the bit line pair BL and BL / in the register section 40, respectively. It is configured to control.

FIG. 3 is a circuit diagram showing the DRAM section and the register section in FIG. 2, and a part of the DRAM section 20 and the register section 30 are shown as an example. The DRAM section 20 includes a plurality of MOS transistors 21a, 22a ... Which are turned on and off based on the potential of each word line WL, and their respective MOs.
Has a plurality of capacitors 21b, 22b ... Which are respectively connected to the bit line BL or BL / when the S transistors 21a, 22a. Capacitor 21
b, 22b ... Are composed of, for example, MOS transistors, and their respective capacitors 21b, 22b ... Accumulate charges and hold data. A refresh counter 23 is connected to the DRAM section 20, and the refresh counter 23 sends a refresh signal to the DRAM section 20 via the word line WL. The register unit 30 includes four MOS transistors 31a, 31b, 31c, 31d.
And MOS transistors 31a and 31b and M
The OS transistors 31c and 31d are CM
It is formed of an OS transistor. A flip-flop is formed by the four MOS transistors 31a, 31b, 31c and 31d, and the flip-flop is connected between the bit lines BL and BL / and holds data.
The register units 10 and 40 shown in FIG.
The flip-flops have the same configuration as the above, and these flip-flops hold data.

Next, the operation of the semiconductor integrated circuit device of FIG. 2 will be described. Bit line pair selection signals are sequentially sent to the plurality of second transfer gates connected to the data buses DT1 and DT1 /, and the MOS transistors 51 and 52 in each of the transfer gates are sequentially turned on. As a result, serial data from the information source is sequentially transferred to each memory cell of the register unit 10 and converted into parallel data. After that, for example, the control signal is transmitted to the MOS transistors 53 and 54 in the plurality of transfer gates all at once,
Each transfer gate is turned on at the same time. As a result, the plurality of data held in the respective memory cells in the register section 10 are simultaneously written in the DRAM section 20. Further, the refresh signal is sequentially transmitted from the refresh counter 23 through the plurality of word lines WL, and each DRAM memory cell in the DRAM section 20 is refreshed. Therefore, the data written in the DRAM section 20 is retained. When reading data, for example, the control signal is transmitted to the MOS transistors 55 and 56 of the plurality of first transfer gates all at once, and the respective first transfer gates are simultaneously turned on. Therefore, one column of data stored in the memory cell array in the DRAM section 20 is transferred to the register section 30 all at once. The register unit 30 temporarily holds the data transferred from the DRAM unit 20. Next, the bit line pair selection signal is output to the MOS transistors 57, 57 of the plurality of second transfer gates for output.
It is sequentially supplied to 58, and the plurality of second transfer gates are sequentially turned on. As a result, the parallel data held in the register unit 30 is sequentially transferred to the data buses DT2, D.
It is converted to serial data via T2 / and read. On the other hand, the register unit 40 is used as an auxiliary of the register unit 30, holds the data held in the register unit, and in the same manner as the register 30, the data buses DT3 and DT.
The read data is output via 3 /. That is, for example,
When data is being transferred from the DRAM section 20 to the register section 30, the register section 40 operates on the data bus DT.
3, read data is output via DT3 /.

[0006]

However, the conventional semiconductor integrated circuit device has the following problems. The register units 10, 30, 40 are PMOS and NM
A static memory composed of the complementary OS is used. Therefore, PMOS and NMOS
Due to the element isolation, etc., the pattern area of the semiconductor integrated circuit has been increased. The present invention provides a semiconductor integrated circuit device which solves the problem of increasing the pattern area, which is a problem of the conventional technique.

[0007]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a DRAM memory comprising MOS transistors at each intersection of a plurality of word lines and a plurality of bit line pairs intersecting the word lines. A memory cell array in which cells are connected to each other and arranged in a matrix, a plurality of first transfer gates that are respectively connected to each of the bit line pairs and that are turned on and off based on a control signal, and each of the first transfer Between each of the registers and the data bus, a plurality of registers for serial data / parallel data mutual conversion, which are respectively connected to the bit line pair through a gate and hold write data or read data for the memory cell, respectively. A plurality of second transfer gates connected to each other and turned on and off by a bit line selection signal, Outputs a shoe signal selecting the plurality of word lines sequentially, and a refresh circuit for performing the re-writing to the memory cell, the semiconductor integrated circuit device having, takes the following means. That is, each of the registers is configured by using the same circuit as the memory cell and is rewritten by the refresh signal. A second aspect of the present invention is characterized in that each of the registers in the first aspect of the invention includes first and second MOS transistors for holding data, which are connected between two bit lines forming a bit line pair, and the refresh transistor. On with signal,
The first and second MOSs are turned off and are turned on.
Rewriting third and fourth MOS transistors for setting the transistors to a constant potential, wherein the first, second, third and fourth MOS transistors are formed of the same channel type MOS transistor. There is.

[0008]

According to the first aspect of the invention, since the semiconductor integrated circuit device is configured as described above, each register becomes a DRAM memory cell, and these DRAM memory cells are based on a fresh signal like the memory cell array. Data is rewritten. According to the second invention, each register includes the first, second, third and fourth MOS transistors, and the first, second, third and fourth MOS transistors are of the same channel type. It is composed of MOS transistors. Therefore, it is possible to omit the element isolation of the MOS transistor required in each register.
Therefore, the conventional problems can be solved.

[0009]

1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. The device shown in FIG. 1 is a partial circuit of a video memory for storing image data, like the conventional devices shown in FIGS. 2 and 3, and elements common to those in FIGS. Has been done. The semiconductor integrated circuit device of FIG. 1 has a DRAM memory cell composed of MOS transistors at each intersection of a plurality of word lines WL and a plurality of bit line pairs BL, BL / which intersects the word lines WL, as in the conventional FIG. Have memory cell arrays connected in a matrix. The memory cell array holds image data input from the data buses DT and DT / which transmit complementary data. A register unit 70 for temporarily holding write data or read data is provided between the memory cell array and the data buses DT and DT /. Further, a plurality of first transfer gates that are opened / closed by a control signal are provided between the register unit 70 and the memory cell array, and are opened / closed between the register unit 70 and the data buses DT and DT / based on a bit line pair selection signal. A plurality of second transfer gates are provided.

Each DRAM memory cell in the memory cell array is turned on, based on the potential of each word line WL.
MOS transistors 21a, 22a, ...
, And capacitors 21b, 22b, ... Connected to the bit line BL or BL / when the MOS transistors 21a, 22a ,. Each of the capacitors 21b, 22b, ... Is composed of, for example, a MOS transistor. Also,
This semiconductor integrated circuit device includes a refresh counter 23 that sequentially supplies a refresh signal to the memory cell array via a word line WL, and a refresh controller 24 that controls the refresh counter 23.
I have it. The semiconductor integrated circuit device of FIG. 1 is a device different from that of FIG. 2 and FIG. 3, and the register unit 70 has a plurality of DRAM memory cells like the memory cell array, and these DRAM memory cells are each of the memory cell array. It is provided corresponding to the bit line pair. Each DRAM memory cell in the register unit 70 is composed of four N-channel type MOS.
Transistors (hereinafter referred to as NMOS) 71, 72, 7
3 and 74, the first and second M for holding data
The NMOS transistors 72 and 74, which are OS transistors, are connected to each other between two bit lines BL and BL / which form a bit line pair. Also, the refresh counter 23 is connected to the NMOS 71 and 73 which are the third and fourth rewriting MOS transistors for rewriting which are turned on and off by the refresh signal and set the NMOS 72 and 74 to a constant potential when in the on state. There is. That is, the sources of the NMOSs 71 and 73 are connected to the power supply potential Vdd, and
The gate is connected to the refresh counter 23.
The gate of the NMOS 74 is connected to the drain of the NMOS 71, and the gate of the NMOS 72 is connected to the drain of the NMOS 73. The sources of the NMOSs 72 and 74 are connected to the ground potential GND, respectively. NMO
The drains of S71 and 72 are connected to the bit line BL, and the drains of the NMOSs 73 and 74 are connected to the bit line BL.
/It is connected to the. On the other hand, each first transfer gate has N
This NMO is composed of MOS transistors 55 and 56.
S transistors 55 and 56 are connected to each bit line pair. Each second transfer gate has an NMOS 5
7, 58 connected to each bit line pair.

Next, the operation of the semiconductor integrated circuit device of FIG. 1 will be described. When one of the plurality of word lines WL is set to “H”, a memory cell including, for example, the NMOS 21a and the capacitor 21b is selected. If "H" level is stored in the selected memory cell, the bit line BL connected to it becomes "H", and the bit line BL is "H" and the bit line BL / is "H" by a sense amplifier (not shown). L ″ is confirmed. next,
The first gate is turned on by the control signal, and the data is transferred and held in the DRAM memory cell in the register unit 70. Further, the bit line pair selection signal "H" is set based on the address, and the second gate MOS transistors 57 and 58 are turned on. As a result, the data held in the memory cell in the register unit 70 is transferred to the data lines DT and DT /, and the read operation is completed.
Since each memory cell in the memory cell array and the register section 70 is a DRAM memory cell, it needs to be refreshed to retain data. FIG. 4 is a diagram showing the discharge characteristic of the DRAM memory cell, and FIG. 5 is a diagram showing the charge characteristic of the DRAM memory cell. The DRAM memory cell releases the electric charge stored in the capacitor over time. That is, as shown in FIG.
The potential that was at the "H" level decreases with time and becomes lower than the "H" definite potential V _T. In a normal refresh operation, the refresh controller 24 controls the refresh counter 23,
Changes the word line WL to "H" sequentially. When the word line WL is sequentially set to “H”, the NMOSs 21a, 22
.. are turned on, and the bit lines BL, BL / and the capacitors 21b, 22b ,. FIG. 5 shows that each capacitor 21b, 2
2b, ... Show that the potential rises due to the charge. Before the potentials of the capacitors 21b, 22b, ... Are lowered from the “H” defined potential V _T by discharging, the potentials are raised by charging to rewrite data. Each memory cell in the register unit 70 of the semiconductor integrated circuit device of FIG. 1 also needs a refresh operation because it is a DRAM memory cell. Each memory cell in the register unit 70 is similarly refreshed by inputting a refresh signal from the refresh counter 23. That is, the refresh signal becomes "H", and the NMOSs 71 and 73 are turned on.
As a result, the "H" level of the drains of the NMOSs 72 and 74 is guaranteed, and the refresh operation is completed.

In the write operation, the bit line selection signal becomes "H" and the NMOSs 57 and 58 are turned on.
As a result, the serial data from the data buses DT and DT / is written in each DRAM memory cell in the register unit 70 and converted into parallel data. After that, the first gate is turned on by the control signal, the data is transferred to the memory cell array, and the data is written in each DRAM cell in the memory cell array. By providing the register unit 70 having the above-mentioned function on the data input side and the data output side of the memory cell array composed of DRAM memory cells, a conventional semiconductor integrated circuit device similar to that of FIG. 2 is realized. To be done. By providing two register units 70 on the output side, a degree of freedom in reading data can be obtained. As described above, in the present embodiment, the register unit 70 is a DRAM memory configured by the NMOS 71 to 74 of the same channel in contrast to the register units 10, 30, 40 configured by the conventional complementary NMOS and PMOS. It has a cell. for that reason,
When the semiconductor integrated circuit device of FIG. 1 is manufactured, for example, if the memory cell array is also an NMOS, it can be manufactured in a rational process. Further, element isolation or the like in each of the NMOSs 71 to 74 can be omitted, and the pattern area can be reduced. Each memory cell of the register unit 70 becomes a DRAM memory cell and needs to be refreshed, but since the refresh counter 23 and the refresh controller 24 of the memory cell array can be used, no special means is required.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) Each DRAM memory cell in the register unit 70 is
The same effect as that of the present embodiment can be obtained even with a DRAM memory cell composed of PMOS. Good. (2) With respect to the memory cell array, the data writing register unit 70 is provided on the input side and the data reading register unit 70 is provided on the output side. However, depending on the application, only one pair of data transfer data buses is provided, and the register unit is provided. 70 may be an input / output register.

[0014]

As described above in detail, according to the first aspect of the invention, since each register is formed by using the DRAM memory cell, each register of the semiconductor integrated circuit device is refreshed like a memory cell array. Will be rewritten with. Therefore, for example, the control of the DRAM memory cell in each register can reduce the scale of the semiconductor integrated circuit device without providing a special control unit as compared with the related art, for example. According to the second aspect of the invention, since each register is composed of the same channel type MOS transistors, the pattern area can be reduced.
Further, for example, if the MOS transistors forming the memory cell array are the same-channel type MOS transistors, they can be manufactured in a rational process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit example of a conventional semiconductor integrated circuit device.

FIG. 3 is a circuit diagram showing a register unit and a DRAM unit in FIG.

FIG. 4 is a diagram showing discharge characteristics of a DRAM memory cell.

FIG. 5 is a diagram showing charging characteristics of a DRAM memory cell.

[Explanation of symbols]

21a, 22a NMOS 21b, 22b Capacitor 55,56 NMOS (first gate) 57,58 NMOS (second gate) 71,73 NMOS (third and fourth MOS transistors) 72,74 NMOS (first, second, first) MOS transistor) BL, BL / bit line WL word line DT, DT / data bus

Claims (2)

[Claims] 1. A memory cell array having a plurality of word lines and a plurality of bit line pairs intersecting the word lines, and a dynamic memory cell composed of a MOS transistor connected to each of the intersections and arranged in a matrix. A plurality of first transfer gates that are respectively connected to each bit line pair and that are turned on and off based on a control signal; and a plurality of first transfer gates that are respectively connected to the bit line pair via the first transfer gates and are connected to the memory cell. Serial data / holds write data or read data respectively
A plurality of registers for parallel data mutual conversion, a plurality of second transfer gates which are respectively connected between the respective registers and the data bus and which are turned on / off by a bit line selection signal, and a refresh signal is output. And a refresh circuit that sequentially selects the plurality of word lines and rewrites the memory cells, wherein each register is configured using the same circuit as the memory cell. In addition, the semiconductor integrated circuit device is configured to perform rewriting by the refresh signal. 2. Each of the registers has a first and a second MOS transistor for holding data, which is connected between two bit lines forming a bit line pair, and is turned on / off by the refresh signal. And a third and a fourth MOS transistor for rewriting which sets the first and the second MOS transistors to a constant potential when in the ON state, and the first, the second, the third and the fourth. 2. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor is composed of a same-channel type MOS transistor.