JPH07181227A - Integrated circuit - Google Patents

Abstract

PURPOSE:To easily test a bi-directional buffer from the outside of an integrated circuit. CONSTITUTION:A test of a bi-directional buffer B10 consisting of an input buffer IB and a tri-state output buffer OTB is carried out by changing a test mode signal TMD to an activating condition. Thereby, it is possible to exchange a signal-input/output direction of the bi-directional buffer B10 in accordance with an input signal from an input pin 11. The input buffer 18 and the tri-state output buffer OTB can be directly accessed from an input pin P12, an output pin P15 or an input/output pin P16, thereby it is possible to test it by means of comparatively fewer test patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which a functioning internal circuit is built, which is connected to an external circuit through an input pin, an output pin or an input / output pin provided on the package. In a bidirectional buffer that is used for output as well as signal input to and output from an external circuit, test the input buffer and output buffer of the bidirectional buffer using a relatively simple and relatively short test pattern. And an integrated circuit capable of

[0002]

2. Description of the Related Art A method of testing an internal circuit of an integrated circuit for testing the operation of a logic circuit built in a manufactured integrated circuit is called a test pattern from the outside to the input of the integrated circuit. Is performed, and the output signal output from the integrated circuit is observed. In addition, for inputting and outputting signals to and from the outside of the integrated circuit, in particular, regarding the input circuit and the output circuit, independent from the test of the internal circuit of the integrated circuit, for example, the electrical characteristics should be examined. For the purpose, it has been conventionally performed from the outside via an input pin, an output pin or an input / output pin of the integrated circuit.

For example, when testing the input circuit of an integrated circuit or measuring the electrical characteristics, while observing the logic state output by the input circuit while inputting a signal to the input circuit to be implemented. To do. The observation of the logical state is
This is done by observing the logic state output from the output pin of the integrated circuit under test while inputting the test pattern to other input pins.

On the other hand, for example, when testing an output circuit for outputting a signal to the outside of an integrated circuit or measuring the electrical characteristics, a desired logic state is input to the target output circuit,
Along with this, the output characteristic of the output circuit is observed. The logic state is input to this output circuit while inputting a test pattern to the input pin of the target integrated circuit. In addition, the logic state output by the output circuit to which the predetermined logic state is input and the output characteristic thereof can be observed from the output pin to which the output of the output circuit is connected during the test or measurement of the electrical characteristics.

As described above, in the test of the input circuit and the output circuit of the integrated circuit, many test patterns are used in order to read the logic state of the test result and set the logic state to be input in the test. I need. In particular, in recent years, the degree of integration of integrated circuits has been improved, the internal circuits thereof have become complicated, and the number of input pins, output pins, or input / output pins has tended to increase. It becomes a thing.

As a technique for facilitating the test of the input circuit and the output circuit of such an integrated circuit, for example, Japanese Patent Laid-Open No. 62-62 is known.
In -50674, the input buffer output of the integrated circuit is used as one input, and the signal processed inside the integrated circuit and taken out is used as the other input. Also, one of them has a built-in selection circuit which is selected by a test signal. Further, a technique is disclosed in which the input characteristic of the input buffer and the output characteristic of the output buffer are tested by connecting the output of the selection circuit to the output buffer of the integrated circuit. In this technique, when testing an input circuit such as an input buffer or an output circuit such as an output buffer, a special mode, that is, a test mode is set at this time, whereby an input circuit or an output circuit to be tested is It allows direct access from outside the integrated circuit. Therefore, according to Japanese Patent Laid-Open No. 62-50674, the input circuit and output circuit of the integrated circuit can be tested with a simple test pattern such as test designation.

Further, in Japanese Patent Laid-Open No. 11-11365, a plurality of input terminals and output terminals, an internal circuit composed of a logic circuit, and the plurality of input terminals and the internal circuit are respectively connected in series. Regarding a semiconductor integrated circuit having a plurality of input buffers and a plurality of output buffers connected in series between the plurality of output terminals and an internal circuit, the same integrated circuit as in the above-mentioned JP-A-62-50674. There is disclosed a technique for facilitating the test of the input circuit and the output circuit. In this technique, first, when a test terminal and a test signal are input to this test terminal,
It is said that the output end of the input buffer and the input end of the output buffer are electrically connected to each other so that the input signal input to the input terminal is output to the output terminal via the output buffer without passing through the internal circuit. The technology is disclosed. This technique is also described in JP-A-62-50674.
Similarly, in the test mode in which the test signal is input, the input circuit and the output circuit to be tested can be directly accessed from the outside of the integrated circuit. Particularly, in Japanese Patent Laid-Open No. 11-11365, the input circuit and the output circuit to be tested are connected in series so that the input circuit and the output circuit can be directly accessed from outside the integrated circuit. In the technique disclosed in Japanese Patent Laid-Open No. 11-11365, the above-mentioned Japanese Patent Laid-Open No. 62-50674 is also used.
Similarly, a relatively short or simple test pattern can be used to test the input and output circuits of the integrated circuit.

[0008]

However, the technique disclosed in Japanese Patent Laid-Open No. 62-50674 and the technique disclosed in Japanese Patent Laid-Open No. 11-11365 are subject to testing. The only thing is the input circuit and output circuit of the integrated circuit.

In the integrated circuit, an input circuit used to input a signal from a certain one input pin, an output circuit used to output a signal to a certain one output pin, and one input / output. While inputting a signal using a pin,
Further, there is a bidirectional input / output circuit which also outputs a signal.
This bidirectional input / output circuit is not simply a combination of the input circuit as described above and the output circuit as described above, and has an additional control function such as control of the input / output direction of the signal. ing.

Therefore, the techniques disclosed in the prior art, for example, the above-mentioned JP-A-62-50674 and JP-A-1-1113 are disclosed.
The technique disclosed in No. 65 cannot be simply applied to test such a bidirectional input / output circuit.

The present invention has been made to solve the above conventional problems, and provides an integrated circuit using a bidirectional input / output circuit having a bidirectional buffer for inputting / outputting a signal to / from an external circuit. Therefore, it is an object of the present invention to provide an integrated circuit that can test the input buffer and the output buffer of the bidirectional buffer by using a relatively simple and relatively short test pattern.

[0012]

The present invention relates to an integrated circuit in which a functioning internal circuit is built, which is connected to an external circuit through an input pin, an output pin or an input / output pin provided in the package, A bidirectional buffer including an input buffer IB having its input connected to the same input / output pin as the input / output pin P16 for bidirectional buffer, and a tristate output buffer OTB having its output connected A buffer B10, a direction switching signal input pin P11 used for inputting a test buffer direction switching signal TDR, and a test signal TS used for testing the tristate output buffer included in the bidirectional buffer.
bidirectional buffer output test input pin P12 used for input of a, test mode input pin P13 used for input of test mode signal TMD, and bidirectional buffer B10
And a test signal TSa according to the test mode signal TMD, and a bidirectional buffer input test output pin P15 used to output the test signal TSb of the input buffer and to output an internal circuit output signal OSb.
The internal circuit output signal OSa output from the internal circuit is selectively selected, and the selected one is selected as the bidirectional buffer B.
According to the test mode signal TMD and the bidirectional buffer input signal multiplexer S12 which outputs to the output buffer OTB of 10 and the test signal TSb.
And an internal circuit output signal OS output from the internal circuit
b), the bidirectional buffer output signal multiplexer S11 for outputting the selected one to the bidirectional buffer input test output pin P15, and the test buffer direction switching signal according to the test mode signal TMD. Bidirectional buffer that selectively selects TDR and the internal circuit direction switching signal ODR output from the internal circuit, and outputs the selected one to the control input of the tri-state output buffer OTB included in the bidirectional buffer B10. By including the control signal multiplexer S13,
The above object has been achieved.

Further, in the integrated circuit, the direction switching signal input pin P11 is used for inputting the test buffer direction switching signal TDR and also for inputting the internal circuit input signal ISa. Yes,
Also, the bidirectional buffer output test input pin P12
Is used for inputting the test signal TSa,
Further, by being used also for inputting the input signal ISb for the internal circuit, it is possible to achieve the above-mentioned problems and reduce the number of input pins, output pins, input / output pins, etc., which are provided especially for testing. It is the one.

[0014]

In the integrated circuit, the pins connected to the external circuit include bidirectional input / output pins, which not only input signals but also output signals. For example, it is an input / output pin connected to the data bus line. For such an input / output pin, a bidirectional input / output circuit having a bidirectional buffer is provided inside the integrated circuit.

This bidirectional input / output circuit is in the bidirectional buffer, and is not simply a combination of an input buffer and an output buffer. For example, the output buffer used in such a bidirectional input circuit has a tri-state output.

This is because the signal output from the output buffer of the bidirectional input / output circuit and the signal input from the external circuit collide at the bidirectional input / output pin. This is to prevent

When a signal is input from an external circuit,
On the other hand, the output of the output buffer of the bidirectional buffer inside the integrated circuit needs to be in a high impedance state. Therefore, such bidirectional buffers need to have tri-state outputs. Further, in a bidirectional buffer having such an output buffer of tri-state output, it is necessary to also control the direction switching of the signal, and a direction switching control circuit used for this is also provided.

As described above, the bidirectional input / output circuit is not simply a combination of the input circuit and the output circuit, but has an additional circuit and has an additional function. Therefore, in order to test such a bidirectional input / output circuit, it is necessary to carry out signal direction switching control, and it is also necessary to test a circuit used for such direction switching control. . The present invention has been made paying attention to such a point.

FIG. 1 is a logic circuit diagram showing the gist of the present invention.

As shown in FIG. 1, in the integrated circuit of the present invention, with respect to the bidirectional input / output circuit to be tested, the bidirectional buffer B10, the direction switching control input pin P11, and the bidirectional Input pin P for buffer output test
12, a test mode input pin P13, a bidirectional buffer input test output pin P15, a bidirectional buffer input / output pin P16, a bidirectional buffer input signal multiplexer S12, and a bidirectional buffer output signal multiplexer S11. Buffer control signal multiplexer S1
3 and 3. The bidirectional buffer B10 has an input buffer IB and an output buffer OB.

The bidirectional buffer B10 is connected to the bidirectional buffer input / output pin P16. That is, the input of the input buffer IB of the bidirectional buffer B10 is connected to the bidirectional buffer input / output pin P16, and the bidirectional buffer B10 is further connected.
The output of the tri-state output buffer OTB included in the bidirectional buffer input / output pin P1
6 is connected. The input buffer IB outputs a signal ISc to an internal circuit according to a signal input from the bidirectional buffer input / output pin P16. on the other hand,
The tri-state output buffer OTB outputs the output signal OSa from the internal circuit to the bidirectional buffer input / output pin P16. The tri-state output buffer OTB is usually controlled by a direction switching signal ODR from an internal circuit.

Further, the bidirectional buffer B10 receives the test mode signal TMD in the active state when it is input.
First, with respect to the input buffer IB, the signal output from the input buffer IB can be output from the bidirectional buffer input test output pin P15 via the bidirectional buffer output signal multiplexer S11 and the like described in detail later. . Therefore, the operation of the input buffer IB of the bidirectional buffer B10 and the output buffer O connected to the bidirectional buffer input test output pin P15.
The operation of B and the like can be tested by a signal output from the bidirectional buffer input test output pin P15.

The tri-state output buffer OTB of the bidirectional buffer B10 is input from the outside of the integrated circuit via the bidirectional buffer output test input pin P12 and the bidirectional buffer input signal multiplexer S12 which will be described in detail later. Can be tested by the signal that is made. That is, in addition to the operation of the tri-state output buffer OTB, the operation of the input buffer IB or the like connected to the bidirectional buffer output test input pin P12 is performed by using the signal output from the bidirectional buffer input / output pin P16. It can be tested by observing.

The test mode signal TMD is related to the bidirectional buffer input signal multiplexer S12, the bidirectional buffer output signal multiplexer S11, the bidirectional buffer control signal multiplexer S13, or these, centering on the bidirectional buffer B10. For other input buffers IB, output buffers OB, etc., by selecting whether to perform normal operation or operation according to the test mode for the circuit built in the integrated circuit, The bidirectional buffer B10
This is a control signal for switching so as to perform a test centered on "etc." For example, by selecting the test mode in this way, not only the test of the bidirectional buffer B10 but also the test of the input buffer IB and the output buffer OB provided in the vicinity can be performed. There is.

When such a test is performed by the test mode signal TMD input to the test mode input pin P13, the direction switching signal input pin P11 and the bidirectional buffer control signal described later in detail. The test buffer direction switching signal TDR input via the multiplexer S13 or the like controls the input / output direction of the signal input / output from the bidirectional buffer input / output pin P16.

The bidirectional buffer input signal multiplexer S12 selects one of the test signal TSa and the internal circuit output signal OSa output from the internal circuit according to the test mode signal TMD, and selects the selected one. The data is output to the output buffer OTB included in the bidirectional buffer B10. In order to output a signal from the output buffer OTB to the bidirectional buffer input / output pin P16, the direction switching signal D output from the bidirectional buffer control signal multiplexer S13.
R needs to be in an active state (H state).

Further, the bidirectional buffer output signal multiplexer S11 selects one of the test signal TSb and the internal circuit output signal OSb output from the internal circuit according to the test mode signal TMD, and is selected. The output pin P1 for the bidirectional buffer input test
Output to 5. Therefore, the bidirectional buffer output signal multiplexer S11 outputs the internal circuit output signal OSb during the normal operation, while it outputs the internal circuit output signal OSb during the test mode.
The input buffer I included in the bidirectional buffer B10
To test B, the signal output by the input buffer IB is output.

The bidirectional buffer control signal multiplexer S13 selects one of the test buffer direction switching signal TDR and the internal circuit direction switching signal ODR output from the internal circuit according to the test mode signal TMD. The selected one is output as the direction switching signal DR to the control input of the tri-state output buffer OTD included in the bidirectional buffer B10. That is,
During normal operation, the bidirectional buffer control signal multiplexer S13 controls the input / output direction of the signal of the bidirectional buffer B10 by the internal circuit direction switching signal ODR generated by the internal circuit built in the integrated circuit.
On the other hand, in the test mode, the bidirectional buffer control signal multiplexer S13 receives the signal of the bidirectional buffer B10 according to the test buffer direction switching signal TDR input from the outside of the integrated circuit via the direction switching signal input pin P11. It controls the input / output direction of.

As described above, a bidirectional input / output used for inputting / outputting a signal to / from an external circuit, that is, a bidirectional input / output used for inputting / outputting a signal to / from the same input / output pin. As for the circuit, according to the present invention, the input / output circuit can be tested more easily. That is,
The input buffer and the output buffer included in the bidirectional buffer included in the input / output circuit can be tested using a relatively simple and relatively short test pattern.

As described above with reference to FIG. 1, in the present invention, by inputting the test mode signal TMD input to the test mode input pin P13 to the active state, the signal of the bidirectional buffer B10 is input. According to the test buffer direction switching signal TDR inputting the output direction from the direction switching signal input pin P11,
It can be switched from outside the integrated circuit. Further, while performing such switching, the bidirectional buffer B10
Can test the operation of the input buffer IB and the operation of the tristate output buffer OTB. For example, in such a test, the test mode signal TMD is input, the test buffer direction switching signal TDR is input, and the bidirectional buffer output test input is used in a test performed after these inputs. Pin P
12 signal inputs and the bidirectional buffer input / output pin P
Inputting or outputting a signal to or from the output pin P15 for bidirectional buffer input test can be performed by using a relatively short or relatively simple test pattern.

Although the present invention is not limited to this, the direction switching signal input pin P11 and the bidirectional buffer output test input pin P12 shown in FIG. It is also possible to make more efficient use of the pins provided in the integrated circuit.

Specifically, as shown in FIG. 1, the direction switching signal input pin P11 is used to input the test buffer direction switching signal TDR, and further, another internal circuit input signal ISa is used. It is also used for input. Further, the bidirectional buffer output test input pin P12 is used not only for inputting the test signal TSa but also for inputting the internal circuit input signal ISb of the integrated circuit.

This depends on whether the input of the test mode signal TMD is in the active state or the inactive state, and these direction switching signal input pins P are used.
11 and the use of the bidirectional buffer output test input pin P12 are changed.

By doing so, at least the direction switching signal input pin P11 and the bidirectional buffer output test input pin P12 can be used together with a conventional one for internal circuit without newly installing. Is. That is, in FIG. 1, only the test mode input pin P13 is newly provided, and the electrical characteristics of the input buffer, the output buffer, and the input / output buffer can be measured by only adding one pin. In particular, the number of input pins, output pins, input / output pins, etc. on the package of the integrated circuit, which is limited by the size of the package in which the integrated circuit is sealed, is limited. However, even in such a case, the test function as in the present invention can be incorporated more effectively.

As described above, even when the direction switching signal input pin P11, the bidirectional buffer output test input pin P12 and the like are used in combination with the input signals ISa and ISb, the test mode input is performed. It is preferable that the pin P13 is newly provided and not used together with the input signal in the normal mode. Because the test mode signal TM input from the test mode input pin P13
This is because the test mode and the normal mode are switched by D.

[0036]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a logic circuit diagram including an input / output circuit using the bidirectional buffer of the integrated circuit of the first embodiment to which the present invention is applied.

As shown in FIG. 2, in the integrated circuit of the first embodiment, an input circuit, that is, an input buffer IB is provided for each of the input pins P21 to P26. Further, for the output pins P27 to P29, P31 and P32, an output circuit, that is, an output buffer B13.
Is provided. An input / output circuit B12 using a bidirectional buffer is provided for the input / output pins of P30 and P33. In particular, the input / output circuit B12 includes the bidirectional buffer B10 shown in FIG. 1 as shown in detail with reference to FIG.

The feature of the first embodiment is that one bidirectional buffer control signal multiplexer S13 is provided for the two input / output circuits B12. This is because the switching of the input / output direction of the signal to / from the bidirectional buffer input / output pin P30 or P33 of the input / output circuit B12 is simultaneously performed by the direction switching signal DR.

Another feature of this embodiment is that the bidirectional input / output circuit B12 to which the present invention is applied is tested and, for example, the input pin P used for the input / output circuit B12 is tested.
23. In addition to the test of the input buffer IB connected to 23, P24, etc., for example, the input pin P21, the input pin P24, the output pin P27, the output pin P3, etc.
With respect to No. 1 and the like, the test of the input circuit and the output circuit used for them can be performed using a relatively short and relatively simple test pattern.

The symbols IS10 to IS14 shown in FIG. 2 of the first embodiment, the symbols IS21 to IS23 of FIG. 5 in the second embodiment described later, and the IS31 to IS31 of FIG. 6 in the third embodiment described later. The IS 34 is connected to an internal circuit built in the integrated circuit, and uses the signals from the respective input pins as an input signal for the operation of the internal circuit at a normal time other than the test mode. is there.

FIG. 3 is a circuit diagram of the input / output circuit used in the first embodiment.

FIG. 3 shows the internal circuit of the input / output circuit B12 used in the first embodiment and also in the second and third embodiments described later. As shown in FIG. 3, the input / output circuit B12 is
Input buffer IB and tri-state output buffer OTB
And a bidirectional buffer input signal multiplexer S12.

The input buffer IB shown in FIG.
Regarding the tri-state output buffer OTB,
This corresponds to the input buffer IB or the tri-state output buffer OTB included in the bidirectional buffer B10 shown in FIG. That is, the input buffer IB and the tristate output buffer OTB shown in FIG. 3 form a bidirectional buffer.

FIG. 4 is a circuit diagram of an output circuit used in the first embodiment.

FIG. 4 shows the circuit of the output circuit B13 used in the first embodiment and also used in the second and third embodiments described later. As shown in FIG. 4, the output circuit B13 is composed of a multiplexer S21 and an output buffer OB.

The multiplexer S21 selects one of the test signal TSn and the internal circuit output signal OSn output from the internal circuit according to the test mode signal TMD, and selects the selected one through the output buffer OB.
Output pin (for example, symbols P27 to P29 in FIG. 2)
Is output to. The test signal TSn can be directly input from the outside of the integrated circuit, for example, the test signal TS10 input via the input pin P21 and the input buffer IB connected thereto in FIG. is there. Therefore, the test mode signal TMD is activated and the test signal TS is input to the output buffer OB of the output circuit B13.
By selecting n, a test of the input buffer connected to the input pin that outputs the test signal TSn,
It is possible to test the output buffer OB connected to the next stage of the output of the multiplexer S21 with a relatively short and simple test pattern.

In the first embodiment and also in the second embodiment which will be described later, one direction switching signal DR is output to one bidirectional buffer control signal multiplexer S13 and is output from this bidirectional buffer control signal multiplexer S13. For a total of 2
A plurality of the input / output circuits B12 are provided. However, in addition to this, for example, one bidirectional buffer control signal multiplexer S13, or one direction switching signal DR output from this bidirectional buffer control signal multiplexer S13
It is also possible to provide one or more input / output circuits B12. That is, as long as the control of the signal input / output direction of the bidirectional buffers of the respective input / output circuits B13 is performed at the same time during the normal operation, one such bidirectional buffer control signal multiplexer S13 that is common, It is possible to use one of the direction switching signals DR.

FIG. 5 is a circuit diagram of an input circuit, an output circuit and an input / output circuit portion of the integrated circuit of the second embodiment to which the present invention is applied.

In the second embodiment, as in the first embodiment, one bidirectional buffer control signal multiplexer S13 is shared by the two input / output circuits B12. Further, in the second embodiment, the test signal TSa input to each of these two input / output circuits B12 is also shared by one. That is, for the test signals TSa 1 or TSa 2 of these two input / output circuits B12 connected to the input / output pins P48 or P50, respectively, via the input pin P43 or the input buffer IB connected to the input pin P43. In the test mode, one test signal input from the outside of the integrated circuit is input.

As described above, in the second embodiment, the input pins used for the input of the test signal TSa input from the outside in the test mode are made common to the plurality of the input / output buffers B12, and the number of the input pins is made common. Can be reduced.

FIG. 6 is a circuit diagram of an integrated circuit of the third embodiment to which the present invention is applied, particularly an input circuit, an output circuit and an input / output circuit portion.

In the third embodiment, as shown in FIG. 6, the output of the input buffer IB connected to the input pins P63 and P64 with respect to the test signal TSa of one input / output circuit B12. Can be entered. As a result, when the test mode signal TMD is activated and the input circuit, the output circuit, or the input / output circuit is tested, not only the input circuit and the output circuit of the input / output circuit B12 but also the input pin P63. Also, it is possible to test the input buffer IB connected to each of the input pins P64.

In particular, the third embodiment can also test two or more input pins or input buffers connected to the input pins as described above. Therefore, when applied to an integrated circuit having a large number of input pins as compared with the number of output pins or the number of input / output pins, the number of output pins is increased without increasing the number of output pins or input / output pins. It is possible to more effectively test the input buffer connected to the input pin.

In the third embodiment, the input signal TSa 1 or TSa 2 input via these input pins P63 and P64 and their respective input buffers IB is input.
On the other hand, an AND logic gate G1 is provided to obtain the test signal TSa. Therefore, when the input buffer IB connected to the input pin P63 is tested in the test mode, the signal input through the other input pin P64 and the input buffer IB should be in the H state. Good. On the other hand, the input pin P64
When testing the input buffer IB connected to, the signal input via the input pin P63 and the input buffer IB connected to the input pin P63 may be set to the H state.

It is also possible to use, for example, an OR logic gate instead of the AND logic gate G1.
In this case, when testing the input buffer IB connected to one input pin P63 or P64, the L state may be input to the other input pin P63 or P64.

In FIG. 6, the AND logic gate G1 has two inputs. However, it is also possible to use not only this kind of structure but also, for example, an AND logic gate or an OR logic gate having three inputs or more. In this case, it is possible to test the input buffer connected to more input pins while using one input / output circuit B12.

[0058]

As described above, according to the present invention,
In an integrated circuit that also uses a bidirectional input / output circuit having a bidirectional buffer for inputting / outputting an external circuit and a signal, a test of an input buffer and an output buffer included in the bidirectional buffer is relatively simple and comparative It is possible to obtain an excellent effect that it is possible to provide an integrated circuit that can be performed by using an extremely short test pattern.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram showing the gist of the present invention.

FIG. 2 is a circuit diagram of an input circuit, an output circuit, and an input / output circuit portion of the integrated circuit of the first embodiment to which the present invention is applied.

FIG. 3 is a circuit diagram of an input / output circuit used in the first embodiment.

FIG. 4 is a circuit diagram of an output circuit used in the first embodiment.

FIG. 5 is a circuit diagram of an input circuit, an output circuit, and an input / output circuit portion of the integrated circuit of the second embodiment to which the present invention is applied.

FIG. 6 is a circuit diagram of an input circuit, an output circuit and an input / output circuit portion of an integrated circuit according to a third embodiment of the present invention.

[Simple explanation of symbols]

P11-P13, P21-P26, P41-P44, P
61 to P65 ... Input pins P14, P27 to P29, P31, P32, P45 to P
47, P49, P66 to P68 ... Output pins P16, P30, P33, P48, P50, P69 ... Input / output pin S11 ... Bidirectional buffer output signal multiplexer S12 ... Bidirectional buffer input signal multiplexer S13 ... Bidirectional buffer control signal multiplexer S21 ... multiplexer G1 ... AND logic gate IB ... input buffer OB ... output buffer OTB ... tri-state output buffer ISa, ISb, IS10-IS14, IS21-IS
23, IS31 to IS34 ... Input signal (input to internal circuit) TDR ... Test buffer direction switching signal ODR ... Internal circuit direction switching signal DR ... Direction switching signal TMD ... Test mode signal OSa, OSb, OS10-OS16, OS21-OS
26, OS31 to OS34 ... Output signal (output from internal circuit) TSa, TSa1, TSa2, TSb, TSb1, TS
b2 ... Test signal

Claims (2)

[Claims] 1. A bidirectional buffer input / output pin P16 in an integrated circuit in which a functioning internal circuit is built, which is connected to an external circuit through an input pin, an output pin or an input / output pin provided in the package. To the same input / output pin, the input buffer IB connected to its input and the tri-state output buffer OTB connected to its output, and the test buffer direction A direction switching signal input pin P11 used for inputting a switching signal TDR, and a bidirectional buffer output test input pin P12 used for inputting a test signal TSa used for testing the tri-state output buffer of the bidirectional buffer. , A test mode input pin P13 used for inputting a test mode signal TMD, and the bidirectional buffer The output of the test signal TSb of the input buffer of the buffer B10 is also the internal circuit output signal O.
According to the test mode signal TMD, the bidirectional buffer input test output pin P15 which is also used for the output of Sb, the test signal TSa, and the internal circuit output signal OSa output from the internal circuit are selected and selected. Output buffer OTB included in the bidirectional buffer B10, the bidirectional buffer input signal multiplexer S12
According to the test mode signal TMD, the test signal TSb and the internal circuit output signal OSb output from the internal circuit are selectively selected, and the selected one is output to the bidirectional buffer input test output pin P15. And a bidirectional buffer output signal multiplexer S11 for outputting the test buffer direction switching signal TDR and an internal circuit direction switching signal ODR output from the internal circuit according to the test mode signal TMD. And a bidirectional buffer control signal multiplexer S13 for outputting the output to the control input of the tristate output buffer OTB included in the bidirectional buffer B10. 2. The direction switching signal input pin P11 according to claim 1, which is used not only for inputting a test buffer direction switching signal TDR but also for inputting an internal circuit input signal ISa. Yes, the bidirectional buffer output test input pin P12
Is used for inputting the test signal TSa, and
Further, the integrated circuit is also used for inputting the input signal ISb for the internal circuit.