JPH07175750A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data at a high speed via a bus master while maintaining the conventional software compatibility in regard of a local bus that does not support the I/O slave of a DMA by reading the register of a DMAC(direct memory access controller) in a system by the use of the I/O slave. CONSTITUTION:When data are transferred, the software sets the number of data to be transferred, a data writing start address and the data transfer direction to the register of a DMAC 1 included in a system. Then the software gives a data transfer request to an I/O slave circuit 4. A register reading circuit 2 decides that the transfer of data can be started and notifies a bus master circuit 3 of the number of data to be transferred, the data writing start address and the data transfer direction by a signal 52 which is set to the internal register of the circuit 3. Then the circuit 3 receives data from the circuit 4 via a signal line 53 and then transfers the data to a local bus 21 according to a signal 54.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to input / output (I / O) devices in small computer systems.

[0002]

2. Description of the Related Art Generally, in a system bus, direct memory access control (DMA) in a system is performed.
If an I / O device that used C) tries to transfer by a higher speed bus master for the purpose of speeding up, it is not compatible with the conventional DMA transfer and software is newly developed. I had to. For example, April 1993, Super ASCII, pages 38-39, mentions that new software is required for memory management when using a bus master.

[0003]

In recent years, I / O devices have become able to process large amounts of data at higher speeds. As the performance of the I / O device is improved, there are the following two problems when high-speed data transfer is attempted between the I / O device and the system bus.

The first problem is that in a high-speed local bus, the protocol of the bus becomes complicated, and so on.
The MA I / O slave functionality tends to be unsupported. At this time, data transfer is performed by a bus master method or the like having a simpler bus protocol, but software compatibility cannot be maintained between the new register of the bus master method and the conventional DMAC register.

A second problem is that when an I / O device tries to support a high-speed bus master system on the system bus, a high-speed bus master system register and an in-system DM are used.
This means that software compatibility cannot be maintained with the AC register.

Conventionally, in order to solve these problems, it is often necessary to newly design, which requires a long development period.

[0007]

The means for solving the first problem is that an I / O slave has a DMAC register in the system immediately before data transfer in a high-speed local bus having no DMA I / O function. This is a method of reading out the information and notifying the information to the bus master function, and performing the transfer by the bus master method while maintaining software compatibility with the DMA transfer.

The means for solving the second problem is that the I / O slave in the system bus reads the register of the DMAC in the system immediately before the data transfer, informs the information to the bus master function, and transfers by the bus master method. Is the way to do it.

The means for solving the third problem allows the circuit of the conventional DMA slave to be used as it is by providing the means for solving the first problem with the function of accessing the conventional DMA slave. That is.

The means for solving the fourth problem enables the circuit of the conventional DMA slave to be used as it is by providing the means for solving the second problem with a function of accessing the conventional DMA slave. That is.

[0011]

FIG. 1 shows an embodiment of the first invention. In FIG. 1, a local bus 21 is a bus that enables high-speed data transfer by a bus master method and does not have the I / O slave function of the in-system DMAC 1. In-system DMAC
The contents of the register 1 can be read by the local bus 21 and the register read signals 51 and 56 of the in-system DMAC 1. The register read circuit 2 receives the D signal by the register read signal 51 of the DMAC1 in the system.
The register of MAC1 can be read out, has a signal 55 for monitoring a data request to the I / O slave circuit 4, and the bus master circuit 3 can use the signal 52 to read the contents of the register read from the in-system DMAC1 inside the bus master circuit 3. You can set the register. The bus master circuit 3 is connected to the I / O slave circuit 4 by a signal 53 that receives data from the I / O slave circuit 4, and is connected to the local bus 21 by a signal 54 that transfers data to the local bus 21. It is possible to receive data from the conventional I / O slave circuit 4 by the signal 53 that receives the data from the circuit 4 and transfer the data to the local bus 21 from the signal 54 that transfers the data to the local bus 21. The software sets the register of the DMAC in the system and requests the conventional I / O slave 4 for data transfer.

When data is transferred, the software is transferred by the conventional DMA.
The number of data transfers required for data transfer, the data write start address, and the data transfer direction are set in the 1 register. Next, the software makes a data transfer request to the I / O slave circuit 4. A signal for the register read circuit 2 to set the internal register of the bus master circuit 3 to the bus master circuit 3 after judging that the data transfer can be started from the signal 55 for monitoring the data request to the conventional I / O slave circuit 4. By 52, the number of data transfers, the data write start address, and the data transfer direction are notified. Signal line 5 from conventional I / O slave circuit 4
3 receives data from the conventional I / O slave circuit 4,
The bus master circuit 3 transfers the data to the local bus 21 by the signal 54 for transferring the data to the local bus 21.

An embodiment of the second invention is shown in FIG. In FIG. 2, the system bus 31 is a bus having a DMA I / O slave function by a DMA request signal 56 and a DMA acknowledge signal 57 that connect the intra-system DMAC 1 and the system bus 31. The contents of the register of the in-system DMAC1 can be read by the register read signals 51 and 58 of the in-system DMAC1. The register read circuit 2 is connected to the system bus 31 by the register read signal of the in-system DMAC 1 and can read the register of the in-system DMAC 1, and the register read circuit 2 sends a data request to the I / O slave circuit 4. A signal 55 to monitor is provided. In addition, the register read circuit 2 is connected to the bus master circuit 3 in the system D
The contents of the register read from the MAC1 can be written via the signal line 52. The bus master circuit 3 is an I / O
The slave circuit 4 and the I / O slave circuit 4 are connected by a signal 53 for monitoring a data request, and the bus master circuit 3 is connected to the system bus 31 by a signal 54 for transferring data to the system bus 31. Also, the bus master circuit 3
Can receive data through the I / O slave circuit 4 signal line 53 and transfer the data through the system bus 31. The software sets the register of the DMAC in the system and requests the conventional I / O slave circuit 4 for data transfer.

When data is transferred, the software is first transferred by the conventional DMA, so that the in-system DMAC is used.
The number of data transfers required for data transfer, the data write start address, and the data transfer direction are set in the 1 register. Next, the software makes a data transfer request to the I / O slave circuit 4. The register read circuit 2 determines from the signal 55 that monitors the data request to the I / O slave circuit 4 that data transfer can be started, and the signal 52 that sets the bus master circuit 3 in the register in the bus master circuit determines the number of data transfers. The data write start address and the data transfer direction are notified. Next, the data is received from the I / O slave circuit 4 through the signal line 53, and the bus master circuit 3 transfers the data to the system bus 31.

An embodiment of the third invention is shown in FIG. In FIG. 3, the system bus 21 enables data transfer by a high-speed bus master system, and the I / O of the in-system DMAC 1
It is a bus that does not have a slave function. In-system DMA
The contents of the C1 register can be read by the local bus 21 and the register read signals 51 and 56 of the in-system DMAC1. In the I / O device 11, the register read circuit 2 is connected to the local bus 21 by the register read signal 51 of the in-system DMAC 1 and can read the register of the in-system DMAC 1. In addition, the bus master circuit 3 has a DMAC1 in the system.
The contents of the read register can be written by the signal 52 which sets the internal register of the bus master circuit 3. The bus master circuit 3 is connected to the DMA slave circuit 5 by the DMA transfer signal 59 from the DMA slave circuit 5, and is connected to the system bus 21 by the signal 54 for data transfer to the local bus 21. Also, the bus master circuit 3
Is a DMA transfer signal 59 from the DMA slave circuit 5 and D
The local bus 2 receives from the signal 54 that receives data from the MA slave circuit 5 and transfers the data to the local bus 21.
Data can be transferred to 1. The software sets the register of the DMAC in the system and requests the conventional DMA slave 5 for data transfer.

When data is transferred, the software first sets the number of data transfers required for data transfer, the data write start address and the data transfer direction in the register of the DMAC1 in the system for the DMA transfer. To do. Next, the software makes a data transfer request to the DMA slave circuit 5. The register reading circuit 2 notifies the bus master circuit 3 of the number of data transfers, the data write start address, and the data transfer direction by the signal 52 set in the internal register of the bus master circuit 3. Next, the conventional DMA slave circuit 5 receives the data from the conventional DMA slave circuit 5 by the DMA transfer signal 59, and the bus master circuit 3 transfers the data to the local bus 21 by the signal 54 for transferring the data to the local bus 21.

An embodiment of the fourth invention is shown in FIG. In FIG. 4, the system bus 31 is a bus having a DMA I / O slave function by a DMA request signal 56 and a DMA acknowledge signal 57 connecting the intra-system DMAC 1 and the system bus 31. The contents of the register of the in-system DMAC1 can be read by the register read signals 51 and 58 of the in-system DMAC1. I / O
In the device 11, the register read circuit 2 is connected to the system bus 31 by the register read signal of the in-system DMAC1 and can read the in-system DMAC1 register. In addition, the register read circuit 2
Can write the contents of the register read from the in-system DMAC 1 to the bus master circuit 3 by a signal 52 for setting the register in the bus master 3. The bus master circuit 3 is connected to the DMA slave circuit 5 by a DMA transfer signal 59, and is also connected to the system bus 31 by a signal 54 for transferring data to the system bus 31. DMA
It is possible to receive data from the slave circuit 5 by the DMA transfer signal 59 and transfer the data through the system bus 31. The software sets the register of the DMAC in the system and requests the conventional DMA slave circuit 5 for data transfer.

When data is transferred, the software is transferred by the conventional DMA.
The number of data transfers required for data transfer, the data write start address, and the data transfer direction are set in the 1 register. Next, the software issues a data transfer request to the conventional DMA slave circuit 5. The register reading circuit 2 informs the bus master circuit 3 of the number of data transfers, the data write start address and the data transfer direction by the signal 52 set in the register in the bus master circuit. Next, the signal 53 received from the conventional DMA slave circuit 5 receives the data from the conventional DMA slave circuit 5, and the bus master circuit 3 receives the data from the system bus 31.
Transfer data to.

[0019]

The first invention has the following effects.

In a high-speed local bus that does not support DMA I / O slaves, high-speed bus master transfer is possible while maintaining the conventional software compatibility.

The second invention has the following effects.

In the system bus, high-speed bus master transfer is possible while maintaining the conventional software compatibility.

The third invention has the following effects.

In a high-speed local bus that does not support the DMA I / O slave, high-speed bus master transfer is possible while maintaining the conventional software compatibility, and the design period can be shortened.

The fourth invention has the following effects.

In the system bus, high-speed bus master transfer can be performed while maintaining the conventional software compatibility, and the design period can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

 1 In-system DMAC 2 Register reading circuit 3 Bus master circuit 4 I / O slave circuit 5 DMA slave circuit 21, 31 System bus

Claims (4)

[Claims] 1. A system having no DMA I / O slave function,
A system having at least a local bus having a bus master function, a means for reading an in-system direct memory access control (DMAC) register, and a bus master circuit, and transmitting the information from the means for reading the DMAC register to the bus master circuit From the system that was transferring data using the internal DMAC,
A data transfer method wherein the bus master transfers data to a local bus having a bus master function without having an MA I / O slave function. 2. A DMAC for performing a DMA transfer on the system bus, a system bus having a DMA I / O slave function, a means for reading an in-system DMAC register, and a bus master circuit. A data transfer system characterized in that the bus master circuit transfers data to a system bus from a system which has transferred data by using an in-system DMAC by transmitting information from a means for reading a register to the bus master circuit. . 3. A local bus having a bus master function without a DMA I / O slave function and a DM in the system
Means for reading AC register, bus master circuit, DM
A means for accessing the A-slave and transmitting information from the means for reading the DMAC register to the bus master circuit to use the in-system DMAC and transfer the data from the system to the local bus. A data transfer method in which a bus master circuit transfers data. 4. A DMAC for performing a DMA transfer on a system bus, a system bus having a DMA I / O slave function, a means for reading an in-system DMAC register, a bus master circuit, and means for accessing a DMA slave. By transmitting the information from the means for reading the DMAC register to the bus master circuit, the bus master circuit of the system bus transfers the data from the system that was transferring the data using the in-system DMAC. A data transfer method characterized in that