JPH07169939A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07169939A JPH07169939A JP6292457A JP29245794A JPH07169939A JP H07169939 A JPH07169939 A JP H07169939A JP 6292457 A JP6292457 A JP 6292457A JP 29245794 A JP29245794 A JP 29245794A JP H07169939 A JPH07169939 A JP H07169939A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- base
- emitter
- semiconductor substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000605 extraction Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】
【目的】引出電極のアルミニウム成分が酸化膜に拡散す
ることに基づく、引出電極と半導体基板との間の酸化膜
の耐圧低下を防止できる半導体装置を提供する。
【構成】半導体基板１に表面の一部から内部に向けてベ
ース２，エミッタ３が形成され、半導体基板１の表面に
ベース２，エミッタ３を含む範囲で酸化膜４が形成さ
れ、酸化膜４に開けられたコンタクトホールを介してベ
ース２，エミッタ３とそれぞれ接続するアルミニウムか
ら成る引出電極がベース２，エミッタ３の形成範囲外に
わたって形成されている。酸化膜４と引出電極５，６と
の間には、ベース２，エミッタ３の形成範囲外で引出電
極５，６の形成範囲から一部はみ出すようにポリシリコ
ンの層７が介在する。
(57) [Abstract] [PROBLEMS] To provide a semiconductor device capable of preventing a decrease in withstand voltage of an oxide film between an extraction electrode and a semiconductor substrate due to diffusion of an aluminum component of the extraction electrode into an oxide film. A base 2 and an emitter 3 are formed from a part of the surface of the semiconductor substrate 1 toward the inside, and an oxide film 4 is formed on the surface of the semiconductor substrate 1 in a range including the base 2 and the emitter 3. An extraction electrode made of aluminum, which is connected to each of the base 2 and the emitter 3 through a contact hole opened in, is formed outside the formation range of the base 2 and the emitter 3. A polysilicon layer 7 is interposed between the oxide film 4 and the extraction electrodes 5 and 6 so as to partially protrude from the formation range of the extraction electrodes 5 and 6 outside the formation range of the base 2 and the emitter 3.
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関するもの
であり、更に詳しくは半導体基板の表面の一部から内部
に向けてベース領域及びエミッタ領域を形成して成るト
ランジスタ等の半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a transistor in which a base region and an emitter region are formed from a part of the surface of a semiconductor substrate toward the inside. is there.
【０００２】[0002]
【従来の技術】半導体装置、例えばトランジスタでは、
半導体基板の表面にベースを、またそのベースの表面に
エミッタをそれぞれ拡散によって形成してから、これら
の各伝導型領域を含む前記半導体基板の表面を酸化膜で
覆い、更にこの酸化膜に開けられたコンタクトホールを
介してアルミニウムのような電極をベース，エミッタの
各伝導型領域に接続するとともに、前記酸化膜の表面に
まで延長して引出電極とする構成はよく知られている。2. Description of the Related Art In semiconductor devices such as transistors,
A base is formed on the surface of the semiconductor substrate, and an emitter is formed on the surface of the base by diffusion. Then, the surface of the semiconductor substrate including each of these conductivity type regions is covered with an oxide film, and the oxide film is further opened. It is well known that an electrode such as aluminum is connected to each conductive type region of the base and the emitter through the contact hole, and is extended to the surface of the oxide film to form the extraction electrode.
【０００３】図２は上記した従来のＮＰＮトランジスタ
を示し、１は基板、２はベース、３はエミッタ、４は酸
化シリコンのような酸化膜、５，６は酸化膜４に開けら
れたコンタクトホールを介してベース２，エミッタ３に
接続されたアルミニウムから成る引出用の電極である。FIG. 2 shows the above-mentioned conventional NPN transistor, 1 is a substrate, 2 is a base, 3 is an emitter, 4 is an oxide film such as silicon oxide, and 5 and 6 are contact holes formed in the oxide film 4. It is an electrode for extraction which is made of aluminum and is connected to the base 2 and the emitter 3 via.
【０００４】[0004]
【発明が解決しようとする課題】しかし、このような構
成によると、電極５，６を形成した後でもトランジスタ
として完成するまでに種々の熱が加えられることがあ
り、更にはトランジスタの使用中でも自己発熱又は外部
からの熱を受けて電極５，６のアルミニウム成分が酸化
膜４内に拡散しやすくなる。この拡散によって酸化膜は
次第に導電性を帯びることになるので、等価的に酸化膜
が次第に薄くなったことになり、これが電極とシリコン
(つまり、半導体基板)との間の酸化膜の耐圧低下の原因
となる。However, according to such a structure, various kinds of heat may be applied before the transistor is completed even after the electrodes 5 and 6 are formed. The aluminum component of the electrodes 5 and 6 is likely to diffuse into the oxide film 4 due to heat generation or heat from the outside. The oxide film gradually becomes conductive due to this diffusion, so that the oxide film becomes equivalently thinner and thinner.
(That is, the breakdown voltage of the oxide film between itself and the semiconductor substrate) is reduced.
【０００５】また、上記耐圧低下を防止するのに、引出
電極５，６と酸化膜４との間にポリシリコンの層を形成
することが考えられるが、形成されたこの層のエッチン
グを引出電極をマスクとして行うと、その際、いわゆる
サイドエッチ(アンダーカット)現象が発生し、ポリシリ
コンの層はサイドエッチの分だけ引出電極５，６よりも
小さくなる。そのため、エレクトロマイグレーションに
よって引出電極５，６のアルミニウム成分が、ポリシリ
コンの層の端面伝わって酸化膜に達することがある。こ
のような状態が発生すると、先に述べたようにアルミニ
ウム成分が酸化膜４に拡散してしまい、引出電極５，６
と半導体基板１との間の酸化膜４の耐圧が低下してしま
うようになる。In order to prevent the breakdown voltage from being lowered, it is conceivable to form a polysilicon layer between the extraction electrodes 5 and 6 and the oxide film 4, but etching of the formed layer is performed to extract the extraction electrode. When this is used as a mask, a so-called side etching (undercut) phenomenon occurs at that time, and the polysilicon layer becomes smaller than the extraction electrodes 5 and 6 by the side etching. Therefore, the aluminum component of the extraction electrodes 5 and 6 may reach the oxide film along the end surface of the polysilicon layer by electromigration. When such a state occurs, the aluminum component diffuses into the oxide film 4 as described above, and the extraction electrodes 5, 6
Thus, the breakdown voltage of the oxide film 4 between the semiconductor substrate 1 and the semiconductor substrate 1 is reduced.
【０００６】本発明は上記のような点に鑑みてなされた
ものであって、引出電極を構成しているアルミニウム成
分の酸化膜への拡散に基づく、引出電極と半導体基板と
の間の酸化膜の耐圧低下を防止できる半導体装置を提供
することを目的とする。The present invention has been made in view of the above points, and is based on the diffusion of the aluminum component forming the extraction electrode into the oxide film, and the oxide film between the extraction electrode and the semiconductor substrate. It is an object of the present invention to provide a semiconductor device capable of preventing a decrease in withstand voltage.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体装置は、半導体基板の表面に形
成されたベース領域、前記ベース領域内に形成されたエ
ミッタ領域、前記ベース及びエミッタ領域を含む前記半
導体基板の表面に形成された酸化膜、前記酸化膜にあけ
られたコンタクトホールを介して前記ベース及びエミッ
タ領域に連なるアルミニウムから成る引出電極を前記ベ
ース及びエミッタ領域の形成領域以外の前記半導体基板
の表面上に亘って形成した半導体装置において、前記引
出電極のアルミニウム成分が前記酸化膜に拡散するのを
防止するためのポリシリコンの膜を前記酸化膜と引出電
極との間に、前記ベース領域及びエミッタ領域の形成範
囲外まで形成し前記形成範囲外で前記引出電極の形成範
囲から一部はみ出すように介在させたことを特徴とす
る。In order to achieve the above object, a semiconductor device according to the present invention comprises a base region formed on the surface of a semiconductor substrate, an emitter region formed in the base region, the base and the emitter. An oxide film formed on the surface of the semiconductor substrate including a region, and an extraction electrode made of aluminum connected to the base and emitter regions through a contact hole formed in the oxide film, except for the region where the base and emitter regions are formed. In the semiconductor device formed over the surface of the semiconductor substrate, a polysilicon film for preventing the aluminum component of the extraction electrode from diffusing into the oxide film, between the oxide film and the extraction electrode, It is formed outside the formation range of the base region and the emitter region, and partly protrudes from the formation range of the extraction electrode outside the formation range. Characterized in that by Uni interposed.
【０００８】[0008]
【作用】本発明の構成によると、ポリシリコンの層が、
酸化膜と引出電極との間にベース領域及びエミッタ領域
の形成範囲外で介在しているため、引出電極を構成して
いるアルミニウム成分の酸化膜への拡散が阻止される。
また、このポリシリコンの層はベース領域及びエミッタ
領域の形成範囲外で引出電極の形成範囲から一部はみ出
すように介在しているため、例えば、ポリシリコンの層
をエッチングしたとしても、ポリシリコンの層がサイド
エッチによって引出電極よりも小さくなることは避けら
れ、その結果、エレクトロマイグレーションに起因する
前記アルミニウム成分の酸化膜への拡散が阻止される。
従って、ベース領域及びエミッタ領域の形成範囲外での
引出電極と半導体基板との間の酸化膜の耐圧が向上す
る。According to the structure of the present invention, the polysilicon layer is
Since it is interposed between the oxide film and the extraction electrode outside the formation region of the base region and the emitter region, diffusion of the aluminum component forming the extraction electrode into the oxide film is prevented.
Further, since this polysilicon layer is interposed so as to partially protrude from the formation region of the extraction electrode outside the formation region of the base region and the emitter region, for example, even if the polysilicon layer is etched, It is avoided that the layer becomes smaller than the extraction electrode due to side etching, and as a result, diffusion of the aluminum component into the oxide film due to electromigration is prevented.
Therefore, the breakdown voltage of the oxide film between the extraction electrode and the semiconductor substrate outside the range where the base region and the emitter region are formed is improved.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面を参照しつつ説
明する。なお、図１中、図２と同じ符号を付した部分は
同一又は対応する部分を示す。Embodiments of the present invention will be described below with reference to the drawings. In addition, in FIG. 1, the parts given the same reference numerals as those in FIG. 2 indicate the same or corresponding parts.
【００１０】図１に示すように、本実施例の半導体装置
では、従来例(図２)と同様、半導体基板１に表面の一部
から内部に向けてベース２，エミッタ３が形成され、半
導体基板１の表面にベース２，エミッタ３を含む範囲で
酸化膜４が形成され、酸化膜４に開けられたコンタクト
ホールを介してベース２，エミッタ３とそれぞれ接続す
るアルミニウムから成る引出電極がベース２，エミッタ
３の形成範囲外にわたって形成されている。As shown in FIG. 1, in the semiconductor device of this embodiment, as in the conventional example (FIG. 2), a base 2 and an emitter 3 are formed on a semiconductor substrate 1 from a part of the surface toward the inside. An oxide film 4 is formed on the surface of the substrate 1 in a range including the base 2 and the emitter 3, and an extraction electrode made of aluminum is connected to the base 2 and the emitter 3 via a contact hole formed in the oxide film 4. , The emitter 3 is formed outside the forming range.
【００１１】そして、本実施例の特徴は、酸化膜４と引
出電極５，６との間には、ベース２，エミッタ３の形成
範囲外で引出電極５，６の形成範囲から一部はみ出すよ
うにポリシリコンの層(即ち、引出電極５，６を構成し
ているアルミニウムよりも不活性のポリシリコンから成
る層)７が介在する点にある。この層７は、前記のよう
に酸化膜４の形成後、その表面の引出電極５，６の形成
箇所に酸化膜４を覆うように形成され、その後、この層
７の表面に引出電極５，６が蒸着等によって形成され
る。なお、層７の形成は気相成長法によるとよい。ま
た、層７としてはこれがドープドポリシリコン或いはノ
ンドープドポリシリコンであってもよい。The feature of this embodiment is that the oxide film 4 and the extraction electrodes 5 and 6 are partially protruded from the formation range of the extraction electrodes 5 and 6 outside the formation range of the base 2 and the emitter 3. There is an intervening polysilicon layer (that is, a layer made of polysilicon more inactive than aluminum constituting the extraction electrodes 5 and 6). After the oxide film 4 is formed as described above, the layer 7 is formed so as to cover the oxide film 4 on the surface where the extraction electrodes 5, 6 are formed, and thereafter, the extraction electrode 5, 5 is formed on the surface of the layer 7. 6 is formed by vapor deposition or the like. The layer 7 may be formed by a vapor phase growth method. Further, the layer 7 may be doped polysilicon or non-doped polysilicon.
【００１２】本実施例の構成によると、ポリシリコンの
層７が、酸化膜４と引出電極５，６との間にベース２及
びエミッタ３の領域の形成範囲外で介在しているため、
引出電極５，６を構成しているアルミニウム成分の酸化
膜４への拡散が阻止される。また、このポリシリコンの
層７はベース２及びエミッタ３の領域の形成範囲外で引
出電極５，６の形成範囲から一部はみ出すように介在し
ているため、例えば、前述したようにポリシリコンの層
７をエッチングした場合でも、層７がサイドエッチによ
って引出電極５，６よりも小さくなることは避けられ、
その結果、エレクトロマイグレーションに起因する前記
アルミニウム成分の酸化膜４への拡散が阻止される。According to the structure of this embodiment, the polysilicon layer 7 is interposed between the oxide film 4 and the extraction electrodes 5 and 6 outside the region where the base 2 and the emitter 3 are formed.
Diffusion of the aluminum component forming the extraction electrodes 5 and 6 into the oxide film 4 is prevented. Further, since the polysilicon layer 7 is interposed so as to partially protrude from the formation range of the extraction electrodes 5 and 6 outside the formation range of the regions of the base 2 and the emitter 3, for example, as described above, the polysilicon layer 7 is formed. Even when the layer 7 is etched, it is avoided that the layer 7 becomes smaller than the extraction electrodes 5 and 6 due to side etching.
As a result, diffusion of the aluminum component into the oxide film 4 due to electromigration is prevented.
【００１３】一方、ベース２及びエミッタ３の形成範囲
外の半導体基板１の部分には、ベース２やエミッタ３の
領域に比べて比較にならないほど大きな電圧が印加され
るため、引出電極５，６と半導体基板１との間の酸化膜
４の耐圧のうちバイポーラトランジスタにおいてその低
下が問題となるのは、ベース２及びエミッタ３の領域の
形成範囲外における、引出電極５，６と半導体基板１と
の間の酸化膜４の耐圧である。On the other hand, since an incomparably large voltage is applied to the portion of the semiconductor substrate 1 outside the formation range of the base 2 and the emitter 3 as compared with the region of the base 2 and the emitter 3, the extraction electrodes 5, 6 are formed. The decrease in the breakdown voltage of the oxide film 4 between the semiconductor substrate 1 and the semiconductor substrate 1 is a problem in the bipolar transistor because the extraction electrodes 5, 6 and the semiconductor substrate 1 outside the formation range of the regions of the base 2 and the emitter 3. Is the breakdown voltage of the oxide film 4 between the two.
【００１４】従って、上記したように前記アルミニウム
成分の酸化膜４への拡散が阻止されることによって、ベ
ース２及びエミッタ３の領域の形成範囲外での引出電極
５，６と半導体基板１との間の酸化膜４の耐圧が向上す
る結果、引出電極５，６を構成しているアルミニウム成
分の酸化膜４への拡散に基づく、引出電極５，６と半導
体基板１との間の酸化膜４の耐圧低下を防止することが
できる。Therefore, as described above, the diffusion of the aluminum component into the oxide film 4 is blocked, so that the extraction electrodes 5, 6 and the semiconductor substrate 1 are formed outside the region where the base 2 and the emitter 3 are formed. As a result of the improvement in the breakdown voltage of the oxide film 4 between them, the oxide film 4 between the extraction electrodes 5, 6 and the semiconductor substrate 1 is based on the diffusion of the aluminum component forming the extraction electrodes 5, 6 into the oxide film 4. It is possible to prevent the breakdown voltage from decreasing.
【００１５】また、前述したようにエッチングによって
層７が引出電極５，６よりも小さくなると、引出電極
５，６と酸化膜４との間で放電現象が発生しやすくなる
が、層７のはみ出した部分７Ａの存在によって、そのよ
うな状態となることを避けることができる。従って、引
出電極５，６と酸化膜４との間で放電現象が発生するの
を防止することができる。When the layer 7 becomes smaller than the extraction electrodes 5 and 6 by etching as described above, a discharge phenomenon is likely to occur between the extraction electrodes 5 and 6 and the oxide film 4, but the layer 7 protrudes. Due to the presence of the portion 7A, it is possible to avoid such a state. Therefore, it is possible to prevent a discharge phenomenon from occurring between the extraction electrodes 5 and 6 and the oxide film 4.
【００１６】本発明者の実験によれば、層７を設けない
場合に耐圧が４００Ｖであったトランジスタにおいて、
層７として厚さ３０００オングストロームのポリシリコ
ンを介在させたところ、耐圧が５００Ｖ〜６００Ｖに向
上したことが確かめられている。According to an experiment conducted by the present inventor, in a transistor having a breakdown voltage of 400 V when the layer 7 is not provided,
It has been confirmed that the withstand voltage is improved to 500 V to 600 V by interposing polysilicon having a thickness of 3000 Å as the layer 7.
【００１７】[0017]
【発明の効果】以上説明した通り本発明に係る半導体装
置によれば、ポリシリコンの層を前述のように介在させ
るだけの簡単な構成で、引出電極を構成しているアルミ
ニウム成分の酸化膜への拡散に基づく、引出電極と半導
体基板との間の酸化膜の耐圧低下を防止することができ
る。さらに、ポリシリコンの層をエッチングした場合で
も、その層が引出電極よりも小さくなることは避けられ
るため、引出電極と酸化膜との間で放電現象が発生する
のを防止することができる。As described above, according to the semiconductor device of the present invention, the oxide film of the aluminum component forming the extraction electrode can be formed with the simple structure in which the polysilicon layer is interposed as described above. It is possible to prevent the breakdown voltage of the oxide film between the extraction electrode and the semiconductor substrate from being lowered due to the diffusion of the oxide. Further, even when the polysilicon layer is etched, it is possible to prevent the layer from becoming smaller than the extraction electrode, so that it is possible to prevent a discharge phenomenon from occurring between the extraction electrode and the oxide film.
【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】従来例を示す断面図。FIG. 2 is a sectional view showing a conventional example.
１ …半導体基板 ２ …ベース ３ …エミッタ ４ …酸化膜 ５，６ …引出電極 ７ …層 ７Ａ …はみ出した部分 1 ... Semiconductor substrate 2 ... Base 3 ... Emitter 4 ... Oxide film 5, 6 ... Extraction electrode 7 ... Layer 7A ... Projection part
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/73 Ｈ０１Ｌ 29/72 Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 29/73 H01L 29/72
Claims (1)
域、前記ベース領域内に形成されたエミッタ領域、前記
ベース及びエミッタ領域を含む前記半導体基板の表面に
形成された酸化膜、前記酸化膜にあけられたコンタクト
ホールを介して前記ベース及びエミッタ領域に連なるア
ルミニウムから成る引出電極を前記ベース及びエミッタ
領域の形成領域以外の前記半導体基板の表面上に亘って
形成した半導体装置において、 前記引出電極のアルミニウム成分が前記酸化膜に拡散す
るのを防止するためのポリシリコンの膜を前記酸化膜と
引出電極との間に、前記ベース領域及びエミッタ領域の
形成範囲外まで形成し前記形成範囲外で前記引出電極の
形成範囲から一部はみ出すように介在させたことを特徴
とする半導体装置。1. A base region formed on the surface of a semiconductor substrate, an emitter region formed in the base region, an oxide film formed on the surface of the semiconductor substrate including the base and the emitter region, and an oxide film formed on the oxide film. In a semiconductor device in which an extraction electrode made of aluminum and connected to the base and emitter regions through an opened contact hole is formed over the surface of the semiconductor substrate other than the region where the base and emitter regions are formed, A polysilicon film for preventing an aluminum component from diffusing into the oxide film is formed between the oxide film and the extraction electrode up to the formation range of the base region and the emitter region, and outside the formation range. A semiconductor device characterized in that it is interposed so as to partly protrude from the formation area of the extraction electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292457A JPH07169939A (en) | 1994-11-28 | 1994-11-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292457A JPH07169939A (en) | 1994-11-28 | 1994-11-28 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59041034A Division JPS60183769A (en) | 1984-03-02 | 1984-03-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07169939A true JPH07169939A (en) | 1995-07-04 |
Family
ID=17782055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6292457A Pending JPH07169939A (en) | 1994-11-28 | 1994-11-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07169939A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999052131A1 (en) * | 1998-04-03 | 1999-10-14 | Zetex Plc | Semiconductor contact fabrication method |
| GB2341278A (en) * | 1998-04-03 | 2000-03-08 | Zetex Plc | Semiconductor contact fabrication method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5289467A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Semiconductor device |
| JPS5623299A (en) * | 1979-07-31 | 1981-03-05 | Toyo Sash Kk | Electrolytic coloring method of aluminum or its alloy |
-
1994
- 1994-11-28 JP JP6292457A patent/JPH07169939A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5289467A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Semiconductor device |
| JPS5623299A (en) * | 1979-07-31 | 1981-03-05 | Toyo Sash Kk | Electrolytic coloring method of aluminum or its alloy |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999052131A1 (en) * | 1998-04-03 | 1999-10-14 | Zetex Plc | Semiconductor contact fabrication method |
| GB2341278A (en) * | 1998-04-03 | 2000-03-08 | Zetex Plc | Semiconductor contact fabrication method |
| GB2341278B (en) * | 1998-04-03 | 2003-06-25 | Zetex Plc | Semiconductor fabrication method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0253944B2 (en) | ||
| US5204276A (en) | Method of manufacturing semiconductor device | |
| US5702979A (en) | Method of forming a landing pad structure in an integrated circuit | |
| US6855999B2 (en) | Schottky diode having a shallow trench contact structure for preventing junction leakage | |
| JPS6153867B2 (en) | ||
| US4732872A (en) | Method for making a bipolar transistor and capacitors using doped polycrystalline silicon or metal silicide | |
| US4980738A (en) | Single polysilicon layer transistor with reduced emitter and base resistance | |
| JPH0521793A (en) | Semiconductor device and manufacturing method thereof | |
| US6087708A (en) | Semiconductor integrated circuit device and a method of producing the same | |
| US5591651A (en) | Method of making a bipolar stripe transistor structure | |
| JPH03203261A (en) | Semiconductor device | |
| JPH0936307A (en) | MOS capacitor | |
| JPH07169939A (en) | Semiconductor device | |
| JP3311759B2 (en) | Integrated circuit having screen structure and method of manufacturing the same | |
| JPH07245400A (en) | Field-effect transistor and manufacturing method thereof | |
| US6642606B1 (en) | Method for producing siliconized polysilicon contacts in integrated semiconductor structures | |
| JPH0878433A (en) | Semiconductor device | |
| JPH0316177A (en) | Semiconductor device | |
| JPS641064B2 (en) | ||
| JP2663956B2 (en) | Method for manufacturing semiconductor device | |
| KR100196217B1 (en) | Forming method for plug | |
| JP3340809B2 (en) | Vertical semiconductor device and method of manufacturing the same | |
| JP3194303B2 (en) | Semiconductor device | |
| JP2789998B2 (en) | Semiconductor device | |
| JPH0376023B2 (en) |