JPH07162673A - Resolution converter for picture signal - Google Patents

Abstract

PURPOSE:To convert resolution at a high speed by providing a shift register and a digital adder and defining the high-order (n)-bit output of the digital adder as output digital picture signals. CONSTITUTION:Digital signals are supplied to the D terminal of a DFF 24 and the Q output of the DFF 24 is supplied to the D terminal of the DFF 25 and is similarly supplied to the DFFs 21 and 22 as well. The output of the digital adder 26 becomes the average value (A+B)/2 of the Q output of the DFFs 24 and 25 and the digital adder 23 becomes the average value (C+D)/2 of the Q output of the DFFs 24 and 25. Further, the average value (A+B+C+D)/4 of the output of the adders 26 and 23 is obtained for the output of the digital adders. Thus, the average value of four adjacent data is continuously outputted while being shifted by each data and by thinning out the required data in a CPU, resolution conversion for not generating an unnatural feeding generated because the data are omitted is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal resolution conversion apparatus which is optimum for converting the resolution of an image signal read by an image scanner or the like.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration example of a signal input section of a conventional image input device. In FIG. 5, the input image light beam reaching the line CCD 11 from the original by transmission or reflection is
It is photoelectrically converted by the line CCD 11 into an electric (analog) signal. After that, it is digitally encoded by the A / D converter 12, and is buffer 13 (FIFO memory).
Is temporarily stored in. The image signal accumulated in the buffer 13 is taken into the memory 14 via the bus line 16. The loading into the memory 14 is performed according to an instruction from the CPU 15.

In such a system, the line CCD 11
When all of the data (image signal) output from the device is used, the image signal has the highest resolution, but when the resolution lower than the highest resolution is obtained, the image signal output from the line CCD 11 is thinned out. . An example of this thinning is shown in FIG. FIG. 6 shows an example of 1/4 resolution conversion. As shown in FIG. 6, by using the data (image signal) output from the line CCD 11 once in four times, a resolution of ¼ of the maximum resolution is realized.
That is, the thinning-out is performed by using the 1 + 4nth (n is an integer) data (image signal) of the pixel numbers in the figure. Not shown, but half the maximum resolution
In order to realize the resolution of 1), similarly, 1 + 2n (n is an integer) th data (image signal) in the pixel number in the figure.
Thinning is done by using.

[0004]

In the conventional simple thinning-out shown in FIG. 6, there is a problem that the input image light beam taken into the CCD pixel which is thinned out is not reflected as an output at all. That is, although there are four slit lights a, b, c, and d (see FIG. 6) in the input pixel, the data after thinning out is the data corresponding to the slit lights a, c, and d. Since (image signal) is lost, there is a drawback that only an image signal that is uncomfortable compared to the input image light beam can be obtained.

The present invention has been made in view of such a situation. Even when the resolution is lowered, the loss of the input image data is eliminated, and the processing by hardware is realized to realize high-speed (real-time) resolution. The purpose is to perform the conversion of.

[0006]

In order to achieve the above object, the first aspect of the present invention is to provide n shift registers (21) connected in parallel to shift an n (n is an integer) bit input digital image signal by two stages. , 22) and an n-bit output of two adjacent stages of the shift register are added to the digital adder (23).
And the upper n-bit output of the digital adder is used as an output digital image signal.

According to a second aspect of the present invention, n shift registers (24, 25, 21, 22) connected in parallel for shifting an input digital image signal of n bits (n is an integer) by four stages are adjacent to each other. Add 2 stages of n-bit output 2
First digital adders (26, 23) and adjacent 2
A second digital adder (27) for adding the n-bit outputs of the two first digital adders, the upper n-bit output of the second digital adder being the output digital image signal. ing.

A third aspect of the present invention is an n-number of shift registers (24, 25, 21, 2) connected in parallel to shift an input digital image signal of n (n is an integer) bits by m (m is an integer) stages.
2) and m / 2 first digital adders (26, 2) for adding n-bit outputs of adjacent two stages of the shift register.
3) and m / 4 second digital adders for adding n-bit outputs of two adjacent first digital adders, ...
And one log ₂ m digital adder (27) for adding the n-bit outputs of two adjacent m-th adders, and outputs the upper n-bit output of the log ₂ m digital adder It is configured to be an image signal.

[0009]

In the image signal resolution conversion apparatus having the above structure, the shift register (D flip-flops arranged in series) and the digital adder are used to average adjacent data according to the resolution. Even when the resolution is lowered, the loss of the input image data can be eliminated, and the resolution can be converted at high speed (real time) by implementing the processing by hardware.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block connection diagram showing an embodiment of an image signal resolution converting apparatus according to the present invention.

In FIG. 1, the input image light beam which has reached the line CCD 1 by transmission or reflection from the original is a line C.
The signal is photoelectrically converted by the CD 1 to become an electric (analog) signal. Then, it is digitally encoded by the A / D converter 2 and supplied to the averaging processing circuit 3. The averaging processing circuit 3 will be described later with reference to FIGS. 3 and 4. The image signal averaged by the averaging processing circuit 3 is temporarily stored in the buffer 4. The image signal accumulated in the buffer 4 is taken into the memory 5 via the bus line 7. The loading into the memory 5 is performed according to an instruction from the CPU 6.

The averaging processing circuit 3 includes an A / D converter 2
This is a circuit that continues to output the average of several adjacent pixels of the output data to the next stage (buffer 4) by the hardware logic, and FIG. 2 shows an example of the output signal. Also, FIG.
FIG. 4 shows a block connection diagram. 3 shows an averaging processing circuit 3a that outputs an average value of 2 data (2 pixels), and FIG. 4 shows an averaging processing circuit 3b that outputs an average value of 4 data (4 pixels).

Referring to FIG. 3, the A / D converter 2 shown in FIG.
The digital signal output from the D flip-flop 2
1 is supplied to the D terminal. Q of the D flip-flop 21
The output is supplied to the D terminal of the D flip-flop 22. The D flip-flop 21 is the D flip-flop 2
A shift register that performs two-stage shift in cooperation with 2 is configured. Therefore, a common sample clock is supplied to the D flip-flop 21 and the D flip-flop 22.

Eight D-flip-flops 21 and 22 shown in FIG. 3 are connected in parallel in order to shift an 8-bit input digital image signal by two stages. Individual D flip-flops 2 connected in parallel
The Q output of 1 is supplied to the D terminal of the D flip-flop 22, respectively. Due to this connection relationship, the Q output of the D flip-flop 21 (8 bits connected in parallel),
The Q output (8 bits connected in parallel) of the D flip-flop 22 has two adjacent eight stages shifted by one sample clock.
Bit output.

The Q output (8 bits connected in parallel) of the D flip-flop 21 is supplied to the A terminal of the digital adder 23. The Q output of the D flip-flop 22 (8 bits connected in parallel) is supplied to the B terminal of the digital adder 23. The output of the digital adder 23 is 9 bits including the overflow carry, and the upper 8 bits of this are used as the output of the averaging processing circuit 3a.
The Z0 terminal of the digital adder 23 is the least significant bit.

The upper 8 bits are the average value of the Q output of the D flip-flop 21 (8 bits connected in parallel) and the Q output of the D flip-flop 22 (8 bits connected in parallel). Will be described below.

For example, the Q output (8 bits connected in parallel) of the D flip-flop 21 is represented in binary,

01100100 (100), and the Q output (8 bits connected in parallel) of the D flip-flop 22 is in binary notation,

Assuming 11111000 (248), the added value of both is

01100100

+11111000

Since 101011100 is the output of the upper 8 bits, the output of the averaging processing circuit 3a is

It becomes 10101110 (174). That is, the Q output of the D flip-flop 21 (8 bits connected in parallel) and the Q output of the D flip-flop 22.
It is the average value with the output (8 bits connected in parallel). Note that the values in parentheses are decimal display values provided for reference.

The averaging processing circuit 3a shown in FIG. 3 continues to output the average of two adjacent data, shifted by one data at a time. By thinning out the necessary data in the CPU 6,
It is possible to realize resolution conversion that does not cause a feeling of strangeness caused by the loss of data (image signal). In addition,
When the 2-data average is used, it is possible to support a resolution up to ½ of the maximum resolution.

FIG. 4 shows an averaging processing circuit 3b which outputs an average value of 4 data (4 pixels). In FIG. 4, the digital signal (see FIG. 2C) output from the A / D converter 2 in FIG. 1 is supplied to the D terminal of the D flip-flop 24. The Q output of the D flip-flop 24 is supplied to the D terminal of the D flip-flop 25. Further, the Q output of the D flip-flop 25 is supplied to the D terminal of the D flip-flop 21. The Q output of the D flip-flop 21 is supplied to the D terminal of the D flip-flop 22.

The D flip-flop 24, the D flip-flop 25, the D flip-flop 21 and the D flip-flop 22 constitute a shift register for performing a 4-stage shift as a whole. For that purpose, the D flip-flop 24,
A common sample clock is supplied to 25, 21, and 22.

The D flip-flops 24 and 2 shown in FIG.
In order to shift the 8-bit input digital image signal by 4 stages, 8 units 5, 21, and 22 are connected in parallel. The Q outputs of the individual D flip-flops 24, 25, and 21 connected in parallel are supplied to the D terminals of the D flip-flops 25, 21, and 22 in the next stage, respectively. Due to this connection relationship, the Q outputs (8 bits connected in parallel) of the D flip-flops 24, 25, 21, and 22 become adjacent 8-stage 8-bit outputs that are shifted by 1 sample clock each.

The Q output of the D flip-flop 24 (8 bits connected in parallel) is supplied to the A terminal of the digital adder 26. Further, the Q output (8 bits connected in parallel) of the D flip-flop 25 is supplied to the B terminal of the digital adder 26. The output of the digital adder 26 is 9 bits including the overflow carry, and the upper 8 bits of this are supplied to the E terminal of the digital adder 26.

The Q output (8 bits connected in parallel) of the D flip-flop 21 is supplied to the A terminal of the digital adder 23. The Q output of the D flip-flop 22 (8 bits connected in parallel) is supplied to the B terminal of the digital adder 23. The output of the digital adder 23 is 9 bits including the overflow carry, and the upper 8 bits of this are supplied to the F terminal of the digital adder 27.

The output of the digital adder 27 is 9 bits including the overflow carry. Of these, the upper 8 bits are the output of the averaging processing circuit 3b (see FIG. 2 (d)). The Z0 terminal of the digital adder 27 is
It is the least significant bit.

In the circuit shown in FIG. 4, the output of the digital adder 26 is the average value of the Q output of the D flip-flop 24 and the Q output of the D flip-flop 25 ((A + B) /
2). The output of the digital adder 23 is the average value ((C + D) / 2) of the Q output of the D flip-flop 21 and the Q output of the D flip-flop 22. Further, the output of the digital adder 27 is the average value ((E + F) / 2) of the outputs of the digital adder 26 and the digital adder 23. Therefore, as the output of the digital adder 27, the D flip-flops 24, 2
Average Q output of 5, 21, and 22 ((A + B + C
+ D) / 4) is obtained.

In the circuit of FIG. 4, the average of four adjacent data continues to be output with a shift of one data at a time. Data (image signal) by thinning out necessary data in the CPU 6
It is possible to realize resolution conversion that does not cause a sense of discomfort that occurs due to the lack of. It should be noted that when the 4-data average is used, it is possible to support a resolution up to 1/4 of the maximum resolution. High-speed processing (real-time processing) is possible by repeating the same circuit for resolutions of 4 data averages or less.

By providing a switch circuit for selecting, it is possible to realize a plurality of resolution conversions by the same device. For example, the circuit shown in FIG.
By including the averaging processing circuit 3a shown in (1) inside and controlling the operation / non-operation of the digital adder 26 by the CPU 6, it is possible to switch between 4 data averaging and 2 data averaging.

As described above with reference to the embodiments, the resolution conversion device for an image signal according to the present invention has a demerit that the circuit size becomes larger as the resolution becomes lower. So CP
It can be considered to be used in combination with U treatment. The lower the resolution, the smaller the amount of data to be processed within the same time. That is, the data output performance of the entire device does not change even if the processing is performed slowly. Actually required resolution and CP
Considering the U capability and the like, an inexpensive device with high total performance can be realized.

Further, the present invention is also characterized in that the aperture size of the CCD can be controlled by calculation (average) as described above, and the following moire suppressing effect can be expected. The cause of moiré is recognized as moire due to the generation of undulations in shades due to a slight shift between the density frequency of the input image and the sampling frequency. In the image signal resolution conversion apparatus according to the present invention, since the density frequency of the input image and the sampling frequency do not shift, it is possible to avoid the occurrence of moire by changing the aperture size (sampling frequency).

[0037]

As described above, according to the present invention, the shift register and the digital adder are used to average the adjacent data according to the resolution. Therefore, even when the resolution is lowered, the input image data It becomes possible to perform resolution conversion at high speed (real time) by eliminating the omissions and realizing the processing by hardware.

[Brief description of drawings]

FIG. 1 is a block connection diagram showing an embodiment of an image signal resolution conversion apparatus according to the present invention.

FIG. 2 is a waveform diagram illustrating the operation of an embodiment of the image signal resolution conversion apparatus according to the present invention.

FIG. 3 is a block connection diagram showing an embodiment of an image signal resolution conversion apparatus according to the present invention.

FIG. 4 is a block connection diagram showing an embodiment of an image signal resolution conversion apparatus according to the present invention.

FIG. 5 is a block connection diagram showing an example of a conventional image signal resolution conversion apparatus.

FIG. 6 is a waveform diagram illustrating an operation of an example of a conventional image signal resolution conversion apparatus.

[Explanation of symbols]

 1 line CCD 3 averaging processing circuit 3a averaging processing circuit 3b averaging processing circuit 4 buffer 5 memory 6 CPU 7 bus line 21 D flip-flop 22 D flip-flop 23 digital adder 24 D flip-flop 25 D flip-flop 26 digital addition Unit 27 Digital adder

Claims (3)

[Claims] 1. An n number of shift registers connected in parallel for shifting an n (n is an integer) bit input digital image signal by two stages, and a digital addition for adding n-bit outputs of adjacent two stages of the shift register. And a high-order n-bit output of the digital adder as an output digital image signal. 2. An n number of shift registers connected in parallel that shifts an n (n is an integer) bit input digital image signal by four stages, and two shift registers that add n-bit outputs of adjacent two stages of the shift register. And a single second digital adder for adding the n-bit outputs of two adjacent first digital adders, the upper n-bit output of the second digital adder being An image signal resolution conversion device, which is an output digital image signal. 3. An n number of shift registers connected in parallel for shifting an n (n is an integer) bit input digital image signal by m (m is an integer) stages, and an n-bit output of two adjacent stages of the shift register. M / 2 first digital adders for adding n, m / 4 second digital adders for adding n-bit outputs of two adjacent first digital adders, and two adjacent two A log ₂ m digital adder for adding the n-bit output of the m / 2-th digital adder, and the upper n-bit output of the log ₂ m digital adder is used as an output digital image signal. An image signal resolution converter characterized by the above.