JPH07162005A - Semiconductor integrated circuit and formation thereof - Google Patents

Abstract

PURPOSE:To form properly TFTs of a constitution having a high mobility and a TFT of a constitution having low-leakage current characteristics according to their respective purposes and moreover, to form a CPU circuit and memory circuits on the same substrate by a method wherein at least one element among carbon, nitrogen, oxygen and silicon is added into the active layer of the first thin film transistor in a specified density by irradiating high-speed ions on the active layer. CONSTITUTION:N-channel TFTs for high-frequency low-power consumption of drivers, decoders, a CPU, memories and the others, N-channel TFTs for driver to drive high power and necessary P-channel TFTs are used for a semiconductor integrated circuit in addition to an N-channel TFT 11 constituting an active matrix circuit. Out of these TFTs, oxygen is added into an active layer of the TFT 11, which is arranged at each pixel electrode,in a density of 5X10<19> to 4X10<21> atomic cm<-3> and the TFT 11 is formed into a constitution having low-leakage current characteristics. Moreover, the concentrations of oxygen, nitrogen and carbon are set low in active layers of the other TFTs constituting peripheral circuits in a concentration of 1X19<19>cm<-3> or lower and the TETs are formed into a constitution having a high mobility.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which thin film transistors (hereinafter referred to as TFTs) are integrated on a substrate. In particular, the present invention relates to an active matrix type liquid crystal display device using thin film transistors integrated on a transparent substrate.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal having a matrix structure, which is formed on a transparent insulating substrate. Amorphous silicon TFTs and polysilicon (also called polycrystalline silicon) TFTs are distinguished by the material and crystal state of the semiconductor used.

Recently, however, research has been carried out using a material exhibiting an intermediate state between polysilicon and amorphous. Although intermediate states have been discussed, herein, some thermal process, for example,
All that has reached a certain crystalline state by thermal annealing at a temperature of 450 ° C. or higher or irradiation with strong energy such as laser light or strong light is referred to as polysilicon.

Also in a single crystal silicon integrated circuit, a polysilicon TFT is used as a so-called SOI technology, and this is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used.

A semiconductor circuit on an insulating substrate using TFTs can operate at high speed because there is no capacitive coupling between the substrate and wiring, and can realize an ultrahigh speed microprocessor or an ultrahigh speed memory.

Generally, a semiconductor in an amorphous state has a small electric field mobility, and therefore, a TF which requires a high speed operation.
Not available for T. Further, in amorphous silicon, since the P-type electric field mobility is extremely small, a P-channel type TFT (PMOS TFT) cannot be manufactured. Therefore, an N-channel type TFT (NMOS TF) is not produced.
T) combined with complementary MOS circuit (CMOS)
Cannot be formed.

However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, unlike a transistor of an active matrix of a liquid crystal display having a small matrix scale, such a high speed operation is not required, and only one conductivity type is sufficient and a TFT having a high charge retention capability is required. Is used for.

On the other hand, a polycrystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, an electric field mobility as high as 300 cm ² / Vs is obtained. Considering that the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value, and M on the single crystal silicon is large.
While the operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring, there is no such restriction because it is on the insulating substrate, and extremely high speed operation is expected.

Further, in polysilicon, the TF of NMOS is
Since not only T but also PMOS TFTs can be obtained in the same manner, it is possible to form a CMOS circuit. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also peripheral circuits (driver etc.) Also, it is possible to realize a so-called monolithic structure, which is configured by a polycrystalline TFT of CMOS. The TFT used in the SRAM described above also pays attention to this point.
The OS is composed of TFTs, which are used as load transistors.

Further, in a normal amorphous TFT, it is difficult to form the source / drain regions by the self-alignment process as used in the single crystal IC technique, and the gate electrode and the source / drain regions are geometrically shaped. While the parasitic capacitance due to overlap is a problem,
Since the polysilicon TFT can adopt the self-alignment process, it has a feature that the parasitic capacitance can be remarkably suppressed.

However, in the polysilicon TFT, the leakage current (also referred to as OFF current) when no voltage is applied to the gate (when not selected) is amorphous silicon T.
In order to use it in an electrode of a liquid crystal display pixel, which is larger than FT, an auxiliary capacitance has been provided for compensating for this leak current, and further, two steps of TFTs are connected in series to reduce the leak current.

As another method, there is known a method of utilizing a high OFF resistance of an amorphous silicon TFT and forming a peripheral circuit of a polysilicon TFT having a high mobility monolithically on the same substrate. This is achieved by forming amorphous silicon and selectively irradiating it with a laser to crystallize only the peripheral circuits.

However, at present, the yield is low due to the problem of the reliability of the laser irradiation process (for example, the in-plane uniformity of irradiation energy is poor), and the amorphous silicon TFT having a low mobility in the active matrix region. Since it will be used, more advanced utilization is difficult. For the laser irradiation process, more reliable and less costly thermal annealing is desired. In addition, the mobility of the TFT is desired to be at least 5 cm ² / Vs in order to increase the added value of the product.

Further, in the conventional liquid crystal display device, there has been proposed a structure in which the TFTs forming the decoder / driver circuit and the TFTs arranged in the pixel electrodes arranged in a matrix are formed on the same substrate. The display does not operate only with the decoder / driver circuit and the pixels, but also requires a CPU circuit and a memory circuit. So far, these have been provided outside and connected to the decoder / driver circuit formed on the glass substrate by wire bonding or the like, but such a configuration increases the number of manufacturing steps and increases reliability. Cause a problem of lowering.

[0015]

SUMMARY OF THE INVENTION The present invention is intended to provide an answer to such a difficult problem, and requires a TFT having high mobility and a TFT having low leakage current.
It is an object of the present invention to provide a structure in which two types of TFTs, FT, are made separately, and a CPU circuit and a memory circuit required for a liquid crystal display are formed on the same substrate.

[0016]

According to the present invention, in a liquid crystal display device having a structure in which a liquid crystal is sandwiched between a pair of substrates, a T driving a pixel electrode on one of the substrates forming the liquid crystal display device.
It is characterized in that an FT, a TFT which constitutes a decoder and a driver circuit, a TFT which constitutes a memory and a CPU, and the like are integrated and formed.

Conventionally, the concentration of impurities contained has been made as low as possible in order to make a TFT having high mobility. This is because unlike polysilicon in a single crystal state, impurities lower the energy barrier of crystal grain boundaries in polysilicon. According to the research conducted by the inventor of the present invention, depending on the concentration of oxygen or nitrogen or carbon contained in polysilicon, TF
It has become clear that the characteristics of T vary. That is,
It is generally observed that the mobility decreases as the concentration of oxygen, nitrogen or carbon increases. However, at the same time, the off current can be reduced. A similar effect is
It can also be obtained by irradiating a semiconductor film in an amorphous or polycrystalline state with high-speed ions. Due to damage by the fast ions, the crystallinity is not completely recovered even in the subsequent crystallization process such as thermal annealing, and as a result, a semiconductor film having a low off current can be obtained. Ions to be irradiated are preferably oxygen, carbon, nitrogen, and silicon, and it is preferable that hydrogen ions are simultaneously included in the irradiation of these ions.

The present invention takes advantage of this phenomenon. In the TFT arranged in the pixel, oxygen, nitrogen, or carbon is added as an impurity to the active layer, or oxygen, nitrogen, carbon, silicon, or the like is added at 30 keV or more. By accelerating at high speed and injecting into the active layer, low leak characteristics are obtained, and the driver circuit, the memory circuit, and the peripheral circuit portion that constitutes the CPU circuit are high mobility TFTs with a low impurity concentration. .

In order to realize the above-mentioned structure, the region of the high mobility TFT may be masked and at least one kind of ions of oxygen, nitrogen, carbon and silicon may be accelerated and introduced. . At this time, it is preferable that hydrogen ions are contained in addition to these ions. As for the mask, a method of adhering a photoresist to a substrate, patterning it, and selectively introducing it into an opening, which is used in a normal cMOS technique, or a metal mask is more simple. Alternatively, a mask that is not adhered to the substrate may be used. In particular, the latter method is suitable when the process is simple and the system is not so demanding. For example, it is suitable when the circuits are clearly separated from each other, such as an active matrix circuit area (area to be irradiated with ions) and its peripheral circuit area. Then, after that, a high mobility TFT and a low leakage current TFT are formed by thermal annealing.
Both of the active layers are crystallized. The thermal annealing is used here because it is excellent in uniformity. The thermal annealing process may be performed after the gate electrode is formed or after the source / drain is formed. The temperature of the thermal anneal is limited by the substrate and other materials, but when silicon or quartz is used as the substrate, a thermal anneal of up to 1100 ° C. is possible. Other substrate materials, such as Corning 7059 glass, which is a typical alkali-free glass,
Annealing at a temperature of 650 ° C. or lower is desirable.

One example of the present invention is that, in the display portion of an active matrix circuit such as liquid crystal, a PMOS TFT is used.
Is used as a switching transistor, and the oxygen concentration in the active layer of the TFT in the active matrix region is 10 ¹⁸ c.
m ⁻³ or more, preferably 5 × 10 ¹⁹ cm ⁻³ or more, while the concentration of oxygen or nitrogen in the active layer of the TFT used in the peripheral circuit is 1 × 10 ¹⁹ cm ⁻³ or less, preferably It is to be 1 × 10 ¹⁷ cm ⁻³ or less. Where PM
The reason why the OS is used is that the leakage current (OFF current) can be made smaller than that of the NMOS. The upper limit of the concentration of the implanted impurities such as oxygen is preferably 4 × 10 ²¹ atoms cm ⁻³ or less.

In the pixel TFT circuit, the PMO
The present invention also includes the case where the S and NMOS TFTs are inserted in series. Of course, it is also within the technical scope of the present invention that two PMOS TFTs are inserted in parallel.

In the liquid crystal display device, the display circuit section (active matrix) and its drive circuit (peripheral circuit)
In the device having and, it is useful that the drive circuit is a CMOS circuit. In this case, all circuits are CMOS
However, it is preferable that the transmission gate and the inverter circuit are formed in CMOS.

Regarding the CMOS circuit of the driver section,
In order to obtain high mobility, it is desired that the concentration of impurities such as oxygen, nitrogen and carbon in the active layer be 1 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁷ cm ⁻³ or less. As a result, for example, the threshold voltage of the TFT is 0.5 to 2 V in the NMOS, -0.5 to -3 V in the PMOS, and the mobility is 30 to 150 cm ² / Vs in the NMOS, P
For MOS, it can be set to 20 to 100 cm ² / Vs.

On the other hand, in the active matrix portion, the auxiliary capacitance can be reduced by using a single element having a leak current of about 1 pA with a drain voltage of 1 V or a plurality of elements in series, and it is completely unnecessary. can do.

Further, according to the present invention, the CPU formed on the same substrate at the same time as the TFT formed in the pixel electrode and the peripheral driver circuit.
The feature is that a circuit and a memory circuit are simultaneously formed. For example, in a single crystal IC, the operating speed has already reached its limit, and it is necessary to increase the current capacity of the transistor in order to achieve higher speed operation, but this is due to a further increase in current consumption. Cause.

It is said that the single crystal IC has reached the speed limit because, in part, a large loss occurs due to the capacitance of the substrate and wiring. If an insulator is used for the substrate, it can be driven at a sufficiently high speed without increasing the current consumption. For this reason, an IC having an SOI (semiconductor on insulator) structure has been proposed.

As described above, it is useful to use the TFT in an integrated circuit. Therefore, not only the matrix circuit that constitutes the pixels of the liquid crystal display device, the driver circuit and the decoder circuit that drive the matrix circuit, but also the CP circuit
Forming U circuit and memory circuit on the same substrate
It is extremely useful for downsizing and integration of liquid crystal display devices.

In the present invention, the active layer of the TFT is doped with oxygen, nitrogen or carbon,
One of the features is to control the leakage current characteristics,
This doping reduces the mobility. Therefore, it is necessary to select the leak current and the mobility in a timely manner so as to meet the purpose.

[0029]

EXAMPLES As shown in FIG. 1, it is premised that all TFTs described in the following examples are formed on the same substrate 14. FIG. 1 shows a block diagram of a structure formed on this one substrate. In FIG. 1, 11 is a TFT provided in one pixel of the active matrix portion, 12 is a liquid crystal, and 13 is a capacitor. In the configuration shown in FIG. 1, in addition to the TFT 11 formed in each pixel, an input port, correction memory, memory, CP
It is characterized in that the TFTs forming the circuits of U, XY branch, X decoder / driver, and Y decoder / driver are all formed on the same substrate.

In the configuration shown in FIG. 1, in addition to the N-channel type TFT 111 constituting the active matrix circuit, a driver, a decoder, a CPU, a memory, other high frequency and low power consumption NTFT, high power drive driver NTFT, And the required PTFTs are used.

Of these TFTs, the TFT 11 arranged on each pixel electrode contains 5 × 10 ¹⁹ c of oxygen in the active layer.
Since it contains m ^-3 or more, it has a structure having a low leakage current characteristic. In addition, TFTs that make up other peripheral circuits
Has a concentration of oxygen, nitrogen or carbon of 1 in the active layer.
It is as low as × 10 ¹⁹ cm ^-3 or less and has a high mobility.

By constructing electronic circuits and integrated circuits other than the circuit shown in FIG. 1 using TFTs,
It is easy to imagine that it is possible to construct more sophisticated circuits and systems.

In FIG. 1, an input port refers to a signal input from the outside and converts it into an image signal, and a correction memory is a panel for correcting the input signal and the like in accordance with the characteristics of the active matrix panel. It is a unique memory. In particular, this correction memory has information unique to each pixel as a non-volatile memory and is used for individual correction. That is, when a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the pixel has the same brightness as the surrounding pixels.

The CPU and the memory have the same functions as those of an ordinary computer, and in particular, the memory has an image memory corresponding to each pixel as a RAM. Further, the backlight for irradiating the substrate from the back side can be changed according to the image information.

[Embodiment 1] FIG. 2 shows a manufacturing process of this embodiment. This embodiment is an example in which a polysilicon TFT by low temperature annealing is used in the peripheral circuit and active matrix region of a liquid crystal display device.

First, a base oxide film 102 having a thickness of 200 is formed on a Corning 7059 substrate 101 by a sputtering method.
~ 2000Å Deposit. Further, an amorphous silicon film having a thickness of 500 to 1500 Å is deposited thereon by a plasma CVD method or a low pressure CVD method using monosilane or disilane as a raw material. At this time, the concentration of oxygen and nitrogen in the amorphous silicon film is 1 × 10 ¹⁹
cm ^-3 or less, preferably 1 × 10 ¹⁷ cm ^-3 or less.
The low pressure CVD method is suitable for this purpose. In this embodiment, the oxygen concentration in this amorphous silicon film is set to 1 × 1.
It was set to 0 ¹⁷ cm ^-3 or less. On this amorphous silicon film, a protective silicon oxide film (thickness 1
00 to 500Å) 105 is formed. After that, the peripheral circuit region 104 is covered with a photoresist 106 or the like to expose only the active matrix region 103.

Then, by the ion doping apparatus,
Irradiation with oxygen ions was performed as shown in FIG. The acceleration energy is 10 to 100 depending on the thickness of the protective layer 105.
It was set to keV. The dose is determined by the thickness and acceleration energy of the protective layer 105, and the underlying amorphous silicon film 10.
The optimum value may be determined according to the thickness of 3. For example,
When the thickness of the amorphous silicon film is 1000Å, the protective layer is 250Å, and the acceleration energy is 50 keV, the dose amount is set to 5 × 10 ¹⁴ cm ^-2 , so that the oxygen concentration is 5 × over almost the entire area of the amorphous silicon film 103. It can be set to 10 ¹⁹ cm ^-3 . Instead of using the photoresist mask, a metal mask 106 'may be used as shown in FIG. 2 (A'). In this case, the photolithography process is unnecessary. The photoresist is carbonized by ion irradiation and it takes a lot of time to remove it. However, when a metal mask is used, such an effort is unnecessary. However, when the metal mask is used, the oxygen ion concentration at the boundary is more gently distributed than when the photoresist is used.

After removing the photoresist 106, the amorphous silicon film was crystallized by annealing at 600 ° C. for 24 hours. After that, these Si films are patterned into an island shape, for example, as shown in
As shown in (B), the island-shaped region 107 of the peripheral circuit and the island-shaped region 108 of the active matrix region are formed. Further, a silicon oxide film (thickness 500 to 1500 Å) is formed by a sputtering method so as to cover these island regions, and this is used as a gate insulating film 109. After that, the thickness is 2000Å ~
An aluminum film having a thickness of 5 μm is formed by an electron beam evaporation method, and this is patterned to form a gate electrode in each island region.

Further, the substrate is immersed in an electrolytic solution to pass an electric current through the gate electrode to form an anodic oxide layer around the gate electrode. In this case, Japanese Patent Application Nos. 4-30220 and 4-20
38637 and 4-54322, the anodic oxide film of the TFT in the peripheral circuit region is thinned to improve the mobility, and the anodic oxide film of the TFT in the active matrix portion is thickened to prevent the gate leak. It is desirable to take a configuration. In each of the examples, the thickness of the anodic oxide film is 1000 to 2500 Å. Through the above steps, an oxide layer is formed around the gate electrodes 110 to 112 of each TFT.

Thereafter, by ion doping, impurities are self-alignedly implanted into the island-shaped silicon film of each TFT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask. At this time, first, phosphorus is injected into the entire surface by using phosphine (PH ₃ ) as a doping gas, and then only the right side of the island region 107 in the figure is covered with a photoresist to dope diborane (B ₂ H ₆ ). As a gas, boron is implanted into the left side of the island region 107 and the active matrix region. The dose is 2-8 for phosphorus
× 10 ¹⁵ cm ^-2 , boron is 4 to 10 × 10 ¹⁵ cm ^-2 ,
It is set so that the dose amount of boron exceeds that of phosphorus.

Although the crystallinity of the silicon film is destroyed by the doping process, the sheet resistance thereof can be about 1 kΩ / □. However, if the sheet resistance of this level is too large, it is further increased to 2 to 2 at 600 ° C.
It is possible to reduce the sheet resistance by annealing for 4 hours. This annealing process may be performed by irradiation with infrared light. This step is called RTA (Rapid Thermal Annealing) and utilizes the fact that infrared light is selectively absorbed by the silicon film and impurities added to the silicon film. In this RTA process, since infrared light is not easily absorbed by the glass substrate, 100% is applied to the silicon film.
The same effect as when annealing is performed at a high temperature of 0 ° C. or higher can be provided.

Through the above steps, the N type region 114,
And P-type regions 113 and 115 are formed. The sheet resistance of these regions is 200 to 800 Ω / □. At the same time, the active layers 116 to 118 were also formed. Of these, in the active layers 116 and 117, nitrogen, oxygen,
The concentration of carbon is 1 × 10 ¹⁷ cm ⁻³ or less, while the active layer 118 has a concentration of oxygen of 5 by the process of FIG.
It is increased to × 10 ¹⁹ cm ^-3 . After that, a silicon oxide film having a thickness of 3000 to 10000Å is formed as an interlayer insulator 119 on the entire surface by a sputtering method. This may be a silicon oxide film formed by the plasma CVD method. In particular, a plasma CVD method using TEOS as a raw material can provide a silicon oxide film having good step coverage.

After that, an ITO film is formed as the pixel electrode 120 by the sputtering method and is patterned. And source / drain of TFT (impurity region)
Contact holes are formed in the chrome wires 121 to 12
4 is formed. In FIG. 2D, the NTFT and PTF on the left side are shown.
It is shown that a CMOS circuit is formed by T. The wirings 121 to 124 may be multi-layered wiring with aluminum on which chrome or titanium nitride is used as a base to reduce the sheet resistance. Finally, it is annealed in hydrogen at 350 ° C. for 2 hours to reduce dangling bonds in the silicon film. Through the above steps, the peripheral driver circuit and the active matrix circuit can be integrally formed.

FIG. 2 shows an example in which a peripheral circuit driver circuit and an active matrix circuit composed of TFTs formed in each pixel electrode are integrally formed. At the same time, a memory circuit and a CPU circuit are formed. can do.

Although the liquid crystal display device has been described above as an example, the present invention can be applied to an image sensor having a solid-state image pickup device portion and a drive circuit formed on the same substrate. In this case, the necessary memory circuit and CPU circuit may be formed by TFTs on the same substrate.

[0046]

The matrix circuit (constituting a large number of pixel electrodes) required for the liquid crystal display device, the peripheral driver circuit, the decoder circuit, the CPU circuit, and the memory circuit are formed on the same substrate, so that they are integrated. Liquid crystal display device can be obtained. In particular, by controlling the characteristics of the TFT by the impurity concentration of oxygen, nitrogen, and carbon in the active layer, or by controlling the dose amount of oxygen, nitrogen, carbon, and silicon, the required characteristics can be obtained. .

[Brief description of drawings]

FIG. 1 shows the configuration of an embodiment.

FIG. 2 shows a manufacturing process of an example.

[Explanation of symbols]

11 ... TFT 12 ... Liquid crystal 13 Capacitor 14 Glass substrate 101 Glass substrate 102 Underlying oxide film 103 ... Matrix region 104 ... Peripheral circuit region 105 ... Silicon oxide film 106 ... Photoresist 106 '... Metal mask 107 ... Peripheral circuit Island-shaped region 108 ... Island-shaped region of active matrix region 109 ... Gate insulating film (silicon oxide film) 110-112. Gate electrode portion (gate electrode and oxide layer) 113 .. ... P-type region 114 ... N-type region 115 ... P-type regions 116 to 118-Channel forming region 119 ... Inter-layer insulating film 120 ... Pixel electrode (ITO ) 121-124 black Wiring

Claims (7)

[Claims] 1. A semiconductor integrated circuit having a plurality of first thin film transistors provided in each pixel of a liquid crystal display device and a plurality of second thin film transistors forming a peripheral circuit on the same substrate, wherein: The active layer of the thin film transistor of No. 1 contains 5 × 10 ¹⁹ to 4 × 10 ²¹ atom cm ⁻³ of at least one element selected from carbon, nitrogen, oxygen, and silicon by irradiation with fast ions.
2. The semiconductor integrated circuit, characterized in that carbon, nitrogen, oxygen, and silicon were not intentionally added to the active layer of the second thin film transistor by the irradiation of fast ions. 2. A semiconductor integrated circuit having a plurality of first thin film transistors provided in each pixel of a liquid crystal display device and a plurality of second thin film transistors forming a peripheral circuit on the same substrate. In the active layer of the thin film transistor of No. 1, at least one element of carbon, nitrogen and oxygen is 5 × 10 ¹⁹ to 4
× 10 ²¹ atoms cm ^−3, carbon in the active layer of the second thin film transistor,
A semiconductor integrated circuit characterized in that the concentration of nitrogen and oxygen is 1 × 10 ¹⁹ cm ⁻³ or less. 3. The semiconductor integrated circuit according to claim 2, wherein the peripheral circuit includes a driver circuit, a decoder circuit, a memory circuit, a CPU circuit, and an input / output circuit. 4. A matrix circuit on the same substrate, a drive circuit for driving the matrix circuit, an arithmetic circuit for sending a drive signal to the drive circuit, and a memory circuit for storing information required by the arithmetic circuit. Each of the circuits is formed of a thin film transistor formed on the surface of the substrate, and at least one element selected from the group consisting of oxide, nitrogen, and carbon is included in the active layer of the thin film transistor forming the matrix circuit. A semiconductor integrated circuit containing x10 ¹⁹ to 4x10 ²¹ atoms cm ^-3 . 5. A first step of forming a silicon film on a substrate, and selectively irradiating the silicon film with fast ions of oxygen, nitrogen, carbon, and silicon, thereby irradiating the ion-irradiated region. And a second that forms an unexposed area
And a third step of forming a thin film transistor in both a region irradiated with fast ions and a region not irradiated with the fast ions obtained by the second process. Of manufacturing. 6. The method for manufacturing a semiconductor integrated circuit according to claim 5, wherein in the second step, high-speed ions are selectively irradiated using a mask that does not adhere to the substrate. 7. The method for manufacturing a semiconductor integrated circuit according to claim 5, wherein in the second step, hydrogen ions are simultaneously irradiated in addition to the elements.