JPH07161188A - Multiport memory cell circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To enable multiple data writes simultaneously or serially. [Structure] A transistor Mx is provided between an output node N1 of a first inverter circuit including transistors M1 and M3 and a power supply node Vcc in the inverter circuit. A transistor My is provided between the output node N2 of the second inverter circuit composed of the transistors M2 and M4 and the power supply node Vcc in this inverter circuit. During data writing, the transistors Mx and My are controlled to control the node N1 of the first inverter circuit and the power supply node V
cc, and the node N2 of the second inverter circuit and the power supply node Vcc are electrically disconnected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multiport memory cell circuit, and more particularly to a multiport memory in which a data write word line and a data read word line are different and a data write path and a data read path are different. It relates to a cell circuit.

[0002]

2. Description of the Related Art FIG. 11 shows a word line for writing data,
An example of a conventional multi-port memory cell circuit is a 2-port memory cell circuit that has a data read word line, a data write path, and a data read path that are independent of each other, and has one port for writing data and one port for reading data. Show as. In the figure, M1 and M2 are p
The channel transistors M3 and M4 are n-channel transistors. These transistors M1 to M4 form a flip-flop that latches the store data in the same circuit. M5 to M8 are n-channel transistors, of which M5 and M6 are data read cell select transistors, and M7 and M8 are data write cell select transistors. BL (R) and BLN (R) are data read bit line pairs that propagate complementary data, and
L (W) and BLN (W) are data write bit line pairs that propagate complementary data. Further, WL (R) is a data read word line, and WL (W) is a data write word line. In addition, N1 is a transistor M2, M4
Is an input node of the inverter circuit configured by (the output node of the inverter circuit configured by the transistors M1 and M3), and N2 is an input node of the inverter circuit configured by the transistors M1 and M3 (transistor M1.
2 and M4 are the output nodes of the inverter circuit).

In the multiport memory cell circuit shown in FIG. 11, the node N1 is at "H" level and the node N2 is
Suppose that the "L" level is stored in and the inverted data is written by giving the "L" level to the data write bit line pair BL (W) and the "H" level to BLN (W). Data writing is performed by the data writing word line W.
L (W) is turned on, and the node N is set below the logical threshold value (input voltage value that can invert the state of the inverter circuit) of the inverter circuit formed by the transistors M2 and M4 in the figure.
This is done by lowering the voltage level of 1. In this case, the data write circuit (not shown) causes the node N to pass through the data write bit line BL (W) and the transistor M7.
The charge stored in 1 is extracted. Considering the above situation, a case is considered in which a plurality of word lines WL (W) are activated and "L" level data on the same bit line BL (W) is collectively written to a plurality of same memory cell circuit groups. .

The voltage level of the node N1 is determined by the conduction resistance ratio of the charge drawing transistor, the data writing cell selection transistor M7, and the p-channel load transistor M1 in the data writing circuit. In the case of simultaneous writing to a plurality of multiport memory cell circuit groups, the conduction resistances of the data writing cell selection transistor M7 and the p-channel load transistor M1 are reduced to 1 / (the number of simultaneously operating transistors). Therefore, as the number of simultaneously operating transistors increases, the voltage level of the node N1 rises as compared to when writing to one memory cell circuit. Therefore, the voltage level of the node N1 does not become lower than the logic threshold value of the inverter circuit, and data may not be written in some cases.

FIG. 12 is a 2-port memory in which a data write word line, a data read word line, a data write path and a data read path are independent of each other, and each has one port for writing data and one port for reading data. The cell circuit is shown as another example of the conventional multi-port memory cell circuit. This circuit is different from the circuit configuration of FIG. 11 in that the word line WL for data writing is used.
That is, the delay circuit DL is inserted in (W). Output node of the delay circuit DL (word line W for data writing
L '(W) controls the data write cell select transistors M7 and M8. In the delay circuit DL, the transistors M9 and M10 are n-channel transistors M11 to M11.
M13 is a p-channel transistor.

Due to the continuous voltage change of the control line CTL input to the gate of the transistor M13, the transistor gain constant of the transistor M13 changes, and the rise time of the output of the inverter circuit configured with the transistors M9 and M11 is continuously changed. Change to. As a result, the signal propagation delay amount of the inverter circuit including the transistors M9, M11 and M13 can be changed. The output node of the inverter circuit composed of the transistors M9, M11 and M13 is connected to the input node of the inverter circuit composed of the transistors M10 and M12. Therefore, according to the potential of the control line CTL, the transition timing from the “H” level of the signal on the data write word line WL (W) to the “L” level has a desired delay amount and the data is written with high accuracy. Is propagated to the word line WL '(W).

As is clear from the above description, FIG.
According to the configuration of the multiport memory cell circuit shown in 2, data is written at the transition timing of the signal on the data write word line WL ′ (W) from the “H” level to the “L” level. Therefore, "L" of the input data
Level to “H” level, or the transition from “H” level to “L” level at a desired time interval,
That is, it is possible to write to these multiport memory cell circuit arrays with time accuracy.

A plurality of data writing word lines WL (W) of the multi-port memory cell circuit of FIG. 12 described above are arranged so that the adjacent data writing word lines WL '(W) of the same circuit are connected. Consider the operation of a multiport memory cell circuit. In order to select a plurality of multiport memory cell circuits at the same time, a clock signal with a long cycle is applied to the word line WL for writing data in the circuit at the column end.
When applied to (W), data write bit line pair B
The data on L (W) and BLN (W) is propagated to the nodes N1 and N2 in the multi-port memory cell circuit via the transistors M8 and M7 in the circuit. However, similarly to the above-described conventional example, it is difficult to set the voltage level of the node N1 to be equal to or lower than the logical threshold value of the inverter circuit including the transistors M2 and M4, and a situation in which data cannot be written occurs.

[0009]

As described above, the conventional multiport memory cell circuit has a problem that it is difficult to write data to a plurality of same circuits simultaneously or serially.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a multiport memory cell circuit capable of simultaneously writing a plurality of data or serially. To provide.

[0011]

In order to achieve such an object, the present invention electrically connects between an output node of a first inverter circuit and a power supply node or a ground node in the inverter circuit. A second circuit for providing first circuit means for disconnecting between the nodes and electrically disconnecting between the output node of the second inverter circuit and the power supply node or the ground node in this inverter circuit Means is provided for writing the first and second data when writing data.
The circuit means is controlled to electrically disconnect the output node of the first and second inverter circuits from the power supply node or the ground node in the inverter circuit.

[0012]

Therefore, according to the present invention, the multiport memory cell circuit can be constructed so that the logic threshold value of the inverter circuit is not affected by the data write.

[0013]

EXAMPLES The present invention will now be described in detail based on examples. [Embodiment 1] FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The feature of this embodiment is that the control signal from the control line CTLXY is supplied during the data writing period when any one of the N data writing word line groups WL (W1) to WL (WN) is at the “H” level. Therefore, a p-channel transistor Mx that electrically disconnects the node N1 and the power supply node Vcc and a p-channel transistor My that electrically disconnects the node N2 and the power supply node Vcc are inserted. The control signal from the control line CTLXY in this embodiment is output from the generation circuit shown in FIG.

That is, the word line group W for data writing
By the control signal from the control line CTLXY which is at the “H” level for the same period as the write command command from L (W1) to WL (WN), the node N1 and the power supply node Vcc are connected by the transistor Mx during the data write period, and The node N2 and the power supply node Vcc are connected by the transistor My.
It is electrically disconnected. Therefore, desired data can be independently written to the input nodes of these inverter circuits regardless of the states of the inverter circuits, particularly the theoretical threshold value. This write state does not depend on the number of memory cell circuits selected at the same time. Further, when the data write word line groups WL (W1) to WL (WN) are all set to the “L” level and the data write is completed, both the transistors Mx and My are turned on, and the flip-flop for latching the write data is formed. Composed again.

[Second Embodiment] FIG. 3 is a circuit diagram showing a second embodiment of the present invention. This embodiment is different from the first embodiment in the insertion position of the p-channel transistors Mx and My. Also in this embodiment, the same effect as that of the first embodiment can be obtained.

Embodiments 3 and 4 FIGS. 4 and 5 are circuit diagrams showing the third and fourth embodiments of the present invention. The difference between these embodiments and the first and second embodiments is that n-channel transistors having different polarities are used for Mx and My. Figure 4
5 and FIG. 5 are different in the insertion positions of the n-channel transistors Mx and My. Control line CTLX in FIGS. 4 and 5
The control signal from YN is output from the generation circuit shown in FIG. Data write word line group WL (W1) to WL
The control line CTLXYN is set to the “L” level only when any one of (WN) is at the “H” level, so that the node N1 and the ground node Vss in FIGS. 4 and 5 are transistors during the data writing period. The node N2 is electrically disconnected from the ground node Vss by the transistor My by the transistor My. Therefore, the state of the inverter circuit,
In particular, desired data can be independently written to the input nodes of these inverter circuits regardless of the logical threshold value.

[Embodiments 5 and 6] FIGS. 7 and 8 are circuit diagrams showing fifth and sixth embodiments of the present invention. These embodiments correspond to the case where the number of data writing ports is one in the first embodiment (FIG. 1) and the third embodiment (FIG. 4). The difference between these embodiments and the first and third embodiments is that the data write word line WL (W) or W having complementary polarities is used.
LN (W) controls the data write cell selection transistors M (2M + 5), M (2M + 6) and the transistors Mx, My. In particular, in FIG. 8, transistors M (2M + 5), M (2M + 5), M (2M + 5), M (2M + 6), M (2M + 5), M (2M + 5), M (2M + 5), M (2M + 5), M (2M + 5), M (2M + 5), M (2M + 6), Mx, My are controlled by one data write word line WLN (W).
The polarity of 6) is changed from the n channel in FIG. 4 to the p channel.

In the fifth embodiment (FIG. 7), since the data write word line WL (W) becomes the “H” level, the node N1 and the power supply node Vcc are connected by the transistor Mx and the node N2 and power supply node Vcc are electrically separated by transistor My. In the sixth embodiment (FIG. 8), since the data write word line WLN (W) becomes the “L” level, the node N1 and the power supply node Vcc are connected by the transistor Mx and the node N2 and the power supply are connected during the data write period. Node Vc
c and c are electrically separated from each other by the transistor My. Therefore, desired data can be independently written to the input nodes of these inverter circuits regardless of the state of the inverter circuits, particularly the logical threshold value. The configurations of these embodiments can be applied to the configurations of the second embodiment (FIG. 3) and the fourth embodiment (FIG. 5), and the effects are the same as those of the present embodiment.

Generally, in this type of multi-port memory cell circuit, even if there are a plurality of data read ports,
In many cases, there is only one data writing port. this is,
This is because if different data is written to the multi-port memory cell circuit at the same time via multiple ports, a malfunction will occur, and it will only be possible to mount a data write adjustment circuit (arbiter circuit) on the memory chip to prevent this malfunction. This is because use of a plurality of data writing ports is effective. Therefore, a multi-port memory cell circuit having a one-port data write port is
It can be said that it is more practical than a multi-port memory cell circuit having another configuration.

[Embodiment 7] FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention. In the present embodiment, the ports for data writing and data reading are both 1 in the first embodiment (FIG. 1).
Data write word line WL.
It is different from the first embodiment in that a delay circuit DL similar to that shown in FIG. 12 is inserted in (W). As is apparent from the configuration of FIG. 2, when the number of data write word lines is one, the control line CTLXY in the first embodiment is the delay circuit D in the present embodiment.
It can be made equal to the L data write word line WL ′ (W). This data write word line WL '(W) controls the transistors M7, M8, Mx, My in FIG.

According to the present embodiment, during the data writing period when the data writing word lines WL (W) and WL '(W) are at the "H" level, the node N1 and the power supply node Vcc are connected by the transistor Mx, and The node N2 and the power supply node Vcc are electrically separated by the transistor My. Therefore, desired data can be independently written to the input nodes of these inverter circuits regardless of the logical thresholds of the inverter circuits of transistors M1 and M3 and the inverter circuits of transistors M2 and M4. This write state does not depend on the number of memory cell circuits selected at the same time. In addition, the data write word lines WL (W) and WL ′ (W) are “L”.
When the level is reached and the data writing is completed, the transistors Mx and My are turned on, and the flip-flop for latching the write data is reconfigured. The delay circuit DL shown in this embodiment can be inserted in the configuration of the second embodiment (FIG. 3), and the effect is the same as that of the present embodiment.

[Embodiment 8] FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention. This embodiment is the third embodiment (FIG. 4).
The data write and data read ports both show one example, and the data write word line W
The third embodiment is different from the third embodiment in that a delay circuit DL ′ obtained by modifying the delay circuit DL is inserted in LN (W). In this embodiment, the data write cell select transistors M7 and M are selected.
A p-channel transistor is used as 8. The difference between the delay circuit DL ′ and the delay circuit DL is that the p-channel transistor M13 controlled by the control line CTL in the delay circuit DL is changed to an n-channel transistor controlled by the control line CTL ′, and the n-channel transistor M9.
It is provided on the ground side of.

Due to the continuous voltage change of the control line CTL 'input to the gate of the transistor M13 in the delay circuit DL', the transistor gain constant of the transistor M13 changes, and the inverter circuit formed together with the transistors M9 and M11. The output rise time is continuously changed. As a result, the signal propagation delay amount of the inverter circuit including the transistors M9, M11 and M13 can be changed. The output node of the inverter circuit composed of the transistors M9, M11 and M13 is the transistor M
It is connected to the input node of an inverter circuit composed of M10 and M12.

Therefore, in accordance with the potential of the control line CTL ', the transition timing of the signal on the data write word line WLN (W) from the "L" level to the "H" level has a desired delay amount and data. Write word line WLN '
(W) is propagated. Here, the data write word lines WLN (W) and WLN ′ in the delay circuit DL ′.
The signal on (W) has the opposite polarity to the data write word lines WL (W), WL '(W) in the delay circuit DL in FIG. Therefore, the data write has a polarity opposite to that of the data write word lines WLN (W) and WLN ′ (W). Therefore, data writing is performed while the data writing word lines WLN (W) and WLN ′ (W) are at the “L” level.

As is clear from the above description, FIG.
According to the configuration of the multiport memory cell circuit shown in 0, the data is written at the transition timing of the signal on the data write word line WLN ′ (W) from the “L” level to the “H” level. Further, during the data write period in which the data write word lines WLN (W) and WLN ′ (W) are at the “L” level, the node N1 and the ground node Vss.
Are electrically isolated from each other by the transistor Mx, and the node N2 and the ground node Vss are electrically isolated from each other by the transistor My.

Therefore, desired data can be independently written to the input nodes of these inverter circuits irrespective of the logical threshold values of the inverter circuits composed of the transistors M1 and M3 and the inverter circuit composed of the transistors M2 and M4. . Therefore, "L" of the input data
Level to "H" level or "H" level to "L"
The timing of transition to the level can be written in these multi-port memory cell circuit arrays with a desired time interval, that is, time accuracy. The delay circuit DL ′ shown in this embodiment can be inserted in the configuration of the fourth embodiment (FIG. 5), and the effect is the same as that of the present embodiment.

In the embodiment of the present invention described above,
The delay circuits DL and DL ′ are not limited to the illustrated configuration. For example, the signal propagation delay amount of the data write word line WL (W) may be controlled by both the p-channel transistor controlled by the control line CTL and the n-channel transistor controlled by the control line CTL ′. Alternatively, another signal propagation delay amount control method may be used for replacement.

[0028]

As is apparent from the above description, according to the present invention, the output node of the first inverter circuit and the power supply node or the ground node in the inverter circuit are electrically connected to each other. First circuit means for shutting off is provided, and second circuit means for electrically shutting off between these nodes is provided between the output node of the second inverter circuit and the power supply node or ground node in this inverter circuit. , The first and second circuit means are controlled at the time of writing data to electrically disconnect the output node of the first and second inverter circuits from the power supply node or the ground node in the same inverter circuit. Therefore, the multi-port memory cell circuit can be configured so that the logic threshold value of the inverter circuit is not affected by the data write, An effect that it is possible to easily write data simultaneously or serially to the memory cell circuit. In particular, if the multiport memory cell circuit of the present invention, which has a delay circuit in which a desired delay amount is controlled with high precision, is used as the constituent element, the input data is changed from the “L” level to the “H” level or the “H” level. The effect that the transition timing to the “L” level can be recorded and accumulated in the present multi-port memory cell circuit array with high precision is achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit for generating a control signal to a control line CTLXY in FIGS. 1 and 3.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

6 is a diagram showing a circuit for generating a control signal to a control line CTLXYN in FIGS. 4 and 5;

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram of a conventional multiport memory cell circuit.

FIG. 12 is a circuit diagram showing another example of a conventional multiport memory cell circuit.

[Explanation of symbols]

M1, M2 p-channel transistor M3, M4 n-channel transistor Mx, My p-channel transistor M5-M (2M + 4) data read cell selection transistor BL (R1) -BL (RM), BLN (R1) -BLN
(RM) Data read bit line pair WL (R1) to WL (RM) Data read word line M (2M + 5) to M (2M + 2N + 4) Data write cell select transistors BL (W1) to BL (WM), BLN ( W1) ~ BLN
(WM) Data write bit line pair WL (W1) to WL (WM) Data write word line Vcc Power supply node Vss Ground node N1, N2 node CTLXY Control line DL Delay circuit

Front page continuation (72) Inventor Junzo Yamada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. A first data read cell selection transistor is provided in a number M (M) at an output node of the first inverter circuit.
≧ 1) connected, and M (M ≧ 1) second data read cell selection transistors are connected to the output node of the second inverter circuit, and the M first and second data read cell selection transistors are selected. Each corresponding one of the transistors is set as one set of data read cell selection transistors, and each of the M sets of data read cell selection transistors has a set of 1st to Mth data read bit line pairs. Connected to each of the first to Mth data read word lines, each of which is controlled by the first to Mth data read word lines, and has N first data write cell selection transistors (N ≧ 1) at the output node of the first inverter circuit. N second (N ≧ 1) second data write cell select transistors are connected to the output node of the second inverter circuit. Each corresponding one of the second data writing cell selection transistors is set as one set of data writing cell selection transistors, and each of the N sets of data writing cell selection transistors has a first to Nth set. Each of the bit lines is connected to a data write bit line pair and controlled by the first to Nth data write word lines to an output node of the first inverter circuit and a power supply node or ground in the inverter circuit. First circuit means for electrically disconnecting these nodes from each other is provided between the node and the node, and electrically connected between the output node of the second inverter circuit and the power supply node or the ground node in the inverter circuit. Second circuit means for cutting off between the nodes is provided, and the first and second circuit means are the first to Nth data write word lines. Characterized in that it is controlled by the write control line activated by al the write command (M + N) multi-port memory cell circuit having a number of ports. 2. The multiport memory cell circuit according to claim 1, wherein the first and second data write cell select transistors connected to the output nodes of the first and second inverter circuits are one (N). = 1) and the first and second circuit means are controlled by the first data write word line. A multi-port memory cell circuit having (M + 1) ports. 3. The multiport memory cell circuit according to claim 1 or 2, wherein a delay circuit capable of controlling a delay amount by a control signal from the outside is added to the data write word line. Multiport memory cell circuit.