JPH0715013A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Construction] After the punch-through stopper layer 7 is formed, a region having a peak is formed in the punch-through stopper layer 7 by limiting the region immediately below the gate, and a substrate having a concentration that compensates the impurity concentration of the stopper layer 7 is formed. A region 8 is formed by ion-implanting impurities of opposite conductivity type. [Effect] The threshold voltage can be set low, and deterioration of transistor characteristics due to punch-through can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor.

[0002]

2. Description of the Related Art In insulated gate field effect transistors, the channel length has been reduced due to the miniaturization of the transistor size, and the depletion layers extending from the source / drain contact each other during operation of the transistor, resulting in a current that cannot be controlled by the gate electrode inside the substrate. It is known that a punch-through phenomenon of flowing through the flow occurs.

Since punch-through occurs even when a voltage is not applied to the drain when the gate length becomes short, conventionally, as shown in FIG. 2, the same conductivity type as that of the substrate 1 is formed below the channel 6 between the source region 4 and the drain region 5. The punch-through stopper layer 7 doped with impurities is formed to suppress the spread of the depletion layer between the source region 4 and the drain region 5. Denoted at 10 and 11 are the ends of the depletion layer extending from the source / drain diffusion layers, 2 is an insulating film represented by SiO ₂ formed on the surface of the p-type Si substrate 1, and 3 is formed on the insulating film. It is a gate electrode represented by polycrystalline Si.

The width x of the depletion layer is expressed by Equation 1. Here, Nd and Na are the donor and acceptor concentrations, ε _Si is the relative permittivity of the silicon substrate, ε ₀ is the permittivity in vacuum, V is the voltage applied to the junction, and φ is the built-in potential.

[0005]

[Equation 1]

According to this equation, it can be seen that the depletion layer extends toward the lower impurity concentration of the substrate. Therefore, in FIG. 2, the depletion layer must extend below the punch-through stopper layer in order for the depletion layer to extend from and contact with or overlap the source region 4 and the drain region 5 to cause punch-through. The presence of the layer makes it possible to suppress punchthrough.

However, in the structure shown in FIG. 2, since the punch-through stopper layer is provided over the entire lower part of the channel,
The substrate concentration increases and the threshold voltage also increases. This is because the threshold voltage is expressed by Equations 2 and 3. Here, Φms for the vacuum is the work function difference between the gate electrode and the silicon substrate, Q
f is a fixed charge, Cox is a gate insulating film capacitance per unit area, k is a Boltzmann constant, T is an absolute temperature, q is a unit charge, and ni is an intrinsic carrier density.

[0008]

[Equation 2]

[0009]

[Equation 3]

According to this equation, it can be seen that the threshold voltage increases as the substrate concentration increases.

As a result, the current in the saturation region does not increase,
High-speed operation cannot be performed, and problems such as increase in leak current at the time of off occur depending on the manufacturing method.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS transistor device in which punch-through is less likely to occur, high-speed operation is possible, and a threshold voltage can be set low.

[0013]

[Means for Solving the Problems] After forming a punch-through stopper layer, an impurity having the same polarity as that of the source / drain is introduced just below the gate and with a limited width in a region other than the source / drain, thereby forming a channel center. Partial impurity concentration is reduced. To form the impurity region, for example, ion implantation using a reverse pattern of the gate or focus ion beam is used.

[0014]

After the punch-through stopper layer is formed by a known method, before the gate electrode is formed, the reverse pattern of the gate electrode is used to compensate for the punch-through stopper layer. Dope impurities. The width of the region to be compensated is set by adjusting the width of the pattern at this time. A focus ion beam method may be used to introduce the impurities. In the latter case, the width of the compensating area is set according to the beam diameter. A high-concentration impurity region having the same conductivity type as the substrate is set around the source / drain to prevent punch-through from occurring, and the substrate concentration is effectively reduced immediately below the gate, so that the threshold voltage can be set low. Further, a desired threshold voltage can be set by adjusting the width of the region to be compensated.

[0015]

1 is a sectional view of an n-channel insulating field effect transistor according to a first embodiment of the present invention. In the figure,
1 is a p-type Si substrate, 4 and 5 are sources and drains respectively formed on the surface of the p-type Si substrate, 3 is a gate electrode made of polycrystalline Si, 7 is a channel stopper layer, 8 is an impurity of a conductivity type opposite to that of the substrate. A low-concentration channel impurity region formed by ion implantation at a concentration that compensates for the channel stopper layer 7. The source / drain and punch-through stopper layers are respectively formed on the substrate 1 by a known method to form a normal MOS transistor.

In the conventional structure shown in FIG. 2, the channel stopper layer is formed over the entire lower part of the channel, but in the present embodiment, a region having a conductivity type opposite to that of the substrate and punched just below the gate and narrower than the gate length is punched. The impurity concentration of the through stopper layer is compensated (compensate), and the impurity having the peak ion implantation depth (Rp) set to the depth giving the peak concentration of the punch through stopper layer is introduced. It's different.

FIG. 3 shows the gate length dependence of the threshold voltage according to the present invention. V with a structure provided with a punch-through stopper layer
It can be seen that the threshold value can be set low while maintaining the th-L characteristic.

FIG. 4 shows the width dependence of the impurity implantation region for controlling the threshold value. It can be seen that the threshold voltage decreases as the low-concentration impurity region just below the gate expands. In this way
It can be seen that the threshold value can be set at an arbitrary gate length by adjusting the width of the region for compensating the punch through stopper layer.

FIG. 5 shows a second embodiment of the present invention. In the first embodiment, a lightly doped drain (LDD) structure having a low concentration region in the source / drain is applied. Since the electric field relaxation at the drain end is realized in the LDD structure, the application of the present invention is not only a short channel resistance effect but also a high breakdown voltage structure, which is more effective in terms of reliability. In the figure, 12 and 13 are low-concentration diffusion layer regions in the source and drain, respectively.

FIG. 6 shows a third embodiment of the present invention. In the first embodiment, gold (GOL) is used to form the gate electrode.
D) The structure is applied. In the gold structure, the gate / drain overlap region induces more carriers on the substrate surface than in the conventional structure. Therefore, the gold structure is more effective as a short channel transistor structure than the LDD structure, and the application of the present invention is particularly effective. In the figure, 14 is a base gate electrode.

FIG. 7 shows a fourth embodiment of the present invention. In the first embodiment, the gate electrode insulating film is formed by air isolation. By applying air isolation, even if hot carrier injection occurs at the drain edge, it is not trapped, so not only punch-through resistance but also hot carrier resistance improvement is realized. In this structure, the source / drain diffusion layer is LD
It is possible to have a D structure and the gate electrode to have a GOLD structure.

FIG. 8 shows a fifth embodiment of the present invention. The fourth embodiment is applied to the second embodiment.

FIG. 9 shows a sixth embodiment of the present invention. The fourth embodiment is applied to the third embodiment.

Although the N-channel transistor is used in the first to sixth embodiments of the present invention described above, it may be applied to a p-channel transistor. In that case, all impurities may be converted from p-type to n-type and from n-type to p-type. The present invention is effective because punch-through is more remarkable in the p-channel transistor. Further, the present invention can be used to form a CMOS circuit in which an n-channel transistor and a p-channel transistor are formed on the same Si substrate. The n-channel region may be covered with photoresist when forming the p-channel, and the p-channel region may be covered with photoresist when forming the n-channel.

[0025]

According to the present invention, it is possible to prevent the transistor characteristics from being deteriorated due to punch through without newly increasing the number of masks, and it is easy to set the threshold voltage. Therefore, a highly reliable integrated circuit is provided. Can be configured.

[Brief description of drawings]

FIG. 1 is an N-channel MOS showing a first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a transistor.

FIG. 2 is a sectional view of an n-channel MOS transistor having a conventional punch-through stopper layer.

FIG. 3 is an explanatory diagram of gate length dependency of threshold voltage of the N-channel MOS transistor according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of the width (Δx) dependence of the threshold voltage of the N-channel MOS transistor of the first embodiment of the present invention and the impurity introduction region that compensates for the punch-through stopper layer.

FIG. 5 is a sectional view of an N-channel MOS transistor according to a second embodiment of the present invention.

FIG. 6 is a sectional view of an N-channel MOS transistor according to a third embodiment of the present invention.

FIG. 7 is a sectional view of an N-channel MOS transistor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view of an N-channel MOS transistor according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view of an N-channel MOS transistor according to a sixth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type Si substrate, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... Source, 5 ... Drain, 6 ... Channel, 7 ... Punch through stopper layer, 8 ... Threshold voltage control impurity region.

Claims (3)

[Claims] 1. In a MOS transistor, a punch-through stopper layer doped with an impurity of the same conductivity type as that of a substrate is provided between a source and a drain, and the width is limited to a region other than the source and the drain and directly under a gate electrode. The semiconductor device is provided with a region in which an impurity having a polarity opposite to that of the punch-through stopper layer is doped to reduce the concentration of the punch-through stopper layer just below the gate. 2. The method according to claim 1, wherein before forming the gate electrode, the pattern width is narrowed by using the reverse pattern of the gate electrode as a mask, and then impurity doping having a polarity opposite to that of the punch through stopper layer is performed. Manufacturing method of semiconductor device. 3. The focus ion according to claim 1,
A method of manufacturing a semiconductor device, which comprises using a beam method to dope impurities having a polarity opposite to that of the punch-through stopper layer.