JPH07147413A - Insulated gate transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] Insulated gate that can prevent image burning due to parasitic capacitance between gate and drain, prevent generation of defect levels due to plasma doping, and can reduce resistance of source and drain wiring. Provided are a type transistor and a manufacturing method thereof. [Structure] An insulating substrate 2, a gate 11 formed on the insulating substrate 2, and a first insulating layer 24 on the gate 11.
A second insulating layer (27 ') formed through the channel, a channel (31) of an amorphous silicon layer containing no impurities formed under the second insulating layer, and a channel containing impurities ( 31) a pair of amorphous silicon layers 32 adjacent to
And source / drain wirings 12 and 23 formed on the amorphous silicon layer containing impurities.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor applied to a liquid crystal image display device and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art Due to recent advances in microfabrication technology, liquid crystal materials, packaging technology and the like, although the size is about 3 to 15 inches, a television image and various image displays that are practically usable on a liquid crystal panel are commercially available. Already obtained in.
In addition, one of the two glass substrates forming the liquid crystal panel has an R
Color display is easily realized by forming a GB colored layer. Further, in a so-called active type liquid crystal panel in which a switching element is built in for each picture element, an image having a small crosstalk and a high contrast ratio is guaranteed.

These liquid crystal panels have only one scanning line.
A standard matrix organization is 20 to 960 lines and 240 to 2000 signal lines. For example, as shown in FIG. 15, one glass substrate 2 constituting the liquid crystal panel 1
COG (C which directly connects the semiconductor integrated circuit chip 3 which supplies a drive signal to the electrode terminal group 6 of the scanning line formed above
(Hip-On-Glass) method, or for example, a connection film 4 having a terminal group (not shown) of copper foil plated with gold based on a polyimide resin thin film as a base is pressure-bonded to an electrode terminal group 5 of signal lines with an adhesive. Meanwhile, the electric signal is supplied to the image display unit by mounting means such as a fixing method. Here, for convenience, the two mounting methods are shown at the same time,
It goes without saying that either mounting method is actually selected.

Reference numerals 7 and 8 are wiring paths for connecting the central image display portion of the liquid crystal panel 1 and the electrode terminal groups 5 and 6 of the signal lines and the scanning lines, and are necessarily the same as the electrode terminal groups 5 and 6. It need not be composed of a conductive material. Reference numeral 9 is another glass substrate having a transparent conductive counter electrode common to all liquid crystal cells, and the two glass substrates 2 and 9 are each a predetermined size of about several μm by a spacer such as quartz fiber or plastic beads. Is formed at a distance of, and the gap is a closed space sealed with a sealing material made of an organic resin and a sealing material, and the closed space is filled with liquid crystal. In order to realize color display, an organic thin film containing one or both of a dye and a pigment called a coloring layer is applied to the closed space side of the glass substrate 9 to provide a color display function. The glass substrate 9 is also called a color filter. Then, depending on the property of the liquid crystal material, a polarizing plate is attached to either the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2 or both surfaces thereof, and the liquid crystal panel 1 functions as an electro-optical element.

FIG. 16 is an equivalent circuit diagram of an active liquid crystal panel in which an insulated gate transistor 10 is arranged as a switching element for each pixel. The element drawn by the solid line is formed on one glass substrate 2, and the element drawn by the broken line is formed on the other glass substrate 9. The scanning line 11 and the signal line 12 are formed of, for example, amorphous silicon (a-S).
The TFT (thin film transistor) 10 having i) as a semiconductor layer and a silicon nitride layer (SiNx) as a gate insulating layer is formed on the glass substrate 2 at the same time. Liquid crystal cell 13
Is composed of a transparent conductive pixel electrode formed on the glass substrate 2, a transparent conductive counter electrode 15 formed on the color filter (9), and two glass substrates 2 and 9. It is composed of a liquid crystal that fills a closed space, and is electrically treated like a capacitor. With respect to the structure of the storage capacitor, several selections are possible. For example, in FIG. 16, the storage capacitor 22 is composed of the gate (scanning line) in the previous stage and the pixel electrode.

In FIG. 16, the storage capacitor 22 is not always an indispensable constituent element for an active liquid crystal panel, but the utilization efficiency of the driving signal source is improved, the stray parasitic capacitance is suppressed from being disturbed, and at the time of high temperature operation. Since it is effective in preventing image flicker (flicker), it is practically used. FIG. 17 is a cross-sectional view of main parts of the color liquid crystal image display device. As described above, the colored layer 18 made of dyed photosensitive gelatin or colored photosensitive resin corresponds to the pixel electrodes 14 on the closed space side of the color filter (9) in accordance with a predetermined arrangement in the three primary colors of RGB. It is arranged. The counter electrode 15 which is common to all the pixel electrodes 14 is formed on the coloring layer 18 as shown in order to avoid the voltage distribution loss due to the presence of the coloring layer 18. The polyimide resin thin film layer 19 having a film thickness of, for example, about 0.1 μm, which is adhered on the two glass substrates 2 and 9 in contact with the liquid crystal 16, is an alignment film for aligning liquid crystal molecules in a predetermined direction. is there. In addition, when the twisted nematic (TN) type liquid crystal 16 is used, two polarizing plates 20 are required above and below.

If a low-reflectivity opaque film 21 is arranged at the boundary of the RGB colored layers 18, reflected light from the wiring layers such as the signal lines 12 on the glass substrate 2 can be prevented and the contrast ratio can be improved. Further, it is possible to prevent an increase in the leak current at the time of OFF of the switching element 10 due to the external light irradiation, and it is possible to operate the switching element 10 even under strong external light, which is put to practical use as a black matrix. There are many possible configurations of the black matrix material, but considering the occurrence of steps at the boundaries of the colored layers and the light transmittance, the cost is high, but a Cr thin film with a thickness of about 0.1 μm is simple. is there.

Reference numeral 23 is a conductive thin film for connecting the pixel electrode 14 and the drain of the thin film transistor 10, and is generally formed of the same material as the signal line 12 at the same time. Although not shown here, the counter electrode 15 is connected to an appropriate conductive pattern on the TFT substrate 2 via an appropriate conductive paste at a corner slightly outside the image display portion, and the electrode terminal group 5 is formed. , 6 to be incorporated into a part thereof to provide electrical connection.

In order to simplify understanding in FIG. 17, the thin film transistor 10, the scanning line 11, the storage capacitor 2
2, main factors such as light source and spacer are omitted. FIG. 18 shows a typical plan pattern layout view of an insulated gate transistor which is a switching element currently adopted. Here, the storage capacitor 22 is composed of the preceding scanning line 11 ′ and the pixel electrode 14. Figure 1
19 to 24 are sectional views of the manufacturing process on the line AA ′ of FIG.
The manufacturing process of the liquid crystal image display TFT substrate including the insulated gate transistor will be described below.

First, as shown in FIG. 19, the glass substrate 2
A metal layer (11) also serving as a gate electrode of the insulated gate transistor and a scanning line is formed on one main surface of the chrome (C) film having a thickness of 0.1 μm by using a vacuum film forming apparatus such as sputtering.
In step r), deposition is performed to perform selective pattern formation. Next, as shown in FIG. 20, a first silicon nitride layer (SiNx) to be the gate insulating layer 24 and a first silicon nitride layer containing almost no impurities are formed.
Amorphous silicon (a-Si) layer 25 and a second silicon nitride layer (SiNx) serving as an etching stopper
27 three layers in order, for example, 0.4 μm, 0.05 μm,
A film having a thickness of 0.1 μm is continuously deposited using a plasma CVD apparatus.

Then, as shown in FIG. 21, the gate 11
The second SiNx layer which is thinner than the gate 11 is selectively left to be 27 ', and the first amorphous silicon layer 25 containing no impurities is exposed. Then, for example, phosphorus (P) is used as an impurity on the entire surface. The second amorphous silicon layer 26 containing is deposited on the entire surface with a film thickness of, for example, 0.05 μm using a plasma CVD apparatus.

Subsequently, as shown in FIG. 22, the gate 11
The above-mentioned two amorphous silicon layers are selectively formed in the shape of an island in the upper periphery to form 25 'and 26', and the gate insulating layer 24 is exposed. Further, although this position is not always the optimum position in the manufacturing process, it can be set to 0.1 by using a vacuum film forming apparatus such as sputtering.
A transparent conductive ITO film having a thickness of μm is deposited and a selective pattern is formed to form a pixel electrode 14.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line 11, and then the opening is formed as shown in FIG. Including, for example, 0.1 μm thick chromium (Cr) and 0.
A gate wiring (not shown) consisting of two layers of aluminum (Al) having a film thickness of 5 μm and a pair of source / drain wiring 1
2, 23 are selectively deposited so as to partially overlap with the second SiNx layer 27 ', and as shown in FIG. The second amorphous silicon layer 26 'is selectively removed to complete the insulated gate transistor. At this time, the first amorphous silicon layer 25 'which is not covered by the source / drain wiring disappears due to over-etching of the second amorphous silicon layer 26', but the second SiNx layer 27 'is removed. Has a function of protecting the amorphous silicon layer 25 'which does not contain impurities which becomes a channel of the insulated gate transistor against over-etching of the amorphous silicon layer 26', and is therefore called an etching stopper. It

In the manufacturing method described above, the two types of amorphous silicon layers 25 'and 26' are formed in an island shape to expose the gate insulating layer 24, and thereafter, for connecting to the gate (scan line). The opening of the amorphous silicon layer 2 is formed in order to shorten the manufacturing process (particularly the photolithography process).
It is also possible to form the above-mentioned opening by etching a multilayer of two kinds of amorphous silicon layers 25 and 26 and the gate insulating layer 24 at once without forming the islands 5 and 26. Although the formation of the opening becomes slightly complicated by etching the multilayer film, and there is no industrial problem that the cross-sectional shape of the opening tends to become an inverse taper unless dry etching is adopted, but it is not amorphous. This is because the step of forming the silicon layers 25 and 26 in an island shape can be omitted. However, in the latter case, in consideration of the opacity of the amorphous silicon layer, after removing the unnecessary amorphous silicon layer between the wirings by using the gate wiring and the source / drain wirings 12 and 23 as a mask, or 3
It will be easily understood that the pixel electrode 14 is formed before forming the layer, that is, before forming the gate insulating layer 24.

In this conventional example, the storage capacitor 22 has a structure in which the scanning line 11 'and the pixel electrode 14 in the preceding stage are used as electrodes and the gate insulating layer 24 is used as an insulator. Further, in order to improve the reliability of the active liquid crystal panel, it is general to form a transparent insulating layer such as SiNx, which secures a passivation function after the completion of the above-mentioned insulated gate transistor, on the entire surface. Is omitted.
Further, in order to improve the heat resistance of the insulated gate transistor, Cr is introduced as a heat resistant barrier metal between the source / drain wirings 12 and 23 and the amorphous silicon layer 26 'containing impurities. Also Ti (titanium)
A metal thin film layer such as a metal thin film layer or a silicide thin film layer is often adopted. Details of the heat-resistant barrier metal technology are also omitted here.

[0016]

In the insulated gate transistor introduced as a prior example, since the source / drain wiring is formed so as to partially overlap the gate in a plane, it is parasitic on the gate / source and the gate / drain. Capacity is generated. Moreover, since the degree of overlap is determined by the alignment accuracy in the exposure process, when the screen size increases,
It is not uncommon for the total alignment accuracy to reach several μm due to restrictions such as 1) mask accuracy, 2) alignment accuracy of the exposure device, 3) thermal contraction and thermal expansion of the glass substrates 2 and 9. The parasitic capacitance between the gate and the source increases the signal line capacitance, resulting in an increase in power consumption, and the parasitic capacitance between the gate and the drain modulates the potential of the pixel electrode with a gate pulse to print an image or to expose a device. If a stepper is used as a screen joint, all of them will cause serious quality defects. Therefore, along with the improvement of the aperture ratio for securing a bright screen, a self-aligned TFT with a small parasitic capacitance is desired. ing.

FIG. 25 is a plan pattern layout diagram of an insulated gate transistor developed for the purpose of reducing parasitic capacitance. Here again, the storage capacitor 22 is the scanning line 11 'of the preceding stage.
And the picture element electrode 14. BB 'in FIG. 25
26 to 33 are sectional views showing the manufacturing process along the line, and the TFT for liquid crystal image display including the insulated gate type transistor
The manufacturing process of the substrate will be described below.

First, as shown in FIG. 26, the glass substrate 2
A metal layer (11) also serving as a gate electrode of the insulated gate transistor and a scanning line is formed on one main surface of the chrome (C) film having a thickness of 0.1 μm by using a vacuum film forming apparatus such as sputtering.
In step r), deposition is performed to perform selective pattern formation. Next, as shown in FIG. 27, the first silicon nitride layer (SiNx) to be the gate insulating layer 24 and the first silicon nitride layer containing almost no impurities are formed.
Amorphous silicon (a-Si) layer 25, and a second silicon nitride layer (SiNx) 27 serving as an etching stopper.
Of the three layers in order, for example, 0.4 μm, 0.05 μm, 0.
A film having a thickness of 1 μm is continuously deposited using a plasma CVD apparatus. Up to this point, the manufacturing process is the same as that of the preceding example.

Then, as shown in FIG. 28, after the positive type photosensitive resin 28 is applied on the entire surface, the back surface of the glass substrate 2 is exposed to ultraviolet rays 29, and the upper surface of the glass substrate 2 is exposed to a normal photomask. Is used together with the exposure. After the development of the photosensitive resin 28, as shown in FIG.
It is possible to obtain an island-shaped photosensitive resin pattern 28 'having a width slightly smaller than the gate pattern by about 0.5 to 1 .mu.m corresponding to the pattern 1.

The island-shaped photosensitive resin pattern 28 'is subsequently used as a mask to make the second S thinner on the gate 11 than on the gate.
After selectively removing the iNx layer to 27 ', exposing the first amorphous silicon layer 25 containing no impurities and removing the photosensitive resin pattern 28', as shown in FIG.
The entire surface is irradiated with a plasma beam 30 containing, for example, phosphorus (P) as an impurity. At this time, the etching / stopper layer 27 'functions as a mask, and the amorphous silicon 25 layer containing no impurities becomes the amorphous silicon layer 31 containing no impurities and the amorphous silicon layer 32 containing impurities.
It is unnecessary to explain that the amorphous silicon layer 31 containing no impurities constitutes the channel of the insulated gate transistor.

After that, as shown in FIG.
The high melting point metal layer 33 to be the drain electrode is deposited on the entire surface with a thickness of, for example, 0.1 μm using a vacuum film forming apparatus such as sputtering, and left in a clean oven to leave the glass substrate 2
Heating. By this substrate heating, the metal layer 33 forms silicide with the amorphous silicon layer 32 containing impurities at a temperature of 200 ° C. or higher, but does not react with the SiNx layer 27 ′ that is an etching stopper. After the heat treatment is completed, the metal layer 33 is entirely removed by using an etching solution, so that the silicide layer 34 is selectively formed only on the amorphous silicon layer 32 containing impurities. As described above, the metal layer 33 is made of a metal having a relatively high heat resistance, such as tantalum, tungsten, molybdenum, chromium, or titanium, which is alloyed with amorphous silicon to form a silicide.

Further, two layers of the silicide layer 34 and the amorphous silicon layer 32 containing impurities are formed as shown in FIG.
34 'by selectively forming an island shape around the gate 11
a, 34'b, 32 ', and the gate insulating layer 24 is exposed. Although this position is not necessarily the optimum position in the manufacturing process, it can be adjusted to 0.1 μm by using a vacuum film forming apparatus such as sputtering.
A transparent conductive ITO film having a film thickness of m is deposited and a selective pattern is formed to form a pixel electrode 14. At this time, since one of the island-shaped drain electrodes 34'a has already been silicided to have a low resistance, there is no problem even if the pixel electrode 14 is formed to include the drain electrode 34'a.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line 11, and then the opening is formed as shown in FIG. Including aluminum, for example, with a film thickness of 0.5 μm (A1)
The gate wiring (not shown) and the source wiring 12 are selectively deposited and formed including the other island-shaped source electrode 34'b to complete the insulated gate transistor.

The reason why the gate wiring and the source / drain wiring may be a single aluminum layer is that the surface of the amorphous silicon layer 32 containing impurities is silicided.
This is because there is no possibility that aluminum penetrates through the silicide layer and reacts with the lower impurity-containing region of the amorphous silicon layer 32 containing impurities to impair the ohmic characteristics between the source and drain. That is, the heat resistance of the insulated gate transistor is improved.

As in the prior art, the picture element electrode 14 has an independent pattern, and the drain wiring 23 is used to form the drain electrode 3.
There is no problem in connecting 4'a and the pixel electrode 14. In order to reduce the parasitic capacitance, it goes without saying that the source / drain wirings 12 and 23 are formed to include the source / drain electrodes 34'a and 34'b so as not to overlap the gate 11 in plan view. .

Similarly, without forming the silicide layer and the amorphous silicon layer containing impurities in an island shape for the purpose of shortening the manufacturing process (in particular, the photo-etching process), the amorphous layer containing the silicide layer and impurities is formed. It is also possible to etch the multiple layers of the silicon layer and the gate insulating layer at once to form an opening for connection to the scan line. In the latest insulated gate transistor described above, an impurity is injected into an amorphous silicon layer containing no impurities by plasma doping, a metal layer to be source / drain electrodes by substrate heating, and impurities are injected by the plasma doping. The present invention provides a method for manufacturing a self-aligned transistor, which has two new technologies for forming a low temperature silicide with an amorphous silicon layer as a core.

However, the impurities implanted by the plasma doping are naturally also implanted in the etching stopper layer 27 ', and many defect levels are generated.
Even if the initial operation is normal, for a long-term operation, electrons are trapped in the defect level, the threshold voltage of the insulated gate transistor starts to increase, and the ON current may decrease. found.

In order to suppress the generation of defect levels, the etching that acts as a mask against the implantation of impurities.
Whether to thicken the stopper layer, or to leave the photosensitive resin pattern used to form an appropriate metal thin film layer or etching stopper layer as it is in order to further enhance the mask function on the etching stopper layer. , Either measure is required.

The formation of a thick etching stopper layer leads to a reduction in tact of the plasma CVD apparatus and dust generation, and if it is attempted to avoid it, an additional reaction chamber for forming the etching stopper layer is required, resulting in equipment cost. Rises. The adoption of the metal thin film layer for strengthening the mask function leads to the addition of a film forming device and an etching device for the thin film layer, which also raises the equipment cost.

If the photosensitive resin pattern is left as it is and is used as a mask, a large amount of impurities deteriorate the photosensitive resin pattern, and oxygen plasma is used to remove the photosensitive resin pattern. The decomposition rate is low, the removal is long, and secondary defect levels are generated by oxygen plasma irradiation, and a large amount of oxygen is introduced into the amorphous silicon layer 32 containing exposed impurities. The side effect such as the plasma injection lowers the electrical properties of the amorphous silicon layer 32.

Although it is low temperature silicide formation,
The heating of the substrate at ℃ or more leads to the release of hydrogen from the amorphous silicon layers 31 and 32, and although there is a difference depending on the film quality, it is not possible to use the heating for a long time or at 250 ℃ or more in order to reduce the resistance. Bring In other words, it has also been found that there is a limit to reducing the resistance. Therefore, an object of the present invention is to prevent the image burning due to the parasitic capacitance between the gate and the drain, prevent the generation of the defect level due to the plasma doping, and further reduce the resistance of the source and drain wiring. A gate type transistor and a method for manufacturing the same are provided.

[0032]

According to another aspect of the present invention, there is provided an insulated gate transistor including an insulating substrate, a gate formed on one main surface of the insulating substrate, and a first insulating layer on the gate. A second insulating layer which is thinner than the gate and is formed in a self-aligned manner, and a channel of an amorphous silicon layer which does not contain impurities and which is formed in a self-aligned manner with the gate below the second insulating layer, A pair of amorphous silicon layers containing impurities and adjacent to the channel, and source / drain wirings formed in a self-aligned manner on the amorphous silicon layers containing these impurities are provided.

The insulated gate transistor according to claim 2 is
In the first aspect, the source / drain wiring is wired to the source / drain electrodes formed in a self-aligned manner on the amorphous silicon layer containing impurities. According to another aspect of the present invention, there is provided an insulated gate transistor, wherein an insulating substrate, a gate formed on one main surface of the insulating substrate, and a first insulating layer formed on the gate are thinner than the gate and are self-aligned. A second insulating layer formed on the second insulating layer, a channel of an amorphous silicon layer containing no impurities formed under the second insulating layer in a self-aligned manner with the gate, and a pair of channels including impurities and adjacent to the channel. The amorphous silicon layer and the source / drain wiring which is formed in a self-aligned manner on the surface of the amorphous silicon layer containing these impurities and is silicided.

The insulated gate transistor according to claim 4 is
In the third aspect, the source / drain wiring is wired to the source / drain electrodes formed in a self-aligned manner on the amorphous silicon layer containing impurities. The method for manufacturing an insulated gate transistor according to claim 5, wherein a step of selectively forming a first metal layer to be a gate on one main surface of the insulating substrate, a first insulating layer to be a gate insulating layer, A step of sequentially depositing an amorphous silicon layer containing no impurities and a second insulating layer, a step of applying a negative photosensitive resin on the second insulating layer, and another main surface of the insulating substrate. Forming a photosensitive resin pattern having an opening smaller than the gate in the gate, including exposure from above, depositing a lift-off layer made of metal on the entire surface including the opening, and removing the photosensitive resin With the second lift-off layer in the opening
Selectively leaving the lift-off layer on the insulating layer, the step of selectively removing the second insulating layer by using the lift-off layer left selectively as a mask to expose the amorphous silicon layer, and the mask of the lift-off layer. As a step of selectively implanting impurities into the amorphous silicon layer by plasma doping to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer, and a second metal layer over the entire surface. And at least one of the silicide layer and the lift-off layer are removed, and at the same time, the second metal layer or the silicide layer and the amorphous silicon layer containing impurities are selectively removed to remove a pair of impurities adjacent to the channel. Forming an amorphous silicon layer and forming source / drain wirings on the amorphous silicon layer.

According to a sixth aspect of the present invention, in the method of manufacturing an insulated gate transistor according to the fifth aspect, the insulating substrate is one of the substrates for the liquid crystal display device, the gate also serves as a scanning line, and the other substrate of the liquid crystal display device is the other. As a mask, the first insulating layer at the end of the scanning line is removed. The method of manufacturing an insulated gate transistor according to claim 7, wherein a step of selectively forming a first metal layer to be a gate on one main surface of the insulating substrate, a first insulating layer to be a gate insulating layer, A step of sequentially depositing an amorphous silicon layer containing no impurities and a second insulating layer, a step of applying a negative photosensitive resin on the second insulating layer, and another main surface of the insulating substrate. Forming a photosensitive resin pattern having an opening smaller than the gate in the gate, including exposure from above, depositing a lift-off layer made of metal on the entire surface including the opening, and removing the photosensitive resin At the same time, the step of selectively leaving the lift-off layer in the opening on the second insulating layer, and the second insulating layer is selectively removed by using the lift-off layer left selectively as a mask to form an amorphous silicon layer. And the lift-off layer as a mask A step of selectively implanting impurities into the amorphous silicon layer by plasma doping to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer; After depositing at least one of the silicide layers, the lift-off layer is removed, and at the same time, the second metal layer or the silicide layer and the amorphous silicon layer containing impurities are selectively removed to remove a pair of non-doped impurities adjacent to the channel. It includes the steps of forming a crystalline silicon layer and forming source / drain electrodes on the amorphous silicon layer, and forming source / drain wirings on the source / drain electrodes.

The method of manufacturing an insulated gate transistor according to claim 8 comprises the step of selectively forming a first metal layer to be a gate on one main surface of the insulating substrate, and the first metal layer to be a gate insulating layer. A step of sequentially depositing an insulating layer, an amorphous silicon layer containing no impurities, and a second insulating layer; a step of applying a negative photosensitive resin on the second insulating layer; A step of forming a photosensitive resin pattern having an opening smaller than the gate in the gate, including the exposure from the main surface of the substrate, and a lift-off layer made of a second metal capable of forming silicide on the entire surface including the opening. The step of depositing, the step of selectively leaving the lift-off layer of the opening on the second insulating layer together with the removal of the photosensitive resin, and the step of selectively leaving the lift-off layer as a mask to select the second insulating layer. Exposed to expose amorphous silicon layer And a step of selectively implanting impurities into the amorphous silicon layer by plasma doping using the lift-off layer to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer. Forming a silicide layer containing a second metal layer component on the amorphous silicon layer containing impurities by depositing the same metal layer as the second metal layer on the entire surface and then heating the insulating substrate; Layer and an amorphous silicon layer containing impurities are selectively removed to form a pair of amorphous silicon layers containing impurities adjacent to the channel, and source / drain wirings are formed on the amorphous silicon layer. And the step of performing.

According to a ninth aspect of the present invention, there is provided a method of manufacturing an insulated gate transistor according to the eighth aspect, wherein the insulating substrate is one of the liquid crystal display device substrates, the gate also serves as a scanning line, and the other of the liquid crystal display device substrates is used. As a mask, the first insulating layer at the end of the scanning line is removed. The method for producing an insulated gate transistor according to claim 10, wherein a step of selectively forming a first metal layer to be a gate on one main surface of the insulating substrate, a first insulating layer to be a gate insulating layer, A step of sequentially depositing an amorphous silicon layer containing no impurities and a second insulating layer, a step of applying a negative photosensitive resin on the second insulating layer, and another main surface of the insulating substrate. A step of forming a photosensitive resin pattern having an opening smaller than the gate in the gate, including the exposure from above, and depositing a lift-off layer made of a second metal capable of forming silicide on the entire surface including the opening. A step of selectively removing the photosensitive resin and leaving the lift-off layer at the opening on the second insulating layer, and selectively removing the second insulating layer using the lift-off layer left selectively as a mask And exposing the amorphous silicon layer
A step of selectively implanting impurities into the amorphous silicon layer by plasma doping using the lift-off layer to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer, and a step of forming a channel over the entire surface. A step of heating the insulating substrate after depositing the same metal layer as the second metal layer to form a silicide layer containing a second metal layer component on the amorphous silicon layer containing impurities; Selectively removing the containing amorphous silicon layer to form a pair of amorphous silicon layers containing impurities adjacent to the channel, and forming source / drain electrodes on the amorphous silicon layer; And a step of forming source / drain wirings on the source / drain electrodes.

[0038]

According to the insulated gate transistor of the first aspect, the first insulating layer for protecting the channel is formed in a self-aligned manner by backside exposure using, for example, a gate pattern, and on the amorphous silicon layer containing impurities. Similarly, the planar overlap between the source / drain wiring and the gate formed in self-alignment is 1μ regardless of the size of the device.
Since a value of m or less can be realized, it is possible to substantially eliminate image burning due to the parasitic capacitance between the gate and the drain.

According to the insulated gate type transistor of claim 2, in claim 1, the source / drain wiring is wired to the source / drain electrode formed in a self-aligned manner on the amorphous silicon layer containing impurities. Therefore, the resistance of the source / drain wiring can be reduced, and the increase in the resistance value can be easily reduced even if the wiring becomes long. According to the insulated gate transistor of the third aspect, the silicided source / drain wiring is formed in a self-aligned manner on the amorphous silicon layer containing impurities. Resistance can be realized.

According to the insulated gate transistor of the fourth aspect, since the source / drain wiring is formed on the source / drain electrode silicided on the amorphous silicon layer containing impurities, in addition to the function of the third aspect. Further lower resistance can be achieved. According to the insulated gate transistor of claim 5, since the metal lift-off layer exerts a sufficient masking function for plasma doping, a defect is present in the second insulating layer serving as an etching stopper layer on the channel. A metal layer or a silicide layer to be a source / drain wiring can be formed in a self-aligned manner on an amorphous silicon layer containing impurities by generating no levels and by selective removal using a lift-off layer. The heat treatment for reducing the resistance of the wiring can be omitted, and the amorphous silicon layer is not deteriorated by excessive heating.

According to the method of manufacturing an insulated gate transistor of claim 6, the exposed portion is formed by removing the gate insulating layer in the peripheral portion of the substrate using the counter substrate as a mask in a liquid crystal panel state. Since the ends of the scanning lines can be used as electrode terminals, the manufacturing process can be rationalized. According to the method of manufacturing an insulated gate transistor of claim 7, the source / drain layer is formed of a metal layer or a silicide layer deposited or formed on an amorphous silicon layer containing impurities, which has the same function as that of claim 2.
Since the drain electrode is formed in a self-aligned manner, it is not necessary to selectively etch the amorphous silicon layer containing impurities using the source / drain wiring as a mask as in the conventional case.

According to the method of manufacturing an insulated gate transistor of claim 8, the source / drain wiring of the silicide layer of the same metal as the lift-off layer is formed on the amorphous silicon layer containing impurities. It has the same effect as that of claim 5. According to the method for manufacturing an insulated gate transistor of claim 9, in the method of claim 8, the manufacturing process can be rationalized similarly to the operation of claim 6.

According to the method of manufacturing an insulated gate transistor of claim 10, the source / drain electrodes of the silicide layer of the same metal as the lift-off layer are formed on the amorphous silicon layer containing impurities, and the source / drain wiring is formed. Since it is formed, the resistance is further reduced in addition to the same effect as in the eighth aspect.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. For the sake of convenience, the same parts are given the same numbers as in the conventional example. First, as shown in FIG. 2, a metal layer (11) also serving as a gate 11 of an insulated gate transistor and a scanning line is formed on one main surface of a glass substrate 2 which is an insulating substrate, for example, a vacuum film forming apparatus such as a sputtering device. Is used to form a selective pattern by depositing chromium (Cr) having a film thickness of 0.1 μm.

Next, as shown in FIG. 3, a silicon nitride layer (SiN) which becomes the gate insulating layer 24 which is the first insulating layer is formed.
x), amorphous silicon containing almost no impurities (a-S
i) A layer 25 and a silicon nitride layer (SiNx) 27, which is a second insulating layer serving as an etching stopper, are provided in a plasma CVD apparatus with a film thickness of 0.4 μm, 0.05 μm, and 0.1 μm, for example. Used to deposit continuously. Up to this point, the manufacturing process is the same as that of the preceding example.

Then, as shown in FIG. 4, after the negative type photosensitive resin 35 is applied to the entire surface, ultraviolet rays 29 are irradiated from the back surface of the glass substrate 2 and a normal photomask is applied from the upper surface of the glass substrate 2. The exposure used is used in combination. After the development of the photosensitive resin 35, as shown in FIG. 5, the pattern corresponding to the pattern of the gate 11 is slightly smaller than the gate pattern by 0.5.
A photosensitive resin pattern 35 'having an opening 36 with a narrow width of about 1 .mu.m is obtained.

Subsequently, as a lift-off layer, a molybdenum film having a thickness of 0.2 to 0.3 μm, for example, is deposited on the entire surface by using a vacuum film forming apparatus such as sputtering to dissolve the photosensitive resin pattern 35 '. If the photosensitive resin pattern 35 ′ has a thickness of 1 μm or more when left in a liquid that decomposes, it is sufficiently thicker than the lift-off layer. Therefore, as shown in FIG. 6, the lift-off layer is formed on the second insulating layer 27. 37 can be formed in self-alignment with the gate 11. Further, the second insulating layer 27 is selectively etched to 27 'by using the lift-off layer 37 as a mask, and the amorphous silicon layer 25 containing no impurities is formed.
After the exposure, the entire surface is irradiated with a plasma beam 30 containing, for example, phosphorus (P) as an impurity as shown in FIG. At this time, the lift-off layer 37 and the etching stopper layer 27 'function as a mask, and impurities are selectively implanted into the amorphous silicon layer 25 containing no impurities to obtain the amorphous silicon layer 32 containing impurities. The amorphous silicon layer 31 containing no impurities remains under the etching stopper layer 27 '.

After that, as shown in FIG. 8, a vacuum metallization apparatus is used, for example, chromium or titanium or a silicide layer containing molybdenum or tungsten is formed on the entire surface as the third metal layer 38 to be the source / drain wiring. Using 0.0
It is deposited with a film thickness of 5 to 0.1 μm. Since the third metal layer or the silicide layer 38 is thinner than the lift-off layer 37, the lift-off layer 37 made of molybdenum is left in the nitric acid solution and the third metal layer or the silicide layer 38 on the lift-off layer 37 is removed. It is extremely easy to remove selectively. The lift-off layer 37 is not necessarily limited to molybdenum, as long as it can exhibit a mask function effective for plasma doping and can be removed by a simple method.

Then, as shown in FIG. 1, the pair of source wirings 12 is selectively left with the two layers of the third metal layer or the silicide layer 38 and the amorphous silicon layer 32 containing impurities selectively left.
And the drain wiring 23, and the gate insulating layer 24 is exposed. Continue to 0.1μ by using vacuum film forming equipment such as sputtering.
A transparent conductive ITO film having a thickness of m is deposited to selectively form a pattern, and a pixel electrode 14 including a drain electrode is formed. At this time, since the drain electrode is low-resistance titanium, chromium, or silicide, there is no problem even if the pixel electrode 14 is formed to include the drain electrode of the drain wiring 23.

After that, although not shown, the gate insulating layer 24 on the end of the scanning line 11 is selectively removed to expose the end of the scanning line 11 to form the electrode terminal 6 of the scanning line. The first embodiment of the invention is completed. As described above, the insulated gate transistor of the first embodiment has the glass substrate 2 which is an insulating substrate, the gate 11 formed on one main surface of the glass substrate 2, and the first gate 11 formed on the gate 11. Second insulating layer, which is thinner than the gate 11 and is formed in a self-aligned manner via the gate insulating layer 24 which is the insulating layer of
And an amorphous silicon layer 31 containing no impurities formed under the silicon nitride layer 27 in a self-aligned manner with the gate 11.
Channel, a pair of amorphous silicon layers 32 containing impurities and adjacent to the channel, and source / drain wirings 12, 23 formed on the amorphous silicon layer 32 containing these impurities in a self-aligned manner. Since the gate insulating layer 11 for protecting the channel is formed in a self-aligned manner by backside exposure using the gate pattern, the source insulating layer 11 is also formed in a self-aligned manner on the amorphous silicon layer 32 containing impurities. The planar overlap between the drain wirings 12 and 23 and the gate 11 can achieve a value of 1 μm or less regardless of the size of the device, so that image burning due to the parasitic capacitance between the gate and the drain is virtually eliminated. It becomes possible.

According to the manufacturing method of the first embodiment,
Since the metal lift-off layer 37 exerts a sufficient mask function for plasma doping, it does not generate a defect level in the etching stopper layer 27 on the channel, and the lift-off layer 37 selectively removes it. As a result, a metal layer or a silicide layer to be the source / drain wirings 12 and 23 can be formed in a self-aligned manner on the amorphous silicon layer 32 containing impurities.
The heat treatment for reducing the resistance of Nos. 2 and 23 can be omitted, and the amorphous silicon layer is not deteriorated by excessive heating.

Further, by removing the gate insulating layer at the peripheral portion of the substrate using the counter substrate as a mask in a liquid crystal panel state, the exposed end portions of the scanning lines can be used as electrode terminals. Rationalization can be realized. As a modified example of the first embodiment, pattern formation using an exposure machine is not adopted for the selective removal of the gate insulating layer 24 for obtaining the electrode terminals 6, and a counter substrate or a color filter is formed in a liquid crystal panel state. TFT using (9) as a mask
By removing the gate insulating layer 24 in the peripheral portion of the glass substrate 2 where 10 is present, the rationalization of the manufacturing process in which the exposed end portion of the scanning line 11 is used as the electrode terminal 6 is realized.

Second embodiment of the present invention FIG. 9 and FIG.
A description will be given based on 0. That is, FIG. 8 of the first embodiment.
Up to this, the same process as in the first embodiment is performed. Then, after removing the lift-off layer 37, as shown in FIG.
Two layers, that is, the third metal layer or the silicide layer 38 and the amorphous silicon layer 32 containing impurities are selectively removed to form the island-shaped 3
2 ', 38'a (drain electrode) and 38'b (source electrode) are formed to expose the gate insulating layer 24. As described above, this position is not always optimal in the manufacturing process, but a transparent conductive ITO film having a film thickness of 0.1 μm is deposited using a vacuum film forming apparatus such as sputtering to selectively form a pattern. , The pixel electrode 14 is formed. At this time, since the drain electrode 38'a has low resistance such as titanium, chromium, or silicide, there is no problem even if the pixel electrode 14 is formed to include the drain electrode 38'a.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line 11, and then the opening is formed as shown in FIG. Wiring on the gate insulating layer 24 including (not shown)
And the source wiring 12 on the gate insulating layer 24 including the source electrode 38′b are selectively formed by wiring made of aluminum (Al) having a film thickness of 0.5 μm, for example. The insulated gate transistor according to the embodiment is completed.

In the first embodiment, since the source / drain wirings 12 and 23 are made of titanium, chromium or silicide, the wiring becomes longer as the device size becomes larger and the resistance value is prevented from increasing. Absent. On the other hand, in the second embodiment, the source / drain electrode 3
Since the source / drain wirings 12 and 23 are formed on 8'a and 38'b, it is possible to propose a device structure and a manufacturing method in which the resistance values of the source / drain wirings 12 and 23 can be easily lowered.

When aluminum is used to reduce the resistance of the wiring and a conventional barrier metal is used for the third metal layer 38, an amorphous silicon layer 32 containing impurities is formed by plasma doping. On the gate insulating layer 2
Since it is not necessary to implant a sufficiently large amount of impurities up to the boundary surface with 4, it is possible to optimize the implantation amount of plasma doping to a minimum and avoid waste of excessive implantation.

A third embodiment of the present invention will be described with reference to FIGS. 11 and 12. That is, the low-temperature silicide forming method is used for forming the source / drain wiring or the source / drain electrodes instead of the lift-off layer. First, the first embodiment up to FIG. 7 is the same as the first and second embodiments. However, there is a difference that the lift-off layer 37 must be a metal capable of forming a silicide, for example, a refractory metal such as molybdenum, tungsten, tantalum, chromium, or titanium.

Subsequently, as shown in FIG. 11, as the third metal layer 33 to be the source / drain wiring, the same metal layer as the lift-off layer 37 is formed on the entire surface by 0.05 to 0 using a vacuum film forming apparatus. Deposition with a film thickness of 1 μm. Then, the substrate 2 is heat-treated at a temperature of 200 ° C. or higher using a heating device or means such as a clean oven. By this substrate heating, the third metal layer 33 forms a silicide with the amorphous silicon layer 32 containing impurities at a temperature of 200 ° C. or higher, while the SiNx layer 2 serving as an etching stopper is formed.
Since it does not react with 7 ', if it is completely removed by using an etching solution that dissolves the lift-off layer 37 and the metal layer 33 after the heat treatment, only the silicide layer 34 is formed on the amorphous silicon layer 32 containing impurities. Are selectively formed.

Then, as shown in FIG. 12, a pair of source wiring 12 (34'b) and drain wiring 23 (leaving the silicide layer 34 and the amorphous silicon layer 32 containing impurities selectively left). 34'a), and the gate insulating layer 24 is exposed. Subsequently, using a vacuum film-forming apparatus such as sputtering, transparent conductive ITO having a film thickness of 0.1 μm is deposited to selectively form a pattern, and the pixel electrode 14 including the drain electrode 23 is formed.

After that, although not shown, the gate insulating layer 24 on the end of the scanning line 11 is selectively removed to expose the end of the scanning line 11 and form the electrode terminal 6 of the scanning line. The third embodiment of the invention is completed. As a modified example of the third embodiment, pattern formation using an exposure machine is not adopted for the selective removal of the gate insulating layer 24 for obtaining the electrode terminals 6, and a counter substrate or a color filter is formed in a liquid crystal panel state. 9
Using the mask as a mask, the gate insulating layer 2 around the TFT substrate 2
By removing 4, the rationalization of the manufacturing process in which the exposed end of the scanning line 11 is used as the electrode terminal 6 is realized.

A fourth embodiment of the present invention will be described with reference to FIGS. 13 and 14. That is, in the fourth embodiment, the same process as that of the third embodiment is performed up to FIG. Then, after the silicide layer 34 is selectively formed,
As shown in FIG. 13, two layers of a silicide layer 34 and an amorphous silicon layer 32 containing impurities are selectively formed to form an island shape 3
4 '(34'a, 34'b), 32', and the gate insulating layer 24 is exposed. As described above, this position is not always optimal in the manufacturing process, but a transparent conductive ITO film having a film thickness of 0.1 μm is deposited using a vacuum film forming apparatus such as sputtering to selectively form a pattern. , The pixel electrode 14 is formed. At this time, the island-shaped drain electrode 34'a
Is a low-resistance silicide, so there is no problem even if the pixel electrode 14 is formed to include the drain electrode 34'a.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line which also serves as the gate 11, and then, as shown in FIG. A gate wiring (not shown) on the gate insulating layer 24 including the opening and the gate insulating layer 2 including the source electrode 34'b.
The source wiring 12 on 4 is selectively formed by a wiring made of aluminum (Al) having a film thickness of 0.5 μm, for example, to complete the insulated gate transistor according to the fourth embodiment of the present invention.

In the third embodiment, since the source / drain wirings 12 and 23 are composed of an amorphous silicon layer whose surface is silicidized, the wiring becomes longer and the resistance increases as the device size increases. Increasing value is inevitable. On the other hand, in the fourth embodiment, it is possible to propose a device structure and a manufacturing method in which the resistance value of the source / drain wiring can be easily lowered similarly to the second embodiment.

In the pattern in which the picture element electrode 14 is independent as in the conventional example, the drain wiring 23 is used to form the drain electrode 3.
There is no problem in connecting 8'a or 34'a to the pixel electrode 14. Similarly, the metal layer or the silicide layer and the impurities are removed from each other without forming the metal layer or the silicide layer and the impurity-containing amorphous silicon layer in an island shape in order to shorten the manufacturing process (in particular, the photo-etching process). It is also possible to form an opening for connection to the scan line by etching the multilayer film including the amorphous silicon layer containing the film and the gate insulating layer at once.

[0065]

According to the insulated gate transistor of the first aspect, the first insulating layer for protecting the channel is formed in a self-aligned manner by backside exposure using, for example, a gate pattern, and contains amorphous silicon containing impurities. The planar overlap between the source / drain wiring and the gate, which are also formed on the layer in a self-aligned manner, can achieve a value of 1 μm or less regardless of the size of the device. There is an effect that it is possible to substantially eliminate the baking.

According to the insulated gate transistor of claim 5, since the metal lift-off layer exerts a sufficient masking function for plasma doping, the second insulating layer serving as an etching stopper layer on the channel is formed. Since a defect level is not generated inside, and a metal layer or a silicide layer to be a source / drain wiring can be formed in a self-aligned manner on an amorphous silicon layer containing impurities by selective removal using a lift-off layer. The heat treatment for reducing the resistance of the source / drain wiring can be omitted, and the amorphous silicon layer is not deteriorated by excessive heating.

According to the method of manufacturing an insulated gate transistor of claim 6, in the method of claim 5, the gate insulating layer in the peripheral portion of the substrate is removed by using the counter substrate as a mask in the state of being made into a liquid crystal panel. Since the ends of the scanning lines can be used as electrode terminals, the manufacturing process can be rationalized. According to the insulated gate transistor of claim 2, in claim 1, the source / drain wiring is wired to a source / drain electrode formed in a self-aligned manner on an amorphous silicon layer containing impurities. Therefore, the resistance of the source / drain wiring can be reduced, and the increase of the resistance value can be easily reduced even if the wiring becomes long.

According to the method of manufacturing an insulated gate transistor of claim 7, the same effect as that of claim 2 can be obtained, and a method of manufacturing a metal layer or a silicide layer deposited or formed on an amorphous silicon layer containing impurities can be used. Since the source / drain electrodes are formed in a self-aligned manner, it is not necessary to selectively etch the amorphous silicon layer containing impurities using the source / drain wiring as a mask as in the conventional case.

According to the insulated gate transistor of the third aspect, the silicided source / drain wiring is formed in a self-aligned manner on the amorphous silicon layer containing impurities. Besides, low resistance can be realized. According to the method of manufacturing an insulated gate transistor of claim 8, since the source / drain wiring of the silicide layer of the same metal as the lift-off layer is formed on the amorphous silicon layer containing impurities, the method of claim 3 or 5 is employed. Has the same effect as.

According to the manufacturing method of the insulated gate transistor of the ninth aspect, in the eighth aspect, the manufacturing process can be rationalized similarly to the effect of the sixth aspect. Claim 4
According to the insulated gate type transistor, since the source / drain wiring is formed on the source / drain electrode silicided on the amorphous silicon layer containing impurities, the resistance can be further reduced in addition to the effect of claim 3. .

According to the method of manufacturing an insulated gate transistor of claim 10, the source / drain electrodes of the silicide layer of the same metal as the lift-off layer are formed on the amorphous silicon layer containing impurities, and the source / drain wiring is formed. Since it is formed, the resistance is further reduced in addition to the same effect as the eighth aspect.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an insulated gate transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state in which a gate is formed on the glass substrate.

FIG. 3 is a cross-sectional view showing a state in which a gate insulating layer, an amorphous silicon layer containing no impurities, and an insulating layer are formed thereon.

FIG. 4 is a cross-sectional view showing a state in which a negative photosensitive resin layer is formed thereon.

FIG. 5 is a cross-sectional view showing a state where the photosensitive resin layer is subsequently developed to form an opening.

FIG. 6 is a cross-sectional view showing a state where a lift-off layer is subsequently formed.

FIG. 7 is a cross-sectional view showing a state of subsequently irradiating a plasma beam.

FIG. 8 is a cross-sectional view showing a state where a metal layer for source / drain is subsequently formed.

FIG. 9 is a cross-sectional view showing a state where a source / drain metal layer of the second embodiment is selectively removed.

FIG. 10 is a cross-sectional view showing a state where source / drain wirings are formed.

FIG. 11 is a cross-sectional view showing a state in which a metal layer for source / drain of the third embodiment is formed following FIG.

FIG. 12 is a cross-sectional view showing a state where source / drain wirings are formed.

FIG. 13 is a cross-sectional view showing a state where source / drain electrodes of the fourth embodiment are formed following FIG. 11.

FIG. 14 is a cross-sectional view showing a state where source / drain wirings are subsequently formed.

FIG. 15 is a perspective view of a main part of a liquid crystal panel.

FIG. 16 is an equivalent circuit diagram of an active liquid crystal panel.

FIG. 17 is a cross-sectional view of a color display panel.

FIG. 18 is a plan view of a liquid crystal display substrate.

FIG. 19 is a cross-sectional view showing the manufacturing process and showing a state in which a gate is formed on the substrate.

FIG. 20 is a cross-sectional view showing a state where a gate insulating layer, an amorphous silicon layer, and an insulating layer are formed.

FIG. 21 is a cross-sectional view of a state in which an insulating layer is selectively removed and a plasma beam is irradiated.

FIG. 22 is a cross-sectional view showing a state where a pixel electrode is formed by selectively removing the amorphous silicon layer.

FIG. 23 is a cross-sectional view showing a state where source / drain wirings are formed.

FIG. 24 is a cross-sectional view with an opening removed.

FIG. 25 is a plan view of a liquid crystal display substrate of a proposed example.

FIG. 26 is a cross-sectional view showing the manufacturing process and showing a state in which a gate is formed on the substrate.

FIG. 27 is a cross-sectional view showing a state where a gate insulating layer, an amorphous silicon layer and an insulating layer are formed.

FIG. 28 is a cross-sectional view showing a state where a positive photosensitive resin is formed.

FIG. 29 is a cross-sectional view showing a state where the photosensitive resin is selectively removed.

FIG. 30 is a cross-sectional view showing a state where a plasma beam is irradiated.

FIG. 31 is a cross-sectional view showing a state where a source / drain metal layer is formed.

FIG. 32 is a cross-sectional view showing a state where a metal layer is selectively removed.

FIG. 33 is a cross-sectional view showing a state where source / drain wirings are formed.

[Explanation of symbols]

 2 Glass substrate which is an insulating substrate 11 Gate 12 Source wiring 23 Drain wiring 24 Gate insulating layer which is the first insulating layer 27 ′ Etching stopper layer of the second insulating layer 31 Amorphous silicon layer containing no impurities 32 Impurity Amorphous silicon layer containing

Claims (10)

[Claims] 1. An insulating substrate, a gate formed on one main surface of the insulating substrate, and a gate formed on the gate via a first insulating layer so as to be thinner than the gate in a self-aligned manner. A second insulating layer, a channel of an impurity-free amorphous silicon layer formed under the second insulating layer in a self-aligned manner with the gate, and a pair of non-adjacent channels including the impurity and adjacent to the channel. An insulated gate transistor having a crystalline silicon layer and source / drain wirings formed in a self-aligned manner on an amorphous silicon layer containing these impurities. 2. The insulated gate transistor according to claim 1, wherein the source / drain wiring is wired to a source / drain electrode formed on the amorphous silicon layer containing impurities in a self-aligned manner. 3. An insulating substrate, a gate formed on one main surface of the insulating substrate, and a gate formed on the gate via a first insulating layer so as to be thinner than the gate and self-aligned. A second insulating layer, a channel of an impurity-free amorphous silicon layer formed under the second insulating layer in a self-aligned manner with the gate, and a pair of non-adjacent channels including the impurity and adjacent to the channel. An insulated gate transistor having a crystalline silicon layer and a source / drain wiring which is formed in a self-aligned manner on the surface of an amorphous silicon layer containing these impurities and is silicided. 4. The insulated gate transistor according to claim 3, wherein the source / drain wiring is wired to a source / drain electrode formed on the amorphous silicon layer containing impurities in a self-aligned manner. 5. A step of selectively forming a first metal layer to be a gate on one main surface of an insulating substrate, a first insulating layer to be a gate insulating layer, and amorphous silicon containing no impurities. A layer and a second insulating layer are sequentially applied, a step of applying a negative photosensitive resin on the second insulating layer, and an exposure from another main surface of the insulating substrate. Forming a photosensitive resin pattern having an opening smaller than the gate on the gate, depositing a lift-off layer made of metal on the entire surface including the opening, and removing the photosensitive resin and Selectively leaving the lift-off layer in the opening on the second insulating layer; and selectively removing the second insulating layer by using the selectively left lift-off layer as a mask to form the amorphous state. Of the porous silicon layer and the lift-off layer A step of selectively implanting impurities into the amorphous silicon layer by plasma doping using the mask as a mask to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer; Of at least one of the metal layer and the silicide layer, the lift-off layer is removed, and the second metal layer or the silicide layer and the amorphous silicon layer containing impurities are selectively removed to be adjacent to the channel. Forming a pair of amorphous silicon layers containing impurities and forming source / drain wirings on the amorphous silicon layers. 6. The insulating substrate is one of the substrates for a liquid crystal display device, the gate also serves as a scanning line, and the other of the substrates for the liquid crystal display device is used as a mask for the first portion of the end portion of the scanning line. The method for manufacturing an insulated gate transistor according to claim 5, wherein the insulating layer is removed. 7. A step of selectively forming a first metal layer to be a gate on one main surface of an insulating substrate, a first insulating layer to be a gate insulating layer, and amorphous silicon containing no impurities. A layer and a second insulating layer are sequentially applied, a step of applying a negative photosensitive resin on the second insulating layer, and an exposure from another main surface of the insulating substrate. Forming a photosensitive resin pattern having an opening smaller than the gate on the gate, depositing a lift-off layer made of metal on the entire surface including the opening, and removing the photosensitive resin and Selectively leaving the lift-off layer in the opening on the second insulating layer; and selectively removing the second insulating layer by using the selectively left lift-off layer as a mask to form the amorphous state. Of the porous silicon layer and the lift-off layer A step of selectively implanting impurities into the amorphous silicon layer by plasma doping using the mask as a mask to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer; Of at least one of the metal layer and the silicide layer, the lift-off layer is removed, and the second metal layer or the silicide layer and the amorphous silicon layer containing impurities are selectively removed to be adjacent to the channel. Forming a pair of amorphous silicon layers containing impurities, forming source / drain electrodes on the amorphous silicon layer, and forming source / drain wirings on the source / drain electrodes. A method of manufacturing an insulated gate transistor including. 8. A step of selectively forming a first metal layer to be a gate on one main surface of an insulating substrate, a first insulating layer to be a gate insulating layer, and amorphous silicon containing no impurities. A layer and a second insulating layer are sequentially applied, a step of applying a negative photosensitive resin on the second insulating layer, and an exposure from another main surface of the insulating substrate. Forming a photosensitive resin pattern having an opening thinner than the gate on the gate, and depositing a lift-off layer made of a second metal capable of forming a silicide on the entire surface including the opening, A step of selectively leaving the lift-off layer of the opening on the second insulating layer together with the removal of the photosensitive resin; and selecting the second insulating layer by using the selectively left lift-off layer as a mask Exposed to expose the amorphous silicon layer And a step of selectively implanting impurities into the amorphous silicon layer by plasma doping using the lift-off layer to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer. Step, and after depositing the same metal layer as the second metal layer on the entire surface, the insulating substrate is heated to form a silicide layer containing the second metal layer component on the amorphous silicon layer containing the impurities. And a step of selectively removing the silicide layer and the amorphous silicon layer containing impurities to form a pair of amorphous silicon layers containing impurities adjacent to the channel and on the amorphous silicon layer. And a step of forming source / drain wiring on the insulating layer. 9. The insulating substrate is one of the substrates for a liquid crystal display device, the gate also serves as a scanning line, and the other one of the substrates for the liquid crystal display device is used as a mask for the first insulation of the end portion of the scanning line. 9. The method for manufacturing an insulated gate transistor according to claim 8, wherein the layer is removed. 10. A step of selectively forming a first metal layer to be a gate on one main surface of an insulating substrate, a first insulating layer to be a gate insulating layer, and amorphous silicon containing no impurities. A layer and a second insulating layer in sequence, said second layer
A step of applying a negative photosensitive resin on the insulating layer, and a photosensitive resin pattern having an opening thinner than the gate in the gate including the exposure from the other main surface of the insulating substrate. Forming step, depositing a lift-off layer made of a second metal capable of forming silicide on the entire surface including the opening, removing the photosensitive resin, and forming the lift-off layer in the opening with the second layer. Selectively leaving the second insulating layer by using the selectively left lift-off layer as a mask to expose the amorphous silicon layer. A step of selectively implanting impurities into the amorphous silicon layer by plasma doping using a lift-off layer to form a channel of the amorphous silicon layer containing no impurities under the second insulating layer, and Second Depositing the same metal layer as the metal layer and heating the insulating substrate to form a silicide layer containing a second metal layer component on the amorphous silicon layer containing impurities; The amorphous silicon layer containing impurities is selectively removed to form a pair of amorphous silicon layers containing impurities adjacent to the channel, and source / drain electrodes are formed on the amorphous silicon layers. A method of manufacturing an insulated gate transistor, comprising the steps of: forming a source / drain wiring on the source / drain electrode.