JPH07147087A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To suppress the lowering in bit line potential so as to reduce power consumption at the time of precharging a semiconductor memory. CONSTITUTION:This device is provided with bit line pairs BL, XBL, pre-charge circuits 102, switch circuits 103, timing control circuits 106 and sense amplifiers 107 respectively for respective plural memory cells 101 commonly connected to one word line ML activated by a row decoder 104. The timing control circuit 106 outputs a word line control signal WC and a switch control signal SC so as to separate the memory cell 101 and the sense amplifier 107 from the bit line pair BL, XBL when the potential of the bit line pair BL, XBL are changed to the extent where the sense amplifier 107 is operated after the precharge of the bit line pair BL, XBL are ended and the word line WL is activated. The unactivation of the word line ML is controlled by an OR gate 108 and an AND gate 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static RAM.
The present invention relates to a semiconductor memory device such as (SRAM).

[0002]

SR in which a pair of bit lines are precharged to "H" level (potential Vdd) and then the word lines are activated to read the data held in the memory cells
AM is known. One of the bit line pairs, which is determined according to the held data, is gradually discharged through the memory cell, and the resulting potential difference between the bit line pairs is amplified by the sense amplifier. However, if the word line is still activated, the potential of the bit line on the side where the discharge is started tends to continue decreasing to the ground level (potential 0V). This is because the charge on the bit line continues to be lost through the memory cell. As a result, the potential of the bit line is significantly lowered, and the charging current in the next precharge cycle is increased.

Therefore, in the conventional SRAM described in JP-A-60-61986, the word line is activated when the output potential of the sense amplifier is determined before the potential of the bit line is completely lowered to the ground level. The memory cell is separated from the bit line pair by stopping the conversion. As a result, the potential drop of the bit line is suppressed, and the power consumption during precharge is reduced. The determination of the output potential of the sense amplifier is detected by a detection circuit having a circuit threshold value of 1/2 Vdd, for example.

[0004]

In an SRAM having a CMOS structure having a latch type sense amplifier, the sense amplifier is amplified when the potential of one bit line drops from Vdd by the threshold voltage Vtp of the PMOS transistor. The operation can be started. Moreover, after the potential of one bit line becomes lower than Vdd-Vtp, the sense amplifier performs the amplifying operation even if the memory cell is disconnected from the bit line pair or the sense amplifier is disconnected from the bit line pair. It can be continued, and the output potential of the sense amplifier is fixed.

However, since the conventional SRAM having the above-described detection circuit has a structure in which the activation of the word line is stopped after the output potential of the sense amplifier is fixed, the potential of the bit line is lowered. There was insufficient suppression. There is also a problem that the sense amplifier pulls down the bit line potential with a large driving force depending on the internal configuration of the sense amplifier. There is also a problem that all the memory cells belonging to one row cause the potential of the bit line to drop.

An object of the present invention is to suppress the decrease in bit line potential so that the power consumption during precharge of the semiconductor memory device can be reduced.

[0007]

In order to achieve the above object, the first semiconductor memory device according to the present invention is provided with a sense amplifier before the output potential of the sense amplifier is fixed and at the latest, to the extent that the sense amplifier can operate. The memory cell and the sense amplifier are separated from the bit line pair when the potential of the bit line changes.

In the second semiconductor memory device according to the present invention, only the word line in one memory block selected by the column address among the plurality of memory blocks is activated. . Moreover, precharge of the bit line pair is permitted only when the word line is activated in the immediately preceding access cycle.

[0009]

According to the first semiconductor memory device, the discharge of the bit line is stopped earlier than in the conventional case, so that the decrease of the bit line potential is suppressed. Further, since the load on the sense amplifier is reduced at an early stage, the output potential of the sense amplifier is rapidly determined.

According to the second semiconductor memory device, it is possible to prevent an unnecessary decrease in bit line potential. Further, since the target of precharging is determined depending on whether or not the word line is activated in the immediately preceding access cycle, the precharge operation can be started early even if the confirmation of the input address is delayed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor memory devices according to embodiments of the present invention will be described below with reference to FIGS.

(First Embodiment) FIG. 1 is a circuit diagram of an SRAM having a CMOS structure according to a first embodiment of the present invention. Figure 1
In, WL indicates one of the plurality of word lines. A plurality of memory cells 101 for storing data are commonly connected to the word line WL. For each of the plurality of memory cells 101, a bit line pair BL, X
BL, data line pair DL, XDL, precharge circuit 10
2, the switch circuit 103, the timing control circuit 106, and the sense amplifier 107 are respectively provided so as to form one column.

In each column, the precharge circuit 10
2 is an "H" level (potential V
It is composed of three PMOS transistors so as to be precharged to dd). Precharge enable signal PC
E is a signal for activating the precharge circuit 102. The switch circuit 103 includes a bit line pair BL, XB
Two Ns interposed between L and the data line pair DL, XDL
It is composed of MOS transistors. Sense amplifier 107
Is the memory cell 101 when the word line WL is activated.
It intervenes on the data line pair DL, XDL so as to amplify the potential change of the bit line pair BL, XBL based on the stored data. This sense amplifier 107 has a bit line pair B
The potential of one bit line of L and XBL is from Vdd to P
The latch type internal structure is provided so that the amplification operation can be started when the threshold voltage Vtp of the MOS transistor is lowered. The sense amplifier enable signal SAE is a signal for activating the sense amplifier 107. The timing control circuit 106 is interposed between the switch circuit 103 and the sense amplifier 107, and has a bit line pair BL, XB that allows the sense amplifier 107 to operate before the output of the sense amplifier 107 is determined.
When the potential of one of L changes, the word line control signal WC and the switch control signal SC are output. WE is a write enable signal and CK is a clock signal. The switch control signal SC is the switch circuit 103 of the column.
Are input to the respective gates of the two NMOS transistors constituting the.

The word line control signal WC output from the timing control circuit 106 of each column is input to one OR gate 108. The output of the OR gate 108 is input to the AND gate 105 together with the output of the row decoder 104. The output terminal of the AND gate 105 is the word line W
It is connected to L.

FIG. 2 is a circuit diagram showing an internal configuration of the timing control circuit 106. In FIG. 2, 121, 12
2, 124, 125 are first to fourth PMOS transistors, and 123, 126, 127, 128 are first to fourth N transistors.
A MOS transistor, 131 is a NOR gate, and 132 is an inverter. The sources of the first and second PMOS transistors 121 and 122 are connected to a power source (potential Vdd), and the second to fourth NMOS transistors 126 to 126 are connected.
The source of each of 128 is grounded. Third PMO
The gate of the S transistor 124 is connected to one bit line BL via one data line DL, and the gate of the fourth PMOS transistor 125 is connected to the other bit line XBL via the other data line XDL.

The write enable signal WE and the clock signal CK are input to the NOR gate 131. During the write operation in which the write enable signal WE holds the “H” level, the output of the NOR gate 131, that is, the read control signal Re holds the “L” level. During the read operation in which the write enable signal WE holds the “L” level, the logical level of the read control signal Re becomes the inversion level of the clock signal CK. The read control signal Re is directly input to the gate of the first PMOS transistor 121, and is connected to the second PMOS transistor 122 and the fourth NM.
An inverter 1 is provided at each gate of the OS transistor 128.
It is input via 32.

The first PMOS transistor 121 constitutes a first potential setting means for initializing the potential of the output node NA of the word line control signal WC and the switch control signal SC to "H" level. . Output node N
In addition to the drain of the first PMOS transistor 121, the gate of the first NMOS transistor 123 and the drain of the second NMOS transistor 126 are connected to A.

The second and third NMOS transistors 12
6, 127 constitute the current mirror 135. The drain and gate of the third NMOS transistor 127 are connected to the gate of the second NMOS transistor 126 so as to form the current input node NB. The drain of the second NMOS transistor 126 is connected to the output node NA as a current output terminal. The fourth NMOS transistor 128 constitutes second potential setting means for initializing the potential of the current input node NB of the current mirror 135 to the “L” level (ground level).

Third and fourth PMOS transistors 12
Reference numerals 4 and 125 constitute a current supply circuit 134 for supplying a current to the current input node NB of the current mirror 135 when the potential of one of the bit line pair BL and XBL becomes lower than Vdd-Vtp. To do. Here, Vtp is the threshold voltage of the PMOS transistor.

The second PMOS transistor 122 and the first NMOS transistor 123 have a current supply circuit 13 when the read control signal Re becomes "H" level.
4 to determine the current supply amount to the current mirror 135,
In addition, the current control circuit 133 is configured to cut off the supply current from the current supply circuit 134 to the current mirror 135 when the potential of the output node NA is lowered to the “L” level by the current mirror 135.

Next, the SRA having the configuration of FIG. 1 and FIG.
The read operation of M will be described. 3 (a)-(d)
FIG. 6 is a timing chart for explaining its operation.

At time T0, in all columns,
The word line control signal WC of “H” level and the switch control signal SC of “H” level are supplied to the timing control circuit 106.
Is output from. The output of the OR gate 108 is "H"
This is the level, and the switch circuits 103 of all columns are conducting. Bit line pair BL, XBL and data line pair DL,
XDL is previously set to “H” by the precharge circuit 102.
It is precharged to the level (potential Vdd). At this time, in the timing control circuit 106, since the read control signal Re is at the “L” level in response to the “H” level clock signal CK, the first PMOS transistor 121 and the first and fourth PMOS transistors 121 and Only the NMOS transistors 123 and 128 are conductive. The current supply circuit 1 is connected to the current input node NB of the current mirror 135.
The current is not supplied from 34, and the potential of the current input node NB is pulled down to the ground level by the fourth NMOS transistor 128.
And the third NMOS transistors 126, 127 are never conductive. Therefore, the potential of the output node NA is surely at "H" level.

At time T1, the clock signal CK transitions to the "L" level, and the read cycle starts. The precharge circuit 102 is deactivated. In the timing control circuit 106, since the read control signal Re changes to the “H” level, the first PMOS transistor 121
Is turned off, the second PMOS transistor 122 is turned on, and the fourth NMOS transistor 128 is turned off. On the other hand, in response to the output of the row decoder 104, the AND gate 105 starts activation of the word line WL. In all columns, the bit line pair BL,
One bit line of XBL that is determined according to the data held in the memory cell 101 (BL in the example shown in FIG. 3C)
Potential gradually decreases from Vdd. One data line D
The potential of L also drops similarly.

When the potentials of one bit line BL and one data line DL drop to Vdd-Vtp at time T2, the third PMO in the timing control circuit 106 is reached.
S-transistor 124 switches from a non-conducting state to a conducting state. As a result, from the power supply to the second PMOS transistor 1
22, the first NMOS transistor 123 and the third P
A current is supplied to the current input node NB of the current mirror 135 via the MOS transistor 124. At this time, in the current mirror 135, the output node NA
A drain current flows through the second and third NMOS transistors 126 and 127 so as to lower the potential of the signal to the "L" level. Thus, when the potential of the output node NA in the timing control circuit 106 in a certain column becomes "L" level, the timing control circuit 106 in the column concerned.
Outputs the word line control signal WC of "L" level and the switch control signal SC of "L" level. The switch circuit 103 in the column is turned off, and the sense amplifier 107 and the data line pair DL and XDL are connected to the bit line pair B.
Immediately separated from L and XBL. As a result, the activated sense amplifier 107 causes the data line pair DL, XDL
Even if the potential of one data line DL is greatly lowered as shown in FIG. 3D so as to determine the potential of the bit line BL, the potential of the bit line BL is not lowered by the sense amplifier 107. Note that when the potential of the output node NA in the timing control circuit 106 becomes “L” level, the first NMOS transistor 123 becomes non-conductive,
The current supplied to the current mirror 135 is cut off.

At time T3, the word line control signal WC of "L" level is output from the timing control circuits 106 of all columns.
Is output, the output of the OR gate 108 shifts to the “L” level, and the AND gate 105 causes each of the plurality of memory cells 101 to correspond to the corresponding bit line pair BL, XB.
The activation of the word line WL is stopped so as to be separated from L. As a result, as shown in FIG. 3C, the potential of the bit line BL does not drop after time T3.

As described above, according to this embodiment, when the potential of one bit line BL becomes lower than Vdd-Vtp to the extent that the sense amplifier 107 can operate before the output potential of the sense amplifier 107 is determined. Since the memory cell 101 and the sense amplifier 107 are separated from the bit line pair BL, XBL, the potential decrease of the bit line BL is suppressed as compared with the conventional case, and the power consumption during precharge is reduced. Further, by opening the switch circuit 103, the sense amplifier 10
Since the load of No. 7 is reduced, the output potential of the sense amplifier 107 can be rapidly determined.

Further, according to this embodiment, in the timing control circuit 106, the fourth NMOS transistor 128 is used to initialize the potential of the current input node NB of the current mirror 135 to the "L" level. Therefore, even if the mirror ratio of the current mirror 135 is increased, the problem that the second NMOS transistor 126 maintains the conductive state does not occur. However, if the mirror ratio of the current mirror 135 is not made too large, the fourth
The provision of the NMOS transistor 128 can be omitted.

The current mirror 135 has two NPs.
It is also possible to use an N-type bipolar transistor.

(Embodiment 2) FIG. 4 is a circuit diagram of an SRAM having a CMOS structure according to a second embodiment of the present invention. Figure 4
The configuration of the word line control signal WC and the switch control signal S
C and C are obtained from the dummy column 200. The dummy column 200 includes a dummy cell 201, a dummy bit line pair BL and XBL, a dummy precharge circuit 202, a dummy switch circuit 203, and a timing control circuit 106. The dummy cell 201 is connected to the word line WL together with the memory cell 101. The word line control signal WC output from the timing control circuit 106 is input to the AND gate 105 for word line control without passing through the OR gate. The switch control signal SC is supplied to the dummy switch circuit 203 in the dummy column 200 and the switch circuits 103 in other columns.

According to this embodiment, it is possible to achieve the same effect as that of the configuration of FIG. 1 while suppressing the layout area.

(Embodiment 3) FIG. 5 is a circuit diagram of an SRAM having a CMOS structure according to a third embodiment of the present invention. Figure 5
The configuration of the word line control signal WC and the switch control signal S
A dummy column 20 in which C and C are provided for each memory block
It was obtained from 0. In FIG. 5, 35
0a and 350b represent the first and second memory blocks. Dummy column 200 for each memory block
The word line control signal WC output from the timing control circuit 106 is input to the AND gate 105 for word line control via the OR gate 108. In the same memory block, the switch control signal SC is
Dummy switch circuit 203 in the dummy column 200
And the switch circuits 103 of other columns.

According to this embodiment, the timing control circuit 1
By reducing the load of 06, it is possible to achieve the same effect as the configuration of FIG. 4 while realizing the high-speed opening of the switch circuit 103.

(Embodiment 4) FIG. 6 is a circuit diagram of an SRAM having a CMOS structure according to a fourth embodiment of the present invention. Figure 6
4 adopts the configuration of FIG. 4 for each memory block. In FIG. 6, 350a and 350b represent the first and second memory blocks. 104a
And 402a are a first row decoder and a first precharge circuit provided for the first memory block 350a, and 104b and 402b are a second row provided for the second memory block 350b. A decoder and a second precharge circuit. The same row address RA is supplied to the first and second row decoders 104a and 104b. Reference numeral 403 is an inverter for supplying an inverted signal of the clock signal CK to the first and second precharge circuits 402a and 402b as a precharge enable signal PCE. Both memory blocks 350a, 350
In each of b, each of the plurality of columns includes a switch circuit 103, and the data line pairs DL and XDL of the plurality of switch circuits 103 are commonly connected to one sense amplifier 107. Each switch circuit 103 has not only the function of disconnecting the sense amplifier 107 from the bit line pair BL, XBL in accordance with the switch control signal SC output from the timing control circuit 106 in the dummy column, but also the function of a column selector. Be prepared. The sense amplifier 107 for each memory block is connected to one block selector 404.

The SRAM of FIG. 6 has a column decoder 400.
And the first and second access flag registers 401a,
401b and. The clock signal CK is supplied to the first and second access flag registers 401a and 401b and the first and second row decoders 104a and 104b. The column decoder 400 generates block selection signals BS1 and BS2 from the upper column address UCA, and generates a plurality of column selection signals CS from the lower column address LCA. BS1 is a signal for selecting the first memory block 350a and is input to the block selector 404, the first row decoder 104a, and the first access flag register 401a. BS2
Is a signal for selecting the second memory block 350b, and includes the block selector 404 and the second row decoder 1
04b and the second access flag register 401b. The column selection signal CS is applied to both memory blocks 3
Switch circuit 103 of each column in 50a and 350b
And the dummy switch circuit 203.

Next, in a certain access cycle, the first
Memory cell 10 in the memory block 350a of
As shown in FIG.
The read operation of the SRAM having the above configuration will be described.

When the input address becomes valid, column decoder 400 generates block selection signals BS1 and BS2 and column selection signal CS. BS1 is activated and becomes "H" level, and BS2 is inactivated and becomes "L" level. In the first memory block 350a, the switch circuits 1 for a plurality of columns are responsive to the column selection signal CS.
One of 03 and the dummy switch circuit 203 are electrically connected.

When the clock signal CK transits to "L" level, the first row decoder 104a which receives the "H" level block selection signal BS1 receives the AND gate 105.
One word line WL is activated via. After that, the timing control circuit 106 changes the potentials of all the bit line pairs BL and XBL in the first memory block 350a to the extent that the sense amplifier 107 can operate before the output of the sense amplifier 107 is determined. At this time, the word line control signal WC and the switch control signal SC are output. That is, the dummy cell 2 in the first memory block 350a
When the potential of one bit line of the dummy bit lines BL and XBL connected to 01 drops to Vdd-Vtp, the timing control circuit 106 causes the word line control signal WC at the "L" level and the switch at the "L" level. The control signal SC is output. The AND gate 105 stops activation of the word line WL so as to immediately disconnect each of the plurality of memory cells 101 and one dummy cell 201 from the corresponding bit line pair BL, XBL. Further, the switch circuit 103 and the dummy switch circuit 203, which have been conducting, immediately become non-conducting, and the sense amplifier 107 causes the bit line pair B
Separated from L and XBL. On the other hand, the sense amplifier 10
7 continues the amplification operation, and the first memory block 350a
Read data from one of the memory cells 101 in the above is output through the block selector 404.

When the clock signal CK returns to "H" level, the block selection signals BS1 and BS2 are stored in the first and second access flag registers 401a and 401b, respectively. In the above example, BS1 is at "H" level, BS
Since "2" is at the "L" level, data "1" is stored in the first access flag register 401a and data "0" is stored in the second access flag register 401b. The first precharge circuit 402a executes the precharge operation according to the precharge enable signal PCE only when the data stored in the first access flag register 401a is "1". Second
The precharge operation of the precharge circuit 402b is permitted or prohibited according to the data stored in the second access flag register 401b. Therefore, in the above example, the first precharge circuit 40 of both precharge circuits is
Only 2a performs the precharge operation. As a result, the first memory block 3 accessed in the immediately preceding cycle
Bit line pair in 50a and dummy bit line pair BL, X
Only BL is precharged to "H" level. The bit line pair and the dummy bit line pair BL, XBL in the second memory block 350b that has not been accessed retains the "H" level even if the second precharge circuit 402b does not operate. At this point, both memory blocks 35
All bit line pairs 0a and 350b and dummy bit line pairs BL and XBL are precharged to the “H” level, and the standby state for the next access is set.

According to this embodiment, it is possible to achieve the same effect as that of the structure of FIG. 4 while preventing the unnecessary decrease of the potential of the bit line by limiting the activation of the word line WL. Further, since the precharge circuits 402a and 402b are selected based on the input address information relating to the immediately preceding access, even if the determination of the next input address is delayed,
The precharge operation can be started early.

(Embodiment 5) FIG. 7 is a circuit diagram of an SRAM having a CMOS structure according to a fifth embodiment of the present invention. Figure 7
6 is a modification of the configuration of FIG. 6 so as to adopt the configuration of FIG. 5 including the OR gate 108. In this embodiment, the first and second memory blocks 350a and 350a
A row decoder 104 and a main word line MWL which are common to b are provided. The row decoder 104 selectively activates one main word line MWL via the AND gate 105.
Reference numeral 410a denotes a sub-decoder provided for the first memory block 350a, which activates the sub-word line SWL of the first memory block 350a on condition that the main word line MWL and the block selection signal BS1 are activated. Is. Further, 410b is the second memory block 3
The sub-decoder provided for 50b activates the sub-word line SWL of the second memory block 350b on condition that the main word line MWL and the block selection signal BS2 are activated. Each sub-decoder 410
Each of a and 410b can be configured by a 2-input AND gate.

According to the present embodiment, by limiting the activation of the sub word line SWL, it is possible to achieve the same effect as that of the structure of FIG. 5 while preventing unnecessary bit line potential drop. Similar to the configuration of FIG. 6, the precharge operation can be started early even when the confirmation of the input address is delayed.

The present invention can be applied to other than the SRAM having the CMOS structure. The present invention can be applied even when a single bit line is connected to the memory cell. The number of memory blocks in the configurations of FIGS.

[0043]

As described above, according to the present invention, the memory cell and the sense amplifier are separated from the bit line when the bit line potential changes to the extent that the sense amplifier can operate. Is suppressed, and the power consumption during precharge is reduced as compared with the conventional case. Since the load on the sense amplifier is reduced early, the amplification operation of the sense amplifier can be speeded up.

Further, according to the present invention, when only the word line in one selected memory block of the plurality of memory blocks is activated and the word line is activated in the immediately preceding access cycle, Since only the bit line pair is precharged, unnecessary bit line potential drop is prevented, and power consumption during precharge is reduced as compared with the related art. Even if the confirmation of the input address is delayed, the precharge operation can be started early.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a timing control circuit in FIG.

3A to 3D are timing diagrams for explaining the operation of the semiconductor memory device of FIG.

FIG. 4 is a schematic configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

[Explanation of symbols]

101 Memory Cell 102 Precharge Circuit (Precharge Means) 103 Switch Circuit (Switch Means) 104 Row Decoder (Decoding Means) 104a, 104b Row Decoder (Activating Means) 105 AND Gate (Control Means) 106 Timing Control Circuit (Detecting Means) ) 107 sense amplifier (amplifying means) 108 OR gate (detecting means, arithmetic circuit) 121 PMOS transistor (first potential setting means) 128 NMOS transistor (second potential setting means) 133 current control circuit (current suppressing means) 134 Current supply circuit (current supply means) 135 Current mirror (current mirror means) 201 Dummy cell 202 Dummy precharge circuit (dummy precharge means) 203 Dummy switch circuit 350a, 350b Memory block 400 Color Decoder (selection means) 401a, 401b Access flag register (storage means) 402a, 402b Precharge circuit (precharge means, dummy precharge means) 410a, 410b Subdecoder (activation means) WL Word line MWL Main word line SWL subword Line BL, XBL bit line, dummy bit line DL, XDL data line WC Word line control signal (first detection signal) SC switch control signal (second detection signal)

Claims (10)

[Claims] 1. A plurality of memory cells each for storing data, a word line commonly connected to the plurality of memory cells, and a plurality of word lines each connected to a corresponding memory cell of the plurality of memory cells. Bit lines, precharge means for charging each of the plurality of bit lines to a set precharge level, and stored data of each of the plurality of memory cells when the word line is activated. Amplification means connected to the plurality of bit lines so as to amplify potential changes of the plurality of bit lines based on the above, and before the output of the amplification means is fixed, and at the latest, to the extent that the amplification means can operate. Detection means for outputting first and second detection signals when the potentials of the plurality of bit lines change, and the plurality of memos according to the first detection signal from the detection means. Control means for stopping the activation of the word line so as to disconnect each of the recells from the corresponding bit line, and disconnecting the amplifying means from the plurality of bit lines according to a second detection signal from the detection means. And a switch means of the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the detection unit includes a first potential setting unit for initializing a potential of an output node of the first and second detection signals, and a current input. A current mirror means having a terminal and a current output terminal connected to the output node so as to change the potential of the output node when a current is supplied to the current input terminal; A current supply means for supplying a current to the current input terminal of the current mirror means when the potential of a corresponding bit line of the plurality of bit lines changes, and the current supply means when the potential of the output node changes. A semiconductor memory device comprising: current suppressing means for suppressing a current supplied from a supplying means to the current mirror means. 3. The semiconductor memory device according to claim 2, wherein the detection means further comprises second potential setting means for initializing the potential of the current input terminal of the current mirror means. Semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the detection unit is connected to the plurality of bit lines so as to detect a potential change of a corresponding bit line among the plurality of bit lines. A semiconductor comprising a plurality of timing control circuits and a logic circuit for outputting the first detection signal when all the plurality of timing control circuits detect a potential change of a corresponding bit line. Storage device. 5. The semiconductor memory device according to claim 1, wherein the dummy cell connected to the word line, the dummy bit line connected to the dummy cell, and the dummy bit line are charged to a set precharge level. And a dummy precharge unit for detecting the potential change of the plurality of bit lines indirectly through the detection of the potential change of the dummy bit line. A semiconductor memory device comprising a timing control circuit connected to the dummy bit line for outputting. 6. The semiconductor memory device according to claim 1, wherein a plurality of dummy cells that are commonly connected to the word line, and a plurality of dummy bit lines that are connected to corresponding dummy cells of the plurality of dummy cells, respectively. A dummy precharge unit for charging each of the plurality of dummy bit lines to a set precharge level, the plurality of memory cells are divided into a plurality of memory blocks, and the plurality of dummy cells are respectively The detection unit belongs to one of the plurality of memory blocks, and the detection unit indirectly detects one of the plurality of memory blocks by detecting a potential change of a corresponding dummy bit line of the plurality of dummy bit lines. The corresponding dummy bit line is connected to detect the potential change of multiple bit lines in the corresponding memory block. A plurality of timing control circuits, and a logic circuit for outputting the first detection signal when all the plurality of timing control circuits detect a potential change of the corresponding dummy bit line. And semiconductor memory device. 7. A plurality of memory blocks, a selection means for selecting one of the plurality of memory blocks according to column address information, and one of the plurality of memory blocks in the immediately preceding access cycle. Storage means for storing access information indicating whether or not is selected by the selection means, and each of the plurality of memory blocks includes a plurality of memory cells for storing data, and the plurality of memories. A word line commonly connected to the cells, a plurality of bit lines each connected to a corresponding memory cell of the plurality of memory cells, and a memory block selected by the selecting means of the plurality of memory blocks Activating means for activating the word line on the condition that the word line belongs to Precharge means for charging each of the plurality of bit lines to a set precharge level on condition that they belong to the memory block indicated by the access information stored in the storage means. A characteristic semiconductor memory device. 8. The semiconductor memory device according to claim 7, wherein the potential change of the plurality of bit lines based on the stored data of each of the plurality of memory cells when the word line is activated is amplified. The amplifying means connected to the plurality of bit lines, the first and the first before the output of the amplifying means is fixed and at the latest when the potentials of the plurality of bit lines are changed to such an extent that the amplifying means can operate. Detecting means for outputting the second detection signal, and for stopping the activation of the word line so as to disconnect each of the plurality of memory cells from the corresponding bit line according to the first detection signal from the detecting means. And a switch means for disconnecting the amplifying means from the plurality of bit lines according to a second detection signal from the detecting means. Conductor memory device. 9. A plurality of memory blocks, a main word line arranged so as to straddle the plurality of memory blocks, and a decoding means for decoding row address information so as to activate the main word line. Selecting means for selecting one of the plurality of memory blocks according to column address information, and which one of the plurality of memory blocks has been selected by the selecting means in the immediately preceding access cycle. Storage means for storing access information, and each of the plurality of memory blocks, a plurality of memory cells for respectively storing data, a sub-word line commonly connected to the plurality of memory cells, A plurality of bit lines each connected to a corresponding memory cell of the plurality of memory cells; An activation unit for activating the sub-word line on condition that the main word line belongs to the memory block selected by the selection unit and the main word line is activated; Precharge means for charging each of the plurality of bit lines to a set precharge level on condition that they belong to the memory block indicated by the access information stored in the storage means. A characteristic semiconductor memory device. 10. The semiconductor memory device according to claim 9, wherein the potential change of the plurality of bit lines based on the stored data of each of the plurality of memory cells when the sub-word line is activated is amplified. The amplifying means connected to the plurality of bit lines, the first and the first before the output of the amplifying means is fixed and at the latest when the potentials of the plurality of bit lines are changed to such an extent that the amplifying means can operate. Detection means for outputting the second detection signal, and activation of the main word line is stopped so as to disconnect each of the plurality of memory cells from the corresponding bit line according to the first detection signal from the detection means. And a switch means for disconnecting the amplifying means from the plurality of bit lines according to a second detection signal from the detecting means. The semiconductor memory device according to.