JPH07147058A - Data playback device - Google Patents

Abstract

PURPOSE:To share a memory for absorbing the jitter of tape speed with a memory for deinterleaving. CONSTITUTION:Timing that demodulation data is written in a memory 113 from a demodulation part 108 and timing until an error is started to be corrected by an error correction part 111 are controlled by the start signal generation part 906 of a frame synchronous control part 116. Thus, the jitter of the tape speed is absorbed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus for reproducing using a plurality of reproducing heads such as S-DAT (fixed head type digital audio tape recorder), and more particularly to a tape speed control processing. It is a thing.

[0002]

2. Description of the Related Art Unlike a conventional analog compact cassette, a fixed head type digital recording / reproducing apparatus such as an S-DAT has a fixed bit rate of a PCM signal to be reproduced. Need to keep constant. Therefore, it is necessary to keep the average tape speed constant. Therefore, in the conventional fixed head type digital recording / reproducing apparatus, the demodulated data is written in the memory, the demodulated data is read from the memory at a constant rate, and the tape speed is adjusted so that the difference between the write address and the read address becomes small. Had control.

A conventional data reproducing apparatus of the present invention will be described by taking a DCC (Digital Compact Cassette) as an example.

FIG. 12 is a block diagram showing the structure of a conventional data reproducing apparatus. In FIG. 12, 401 is a cassette that stores a magnetic tape, 402 is a mechanism control unit, 403 is a recording head that performs recording and reproduction on the magnetic tape,
And a reproducing head. The recording head is composed of nine heads, one head records auxiliary data for recording control data and the like used for reproduction control, and the remaining eight heads record main data such as audio data. The reproducing head is composed of nine heads, one head outputs an auxiliary channel reproduction signal including control data used for reproduction control, and the remaining eight heads output a main channel reproduction signal including audio data. Output. In this conventional example, the magnetic tape is divided into upper and lower areas and one is used for recording in the forward direction and the other is used for recording in the reverse direction. When reversing the running direction, the head is rotated 180 degrees.

FIG. 13 is a diagram showing a recording track pattern on a tape recorded by a recording head in a conventional example.

In FIG. 13, AUX is an auxiliary data track for recording auxiliary data, and CH0 to 7 are main data tracks for recording main data.

Returning to FIG. 12, reference numeral 404 is a reproduction amplifier for amplifying the reproduction signal reproduced by the head 403.

Reference numeral 405 is an AD converter for analog-digital converting the reproduction signal amplified by the reproduction amplifier 404.

Reference numeral 406 is an equalizer for waveform equalizing the reproduction signal AD-converted by the AD converter 405.

Reference numeral 407 is a data detector for detecting data from the reproduction signal whose waveform is equalized by the equalizer 406.

A data demodulation unit 408 demodulates the data of 9 channels detected by the data detection unit 407. The data demodulation unit 408 detects the synchronization signal,
The demodulated data, which is subjected to demodulation processing such as 8-inverse conversion, is written in the main memory 413.

Reference numeral 416 is a reproduction block address RBAD detected by the demodulation unit 408 and a header parity flag HDP.
The demodulation unit 408 converts the demodulated data to TB based on
This is a TBC address generation unit that generates a write address signal TWRAD for writing to the C memory 409.

The TBC memory 409 is a memory for temporarily storing the demodulated data output from the demodulation unit 408.
Demodulated data is written to the TBC memory 409 by the write address signal TWRAD generated by the demodulation unit and read by read address data TRDAD generated by the address generation unit 410 (described later).
It is called a time base collector in the sense that the data sent in the time base of the reproduction signal is corrected to a fixed time base.

The address generation unit 410 includes a TBC memory 4
09, read address data TRDAD for reading the demodulated data, and address data MWRAD for writing the read data in the main memory 413.
And a write control signal MWREN is generated. These address data are generated on the basis of a fixed frequency clock irrelevant to the demodulation data rate of the demodulation unit 408. Further, since the jitter of the reproduced signal is absorbed by the TBC memory 409, the address data TRDAD and the address data MWRAD for writing the read data in the main memory 413 are offset by 8 channels from the common address data to the common address data. Should be added. For example, common address data may be shifted up by 3 bits and a channel address may be inserted into the lower 3 bits.

The error correction unit 411 is provided with a TBC memory 409.
The error detection / error correction processing is performed using the demodulated data written in the main memory 413 from.

The main data reading section 412 is a demodulation section 40.
After writing data to the main memory 413, the error correction unit 4
11 reads the demodulated data that has been subjected to error correction processing. The main data reading unit 412 performs deinterleaving processing for returning the order of main data to the original order by address control based on the interleaving rule applied at the time of recording.
That is, the read address is generated so that the demodulated data written in the main memory 413 in the demodulated order can be read in the predetermined order. The concept of interleaving is explained on pages 25 to 68 of "Illustrated DAT Reader" issued by Ohmsha, Ltd. on July 25, 1988.

Reference numeral 413 is a main memory in which the demodulated data is written from the TBC memory 409 and the demodulated data written from the main data reading unit 412 is read.

The address subtraction unit 414 includes the write address signal WRAD generated by the demodulation unit 408 and the read address data R generated by the main data reading unit 412.
Calculate the DAD difference.

The tape speed control unit 415 controls the mechanism control unit 402 so that the difference between the write address WRAD and the read address RDAD output by the address subtraction unit 414 becomes small. For example, when the write address is ahead of the read address, the tape speed is controlled to decrease, and in the opposite case, the tape speed is increased.

Next, the configuration of the demodulation unit 408 will be described. In this conventional example, the signal of each channel recorded on the tape is 8-10 modulated and divided into blocks, and the block synchronization signal, the block address, and the error of the block address are added at the beginning of each block. It is assumed that the parity for detection is recorded.

FIG. 14 shows an example of a DCC block format. The DCC block is composed of 51 bytes, and the first 3 bytes are a header and the subsequent 48 bytes are a data area called a body. In the header, the first byte (HD0) is the synchronization signal SYNC and the second byte (HD0)
1) is composed of a 3-bit frame address and a 5-bit block address, and the same data as the second byte is recorded in the third byte (HD2). Since HD1 and HD2 are the same data, an error between the frame address data and the block address data can be detected by taking the exclusive OR of the 2-byte data. That is, if the result of the exclusive OR is 00H (hexadecimal notation), it is possible to determine that HD1 has no error, and if it is other than 00H, there is an error.

FIG. 15 is a block diagram showing the configuration of the conventional demodulation section 408. In FIG. 15, 501 is the detection data PLLDT supplied from the data detection unit 407.
Is a SYNC detection unit that detects the synchronization signal SYNC. The SYNC detection unit 501 generates a word clock WDCK which is a clock for performing serial-parallel conversion and 8-10 demodulation based on the detected synchronization signal.

Reference numeral 502 is a serial-parallel converter that converts serial data into 10-bit parallel data based on the word clock WDCK output from the SYNC detector 501.

Reference numeral 503 is an 8-10 demodulation unit for converting the 10-bit data output by the serial-parallel conversion unit 502 into 8-bit data based on the word clock WDCK output by the SYNC detection unit 501. In addition,
The 8-10 modulation is described from page 96 to page 100 of "Illustrated DAT reader" published by Ohmsha, Ltd. on July 25, 1988.

The parity check unit 504 extracts the symbol HD1 including the block address from the demodulated data output from the 8-10 demodulation unit 503, stores HD1 in the register, and outputs the output of the register as the reproduction block address data RBAD. In addition to outputting, a parity check is performed by taking the exclusive OR of HD1 and HD2. If the result is 0, "1" is output as the header parity flag HDP, and if the result is "1", "0" is output as the header parity flag HDP.

With the conventional data reproducing apparatus constructed as described above, the average tape speed can be kept constant and the digital audio signal can be continuously reproduced.

[0027]

However, in the conventional data reproducing apparatus as described above, if the TBC memory is small and the difference between the write address TWRAD and the read address TRDAD of the TBC memory is large, the difference in the address is the TBC memory. Playback cannot be started until the capacity is reached. Therefore, there is a problem that it takes a long time to produce a sound when the tape is started. On the contrary, there is a problem in that it is necessary to increase the capacity of the TBC memory in order to shorten the time until the sound is output, which increases the cost.

Further, in order to continue the reproduction with respect to the tape speed fluctuation occurring during the reproduction, it is necessary to absorb the delay or advance of the reproduction data caused by the tape speed fluctuation in the TBC memory. In order to continue playback against large tape speed fluctuations,
There is a problem in that it is necessary to increase the capacity of the TBC memory, which increases the cost.

Furthermore, since the error detection of the block address is performed only by the parity check, there is a high probability that the error will be overlooked, and an incorrect TB will be generated based on the incorrect block address.
There is a problem that the C write address TWRAD may be generated and the control direction of the tape speed may be wrong.

[0030]

In order to solve the above-mentioned problems, a data reproducing apparatus of the present invention demodulates a plurality of reproducing heads and a plurality of reproducing signals reproduced from the plurality of reproducing heads to obtain block address data. A demodulation unit that outputs the demodulated data that has been detected and demodulated, a block address detection flag, and a reproduction block address data, and a write address that writes the demodulation data to the memory based on the block address detection flag and the reproduction block address data. A write address generation unit that generates channels independently,
A main data reading unit that reads and outputs the demodulated data written in the memory and an error correction unit that reads the demodulated data written in the memory and performs error correction processing are configured.

Further, the frame synchronization control unit includes a reference address counter for generating reference block address data, a subtracter for obtaining a difference between the reproduction block address data and the reference block address data, and outputting the difference as phase difference data. A comparator that determines whether or not the output value of the subtractor is within a predetermined range, and outputs an out-of-phase flag when the output value is not within the predetermined range,
A state control circuit that outputs a frame synchronization flag that is set by the block address detection flag and reset by the out-of-phase flag, and a tape speed that generates a tape speed control signal that controls the tape speed based on the phase difference data. A control unit and a start signal for sending a processing start signal for controlling the processing timing of the error correction unit and the main data reading unit to the error correction unit and the main data reading unit based on the reference block address data. The reference address counter is configured to load the reproduction block address data output from the demodulation unit when the frame synchronization flag becomes invalid to valid.

Further, according to the present invention, based on the block address detection flags of a plurality of channels and the reproduction block address data outputted from the demodulation section, the majority processing of the reproduction block addresses detected at the same time is carried out and the result is selected. A majority circuit for outputting a block address value as representative block address data is provided.

[0033]

According to the data reproducing apparatus of the present invention, the above-described configuration controls the processing timings of the error correcting unit and the main data reading unit to absorb the jitter of the reproduced signal by using the deinterleave and error correcting memory. It is possible to eliminate the need for the TBC memory, which was required in the past.

Furthermore, the reference address counter has a function of loading a representative block address obtained by performing majority decision on the demodulated reproduced block address data, so that the block address of the signal currently being reproduced is stored in the reference address counter. Since the addresses can be adjusted, demodulated data can be used faster than when the block address of the playback signal is adjusted to the reference block address by tape speed control, and the time from the start of the tape to the sound output can be shortened. Can be shortened.

Further, since the data reproducing apparatus of the present invention performs the majority decision process when detecting the block address as described above, the probability of overlooking the error of the block address data becomes extremely low. Frame synchronization is lost and the playback sound is not interrupted.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First embodiment of the data reproducing apparatus of the present invention
Embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a data reproducing apparatus according to the first embodiment of the present invention.

The embodiment of the present invention will be described by taking as an example a reproducing apparatus for reproducing a recorded tape in the form of a DCC (digital compact cassette).

The DCC is described in "Nikkei Electronics," 9-2, 1991, pages 134 to 141.

In FIG. 1, reference numerals 101 to 108 are the same as 401 to 408 described in the conventional example (see FIG. 12), and a description thereof will be omitted.

Reference numeral 109 denotes reproduction block address data RBAD for 8 channels demodulated by the demodulation unit 108,
The block address processing unit extracts a representative block address PBAD, which is effective block address data, by performing majority processing on the reproduction block address data for 8 channels based on the header parity flag HDP.

Reference numeral 116 denotes frame synchronization control based on the representative block address data, and phase difference data PHER.
And a frame synchronization control unit that outputs a frame clock FRCK. The frame clock FRCK is a fixed-frequency clock having a period of one frame in the case of standard tape speed as one cycle.

Here, the DCC frame format will be described. FIG. 2 is a diagram showing a DCC frame format.

In FIG. 2, block B (i, j) represents block j of channel i (i = 0, 1, 2, ...
., 7, j = 0, 1, 2, ..., 31). Therefore, one frame of main data has 32 blocks per channel, and if 8 channels are combined, 256
Composed of blocks.

Referring back to FIG. 1, the structure of the data reproducing apparatus according to the first embodiment of the present invention will be described.

Reference numeral 110 is a tape speed control unit for generating a tape speed control signal based on the phase difference data PHER generated by the frame synchronization control unit 116.

In the reference numeral 111, the demodulation unit 108 has a main memory 1
An error correction unit that performs error detection / error correction processing using the demodulated data written in 13. Error correction unit 111
Performs error correction processing on a frame-by-frame basis based on the frame clock FRCK.

In the reference numeral 112, the demodulation unit 108 has a main memory 1
This is a main data reading unit that reads out and outputs the demodulated data that has been subjected to error correction processing after being written in 13. The main data reading unit 112 uses the frame clock FRCK.
Based on the above, the main data is read in frame units. For example, the data of the first word in the frame is read in synchronization with the falling edge of the frame clock.

The main memory 113 is a memory in which the demodulation section 108 writes demodulated data. 114 is the demodulation unit 1
08, error correction unit 111, main data reading unit 112,
Tape speed detector 110, mechanism controller 102
Is a system control unit for controlling the. System control unit 11
Reference numeral 4 is a microprocessor.

Reference numeral 115 is a block address processing unit 109.
Based on the representative block address output from the main memory 1 and the block address valid flag BADLD.
13 is a write address generation unit that generates a write address for writing the demodulated data output from the demodulation unit 108 to the reference numeral 13.

In this embodiment, since the TBC memory explained in the conventional example is not provided, the jitter of the signal reproduced from the tape remains as it is, and the timing of the demodulated data of each channel is not constant. It is necessary to generate write address data independently.

Next, the configuration of the block address processing unit 109 will be described. FIG. 3 shows the block address processing unit 1.
It is a block diagram which shows the structure of 09.

In FIG. 3, reference numeral 602 denotes a block address register for selecting and latching block addresses for eight channels from the reproduction block address RBAD sent from the demodulation unit 108 in a time division manner.

603 is a block address register 60
Based on the block address of 8 channels latched in 2, for each channel, the validity of the block address of the channel is determined by the block address of the channel and the number of the same block addresses. It is a block address majority circuit for sending a block valid flag BADLD.

604 is a block address majority decision circuit 6
This is a representative block address register that latches a valid block address of the eight block addresses stored in the block address register based on the block valid flag BADLD output from the block 03. The representative block address register 602 outputs the latched value as representative block address data PBAD.

605 is channel address data CH
It is a timing signal generation unit that generates A. The channel address data CHA is data that circulates the values of 0 to 7 and is a signal that specifies the processing timing for each of the channels 0 to 7. In the block address majority circuit 603, time-division processing of data for 8 channels is performed by the channel address data CHA.

Next, the block address majority decision circuit 603.
Will be described. The purpose of the block address majority processing will be described below.

(1) The block address / frame address is only protected by parity, and the error detection capability is low.

(2) Since tape speed control is performed based on block address information, high reliability is required for block address information. That is, if the block address is wrong, the tape speed may be controlled in the wrong direction, and the reproduction may be impossible.

(3) R based on block address information
Since writing to the AM is performed, high reliability is required for the block address information.

The processing algorithm of the block address majority decision circuit 603 will be described below. When the number of channels + 1 whose block address matches the current channel occupies the majority of the channels whose block address is valid and is 3 or more, the block address is validated.

When this is expressed by an equation, it becomes as shown in (Equation 1).

[0063]

[Equation 1]

[Table 1] is a table showing the conditions for determining the block address.

[0065]

[Table 1]

FIG. 4 shows a block address majority decision circuit 603.
3 is a block diagram showing the configuration of FIG. In FIG. 4, 701
Is a selector that selects one block address from the block addresses for eight channels supplied from the block address register according to the channel address data CHA.

Channel address data CHA is 0 to
It is data that circulates the value of 7 and is a signal that specifies the processing timing for each of channels 0 to 7.

702A to 702J compare the block address data BAD0 to BAD7 with the block address data output from the selector 701, and output "1" when they match and "0" when they do not match. It is a comparator. The comparison result flag, which is the output of the comparator, is 1
It is supplied to the adder 703 as bit data. 70
An adder 3 outputs a value obtained by subtracting 1 from the result of adding the values of the comparison result flags of the comparators 702A to 702J as the matching channel number data.

704 is channel address data CH
According to the coincident channel number data output from A and the adder 703, the block address valid flag BADOK = 1 is output when the determination condition of (Table 1) is satisfied, and the block address valid flag BADOK = 0 is output when the determination condition of (Table 1) is not satisfied.

As described above, in the majority decision processing of the block address, the comparators for 8 channels are prepared, the comparisons are performed in parallel, and the addition of the comparison result is performed by the adder. Can be executed. 8
The processing clock can be lowered as compared with the method of performing comparison of channels by time division and further using a counter to add comparison results. If the processing clock can be lowered, it becomes possible to operate at a lower voltage, so that the power consumption in the case of an LSI can be reduced.

Next, the frame synchronization control unit 116 will be described. The frame synchronization control unit 116 uses the block address data reproduced from the tape to determine the phase of the reproduction frame and the difference between the phase of the reproduction frame and the phase of the reference frame. If the difference exceeds ± 4 blocks, the reference Resynchronization processing for matching the frame phase with the reproduction frame phase is performed, and control is performed so that the reproduction frame frequency and the reference frame frequency fall within a predetermined range.

Since DCC recording / reproduction is repeatedly performed in frame units, the frequency and phase of the frame can be defined.

The position of the point currently being reproduced in one frame is called the phase of the frame.

As described with reference to FIG. 2, since the block address is sequentially incremented from 0 to 31 in one frame, the block address is currently reproduced. But 1
The position in the frame, that is, the frame phase can be known.

FIG. 5 is a block diagram showing the structure of the frame synchronization control unit 116. In FIG. 5, reference numeral 901 is a reference address counter that generates reference block address data SBAD. The reference address counter 901 outputs reference block address data which is incremented 32 times in one frame. The reference block address data has accuracy to the right of the decimal point of the block address number. The reference block address data is composed of upper 5 bits corresponding to the block address number of 0 to 31 and lower 5 bits corresponding to the decimal point of the block address number in total of 10 bits. Further, the reference address counter 901 can load the value of the representative block address data PBAD by the load signal SADLD.

Reference numeral 902 denotes the block address processing unit 109.
This is a subtracter for obtaining the difference between the representative block address data PBAD supplied from the reference block address data SBAD and the reference block address data SBAD supplied from the reference address counter 901.
The output of the subtractor 902 is the phase difference data PHER,
It is supplied to the comparator 903 and the tape speed control unit 110.

Reference numeral 903 denotes an out-of-phase flag OUTP when the absolute value of the phase difference data PHER exceeds 4 blocks.
H = 1 is output, otherwise, out of phase flag OU
This is a comparator that outputs TPH = 0.

Reference numeral 904 denotes the block address processing unit 109.
The block address valid flag BADLD sent by the unit shifts to the frame synchronization state, and the out-of-phase flag OU
It is a state control circuit that transits to an asynchronous state when the overflow flag OVF output from TPH or the block counter 905 is 1.

Reference numeral 905 counts up with the signal of the digit of the 1/2 block of the reference block address data generated by the reference address counter 901, and when it is cleared by the block address valid flag BADLD and the count number reaches 32. , A block counter that outputs an overflow flag OVF.

Reference numeral 906 is a start signal generation unit which outputs a frame clock indicating the processing start timing of the error correction unit 111 and the processing start timing of the main data reading unit 112 based on the count value of the reference address counter 901.

Reference numeral 907 denotes segment address data SE which counts up four times in one cycle of the frame clock based on the count value of the reference address counter 901.
It is a segment address generation unit that generates GAD.

FIG. 6 is a state transition diagram showing the state transition of the state control circuit 109. In FIG. 6, reference numeral 101 indicates a synchronization state, and the frame synchronization flag FSYNC = 1. 102 indicates an asynchronous state, and FSYNC = 0. A transition is made from the synchronous state 101 to the asynchronous state 102 when the out-of-phase flag OUTPH = 1 or the overflow flag OVF becomes 1, and from the asynchronous state 102 to the synchronous state 101, the block address valid flag BA.
It makes a transition when DLD stands.

FIG. 7 is a block diagram showing the configuration of the state control circuit 904. In FIG. 7, reference numeral 1101 is an OR gate that takes the logical sum of the out-of-phase flag OUTPH and the overflow flag OVF.

Reference numeral 1102 is an RS flop flop reset by the output of the OR gate 1101 and set by the block address valid flag. The output of the RS flip-flop 1102 is output as the frame synchronization signal FSYNC.

1103 is a frame synchronization signal FSYNC.
Is a rising edge detection circuit that detects the rising edge of the signal and outputs the load signal SADLD. The load signal SADLD is used as a load signal for the reference address counter 901.

The operation of the data reproducing apparatus of the first embodiment of the present invention constructed as above will be described.

FIG. 8 is a timing chart showing an operation at the time of frame synchronization of the data reproducing apparatus of the first embodiment of the present invention.

In FIG. 8, (a) shows the frame number of the signal reproduced from the tape. V indicates a non-recording period. This period indicates a period during which the demodulation unit 108 demodulates the data of frame 0. In the subsequent demodulation processing, if the frequency of the reproduction signal is the standard frequency, in other words, if the tape recorded at the standard tape speed is reproduced at the standard tape speed, the demodulation processing is repeated at one frame cycle thereafter.

(B) shows the block address of the signal reproduced from the tape. V indicates a non-recording period.

(C) shows the reference block address SBAD generated by the reference address counter 901. The reference block address SBAD is changing even if the reproduction block address cannot be read.

(D) is a frame synchronization flag FSYNC output by the frame synchronization control unit 116. The frame synchronization flag FSYNC is "0" when the block address cannot be read during the non-recording period, but once the block address can be read, it rises due to the block address valid flag.

FIG. 9 is a timing chart showing an operation at the time of losing frame synchronization and resynchronizing the data reproducing apparatus of the first embodiment of the present invention.

In FIG. 9, (a) shows the frame number of the signal reproduced from the tape. (B) shows the block address of the signal reproduced from the tape. (C) shows the reference block address SBAD generated by. (D) is a frame synchronization flag FSYNC output by the frame synchronization control unit 116.

Frames 1 and after are the previously recorded frames, and frames before 0 are newly overwritten frames. Frame 1 is overwritten and the first half block 0 to 14 is erased. Therefore, the block addresses are discontinuous at the connection points between frame 0 and frame 1. That is, the block address is 31
I'm flying from block to block 15.

Here, the reproduction block address is "1".
5 ", but the reference block address is SBAD
Becomes “0”, the frame synchronization control unit 116 sets 1
Since the phase difference of 5 blocks is detected, the frame synchronization flag FSYNC shown in (d) becomes "0". afterwards,
Since the next block address "16" can be read, synchronization is applied again, the frame synchronization flag FSYNC becomes "1", and the reference block counter 901 is loaded with the reproduction block address "16".

Since the reproduction frames are gradually displaced, the difference between the reproduction block address and the reference block address is ± 4.
Even when the number of blocks is exceeded, similar to the case where the block addresses are discontinuous as described with reference to FIG. 9, the frame synchronization is once lost and the frame synchronization is performed again in the next block.

Next, the demodulation section 108, the error correction section 111,
Main data reading unit 112, frame synchronization control unit 116
The operation of will be described.

FIG. 10 is a memory map showing how to use the main memory 113. The main memory 113
Is a 32K * 8-bit SRAM (static random access memory).

In FIG. 10, bank 0 has address 00.
From 0H (hexadecimal notation) to 0BFH, bank 1 is an area from address 0C0H to 17FH. Or later,
An area of 0C0H is assigned to each of the banks 7.

It is assumed that one bank can store 1/4 frame of main data and error correction code.

FIG. 11 shows the demodulation unit 108 and the error correction unit 1.
11 is a timing chart showing the operations of 11 and the main data reading unit 112.

In FIG. 11, SEGAD indicates a segment address generated by the frame synchronization control unit 116.

MBANK0 to MBANK7 are bank 0
The access sections of the demodulation unit 108 to the main data reading unit 112 to 7 are shown.

In the items of MBANK0 to MBANK7, PCmn indicates the processing of the main data reading unit 112 corresponding to the data of the nth segment of the mth frame.

RFmn indicates the processing of the demodulation section 108 corresponding to the data of the nth segment of the mth frame.

In the section of the RF frame, RF. n is
The writing processing period for the data of the nth frame to the main memory 113 of the demodulation unit 108 in the state where the frame synchronization is applied is shown.

The reference block address SBAD output from the reference address counter 901 in the frame synchronization control unit 116 is the RF. In the period indicated by n, the blocks are incremented from 0 block to 31 block.

In the term of C1 / C2, C1. n indicates the C1 correction processing period of the error correction unit 111 for the data of the nth frame. Also, C2. In the PCM frame term indicating the C1 correction processing period of the error correction unit 111 for the data of the nth frame, PC. n is C2 of the main data reading unit 112 for the data of the nth frame.
Indicates the correction processing period.

The C1 correction is a correction process using an error correction code in block units, and the C2 correction is an error correction process using an error correction code in frame units. Therefore, the C2 correction can be started if the data is aligned in block units, but the C2 correction cannot be started unless the data for one frame is aligned.

Regarding the DCC error correction code,
"Nikkei Electronics," 1991, 9-2, pages 137 to 138.

FRCK represents a frame clock generated by the frame synchronization control unit 116. Error correction unit 111
Is the falling edge of the frame clock FRCK,
The C1 correction process is started.

The main data reading unit 112 starts reading the main data from the main data at the head of the frame at the falling edge of the frame clock FRCK.

FSYNC is a frame synchronization control unit 116.
Shows a frame synchronization signal generated by.

In FIG. 11, it can be seen that the writing period of the demodulation section 108 is 2 segments for 1 segment (1/4 of one frame) of data. Therefore, in the writing process of the demodulation unit 108, it is understood that the error correction process and the main data reading process are normally performed even if the shift is ± 0.5 segment.

As a result, it can be understood that the phase shift within ± 0.5 segment of the reproduction signal frame can be absorbed by the main memory 113.

As described above, by using the data reproducing apparatus of the first embodiment of the present invention, it is possible to absorb the frame phase shift of the input signal without separately providing the TBC memory.

In the embodiment of the present invention, the reliability of the block address data is improved by using the representative block address data detected by the block address majority decision process in the block address processing unit 109 in the frame synchronization control unit 116. Although it is possible to prevent erroneous resynchronization due to erroneous block address data, even if the block address data detected by the demodulation unit 108 for which the header parity flag HDP is set is used as it is, Synchronous control processing is possible (however, the probability of malfunction is high). In addition, the frame synchronization control unit 116 obtains the phase difference data based on the representative block address data detected by the block address majority decision processing in the block address processing unit 109, so that the wrong phase difference data is generated by the wrong block address data. Since the calculated tape speed control unit 110 does not erroneously control the tape speed control direction or control amount, stable tape speed control can be realized, but the header parity of the block address data detected by the demodulation unit 108 can be realized. Flag HD
The tape speed can be controlled even if the phase difference data is obtained by using the one with P standing as it is (however, the probability of malfunction is high).

Further, the representative block address data detected by the block address majority processing in the block address processing unit 109 is written into the write address generation unit 1
The reliability of the block address data is increased by using the block address data 15 and it is possible to prevent the reproduction data from being written in the wrong position by the wrong block address data. However, among the block address data detected by the demodulation unit 108, The reproduction data can be written in the memory even if the header parity flag HDP is set as it is (however, there is a high probability that the reproduction data will be written in the wrong position).

Besides improving reliability by majority processing, it is also possible to improve reliability of block address data by applying a stronger error correction code to the block address data.

However, since an error detection code having a high error detection capability generally has a high degree of redundancy, if the recording wavelengths are the same, the data transfer rate will decrease.

[0121]

As described above, according to the present invention, an error correction unit,
By controlling the processing timing of the main data reading unit, using the deinterleave and error correction memory,
It is possible to absorb the jitter of the reproduction signal, and it is possible to eliminate the need for the TBC memory, which has been conventionally required. Usually, since a large capacity of deinterleave and error correction memory is required, a general-purpose RAM is often used. When a general-purpose RAM is used, there is no half-capacity (for example, 256K bits However, a large capacity has 1 Mbit.), So the capacity is often surplus. In such a case, the remaining area can be effectively used to absorb the jitter of the reproduced signal.

Further, the data reproducing apparatus of the present invention performs the majority decision processing of the reproduction block address data detected at the same time based on the block address detection flags of a plurality of channels and the reproduction block address data outputted from the demodulation unit, and Equipped with a majority circuit that outputs the selected block address value as representative block address data. When the frame synchronization flag changes from invalid to valid, the reference address counter is loaded with the representative block address data output by the majority circuit. With this function, it is possible to match the address of the reference address counter to the block address of the signal currently being played. Compared to the case where the block address of the playback signal is adjusted to the reference block address by tape speed control. Quickly Enables the use of adjusted data, it is possible to shorten the time from the start-up tape of up to sound out.

Further, in the data reproducing apparatus of the present invention, since the majority decision processing of the block address reproduced as described above is performed, the probability of overlooking the error of the block address data becomes extremely low. Does not come off and the playback sound is not interrupted. In addition, since the wrong phase difference data is calculated by the wrong block address and the tape speed control direction and the control amount are not mistaken, stable tape speed control can be realized.

Further, the majority circuit of the present invention can execute the majority process in one clock, so that the comparison for eight channels is performed in a time-division manner, and the comparison result is added by using the counter. Since the clock can be lowered and it is possible to operate at a lower voltage, L
It is possible to reduce power consumption when SI is realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data reproducing device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a DCC frame format.

3 is a block diagram showing a configuration of a block address processing unit 109 in FIG.

FIG. 4 is a block address majority decision circuit 60 in FIG.
Block diagram showing the configuration of No. 3

5 is a block diagram showing a configuration of a frame synchronization control unit 116 in FIG.

6 is a state transition diagram showing the state transition of the state transition circuit 109 in FIG.

7 is a block diagram showing a configuration of a state transition circuit 109 in FIG.

FIG. 8 is a timing chart showing an operation during frame synchronization of the data reproducing apparatus of the first embodiment.

FIG. 9 is a timing chart showing an operation at the time of frame synchronization loss and resynchronization of the data reproducing apparatus of the first embodiment.

10 is a diagram showing a memory map showing how to use the main memory 113 in FIG.

FIG. 11 is a timing chart showing the operation of the demodulation unit 108, the error correction unit 111, and the main data read unit 112 in the first embodiment.

FIG. 12 is a block diagram showing the configuration of a conventional data reproducing device.

FIG. 13 is an explanatory diagram showing a recording track pattern on a tape recorded by a recording head in a conventional example.

FIG. 14 is an explanatory diagram showing a block format of DCC.

15 is a block diagram showing a configuration of a demodulation unit 408 in FIG.

[Explanation of symbols]

 101 cassette 102 mechanism control unit 103 recording head and reproduction head 104 reproduction amplifier 105 AD converter 106 equalizer 107 data detection unit 108 demodulation unit 109 block address processing unit 110 tape speed control unit 111 error correction unit 112 main data read unit 113 main memory 114 System control unit 116 Frame synchronization control unit

Claims (8)

[Claims] 1. A plurality of reproduction heads, a plurality of reproduction signals reproduced from the plurality of reproduction heads are demodulated, reproduction block address data is detected, demodulated demodulated data, a block address detection flag, and the reproduction block. A demodulation section for outputting address data; a write address generation section for independently generating a write address for writing demodulated data to the memory based on the block address detection flag and the reproduction block address data, and A data reproducing apparatus comprising: a main data reading unit that reads and outputs the written demodulated data, and an error correction unit that reads the demodulated data written in the memory and performs error correction processing. 2. A frame synchronization control unit for outputting phase difference data, an out-of-phase flag and a frame synchronization flag based on the reproduced block address data and the block address detection flag demodulated by the demodulation unit, and the phase difference data. 2. A data reproducing apparatus according to claim 1, further comprising a tape speed control section for generating a tape speed control signal for controlling the tape speed. 3. A block address processing unit that creates a block address valid flag and representative block address data based on the reproduced block address data demodulated by the demodulation unit and the block address detection flag, the block address valid flag and the block address valid flag. The data reproducing apparatus according to claim 1, further comprising: a frame synchronization control unit that creates phase difference data, a phase shift flag, and a frame synchronization flag based on the representative block address data. 4. A frame synchronization control unit, a reference address counter for generating reference block address data, a subtracter for obtaining a difference between the reproduction block address data and the reference block address data, and outputting the difference as the phase difference data. It is determined whether or not the output value of the subtractor is within a predetermined range, and if it is not within the predetermined range, a comparator that outputs an out-of-phase flag and the block address detection flag are set, A state control circuit that outputs a frame synchronization flag that is reset by the out-of-phase flag, and a processing start signal that controls the processing timing of the error correction unit and the main data reading unit based on the reference block address data, and the error correction unit. And a start signal generation section for sending to the main data reading section, The data reproducing device according to claim 2 or 3, wherein the dress counter loads the reproduction block address data output from the demodulation unit when the frame synchronization flag becomes valid from invalid. 5. A demodulation unit that demodulates a reproduction signal, detects reproduction block address data, and outputs a block address detection flag and the reproduction block address data; and a block address detection flag and the reproduction block address data. A frame sync control unit that creates phase difference data, an out-of-phase flag, and a frame sync flag, and a tape speed control unit that creates a tape speed control signal that controls the tape speed based on the phase difference data. The frame synchronization control unit includes a reference address counter that generates reference block address data, a subtracter that calculates a difference between the reproduction block address data and the reference block address data, and outputs the difference as the phase difference data, and the subtraction unit. Determine whether the output value of the instrument is within the specified range A comparator that outputs an out-of-phase flag when it is not within a predetermined range, and a state control circuit that outputs a frame synchronization flag set by the block address detection flag and reset by the out-of-phase flag And a reproducing device for loading the reproduction block address data output from the demodulation unit to the reference address counter when the frame synchronization flag is changed from invalid to valid. 6. A block address processing unit for creating a block address valid flag and representative block address data based on the reproduced block address data and the block address detection flag demodulated by the demodulation unit. Item 5. The data reproducing device according to item 5. 7. The block address processing section, based on the block address detection flags of a plurality of channels output from the demodulation section and the reproduction block address data,
The frame synchronization control unit includes a majority decision circuit that performs a majority decision process of block addresses detected at the same time and outputs a block address valid flag, and a register that latches the reproduced block address data by the block address valid flag. 7. The data reproducing device according to claim 3, wherein the representative block address data output by the block address processing unit is used in place of the reproduction block address data output by the demodulation unit. 8. A majority decision circuit comprises: a selector for switching reproduction block address data of a plurality of channels; a comparator for the number of channels for comparing output data of the selector with reproduction block address data for the number of channels; And an adder for adding the match flags output from the comparators corresponding to the number of channels, and a determination unit for outputting a block valid flag based on the output result of the adder and the block address detection flag of the current channel. The data reproducing apparatus according to claim 7, which is characterized in that.