JPH07143457A - Memory control circuit for muse decoder - Google Patents

Abstract

PURPOSE:To eliminate the need for memories other than a FIFO memory for a motion correction memory for a MUSE signal. CONSTITUTION:An output of a FIFO memory 2 is fed to a 1st memory 5 of 1H memories 5-8 connected in cascade. Outputs of the memories 5-8 and an output of the FIFO memory 2 are given to each input terminal of selectors 9, 10. A memory control means 4 sets a delay of the FIFO memory to either a delay required for a luminance signal or a delay required for a color difference signal depending on a vertical vector signal which is smaller. When the selectors 9, 10 are controlled, they are controlled depending on an absolute value of the difference between the delay required for the luminance signal and the delay required for the color difference signal to obtain a vector correction signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to MUSE (Mulitiple
Sub-nyquist Sampling Encoding) The present invention relates to a control circuit when a memory for performing vector correction of a decoder is configured by a general-purpose FIFO memory.

[0002]

2. Description of the Related Art Recently, as a next-generation television system,
A high-definition television system called high definition has been developed. High-definition broadcasting uses a band compression method called the MUSE method because it has a larger amount of information than conventional broadcasting.

FIG. 5 is an explanatory diagram of image transmission by the MUSE method. In the MUSE method, one screen of high-definition video is divided into four types of parts in the still image part, and this is transmitted over a time period of four fields. On the receiving side, the original screen is reconstructed by superimposing the screens for these four fields. In the moving image part, the movement becomes unnatural if one screen is transmitted in four fields like the still image part. Therefore, the original screen is reconstructed using only the last transmitted one field screen. . Therefore, the moving image portion has a smaller amount of information than the still image portion, so the resolution is deteriorated, but the human eye does not have a big problem because the moving portion has a low resolution.

As described above, in the MUSE system, band compression is performed based on the characteristics of human eyes. However, when the entire screen moves in the same direction such as when the camera moves up and down, left and right, the entire screen becomes a moving image, which may lead to a reduction in resolution. For this reason, the MUSE method has introduced a motion correction method called vector correction. In this, the encoder detects the amount of motion and the motion vector of the entire screen, and transmits this to the decoder as a control signal as a digital signal. In the encoder and the decoder, position correction is performed on the signal of the previous frame based on this motion vector signal, so that the entire screen becomes a moving image.

FIG. 6A shows an explanatory diagram of the motion vector correction method. In the MUSE method, vector correction is performed only on the luminance signal, and vector correction is not performed on the color difference signals. The MUSE method is based on TCI (Ti
The color difference signal is multiplexed in the horizontal blanking period of the luminance signal. now,
It is assumed that a signal as shown in (a) of FIG. 6A is input to the vector correction memory. In the figure, the portion labeled C is a color difference signal, and the portion labeled Y is a luminance signal. At this time, if no vector signal is input, the output of the motion vector correction memory becomes a signal as shown in (b). Since no motion vector is input to this signal, the input signal is simply delayed by a certain amount. Next, a case where the horizontal vector h is input is shown in (c). In this case, since the screen has moved to the right, a signal in which only the luminance signal of the MUSE signal is shifted to the right by h is output. Since the signal in the shaded area is not in the input signal, a signal of a constant level is output. The signal indicated by the dotted line is not output because it overflows. Next, a case where the vertical vector v is input is shown in (d). In this case, the screen is moved downward, and a signal in which only the luminance signal is shifted downward by v is output as in the case where the horizontal vector is input.

Now, consider a case where the motion vector correction memory is constructed by using a general-purpose FIFO (First In First Out) memory. The FIFO memory is a memory that is output in the order of input, and can give an arbitrary delay amount by giving a timing signal such as reset. This FIFO memory has been widely used in recent years as a memory for digital image processing such as a television receiver and a video tape recorder. However, when a vertical vector is input to the motion vector correction memory, as shown in (d), it is necessary to output a color difference signal up to (v-1) line and then a luminance signal for one line. It is necessary to change the order of signals.
For this purpose, a line memory or the like is used in addition to the FIFO memory to configure the motion vector correction memory.

FIG. 6B shows the configuration of a motion vector correction memory using a conventional general-purpose FIFO memory. The MUSE signal input from the terminal 31 is (112
1H-8) FIFO memory 3 with sample delay amount
It is delayed by 2 and input to the first line memory 41 (H means a horizontal period). Output of FIFO memory 32 and first to seventh line memories 41 to 44, 45 to 4
The outputs of 8 are input to the input terminals of the luminance signal selector 34, respectively. In the luminance signal selector 34, the terminal 3
An input signal is selected and output according to the vertical vector signal input from 3. For example, when the vertical vector is 0, the output of the fourth line memory 44 is selected. The signals selected at this time are (1121H delay−8 samples + 1H memory × 4) in the FIFO memory, that is, 11 in total.
The signal has a delay amount of 25H (1 frame) -8 samples. On the other hand, each time the vertical vector decreases by 1, a signal with a delay amount of 1H is selected. The output of the brightness signal selector 34 is input to the horizontal vector correction circuit 36. Horizontal vector correction circuit 36
Is a variable delay circuit of 0 to 15 clocks, and when the horizontal vector is h, it has a delay amount of (8 + h) clocks to perform horizontal vector correction. The output of the horizontal vector correction circuit 36 is a horizontal / vertical vector corrected signal, which is input to the selector 38. On the other hand, the output of the fourth line memory 44 is
Delay circuit 3 for color difference signals having a fixed delay amount of 8 clocks
Input to 7. The output of the delay circuit 37 is 1125H.
The signal has a delay amount of (= 1 frame) and is not vector-corrected. This signal is the selector 3
8 is input. The selector 38 selects the vector-corrected signal from the horizontal vector correction circuit 36 in the luminance signal period based on the signal indicating the luminance signal period and the color difference signal period input to the terminal 39, and in the color difference signal period, The vector-uncorrected signal from the delay circuit 37 is selected and led to the terminal 50.

[0008]

In the conventional circuit described above, in addition to the FIFO memory, 7H line memories 41 to
There is the problem of requiring 48. Therefore, the present invention reduces the memory other than the FIFO memory to reduce the cost of the MU.
It is an object to provide a memory control circuit of an SE decoder.

[0009]

The present invention provides a FIFO memory with a smaller delay amount of a delay amount DY required for a luminance signal and a delay amount DC required for a color difference signal so that a difference between DY and DC is given. The amount of delay is given to the external memory.

[0010]

By the above means, the required memory other than the FIFO memory can be reduced to 4H or less.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The signal introduced to the terminal 1 is the FIF controlled by the memory control circuit 3.
It is input to the O memory 2. In the memory control circuit 4, the FI
The delay amount of the FO memory 2 is set to the delay amount DY required for the luminance signal.
And the smaller delay amount DC required for the color difference signal is set. Here, the delay amount required for the motion vector correction memory when a vertical vector signal is input to the terminal 3 is shown in FIG.

In FIG. 2A, when the vertical vector amount is 0, a delay of just one frame (1125H) is set, and the luminance signal and the color difference signal have the same delay amount. When the vector quantity changes to -1, -2, ...
When a delay amount of 4H, 1123H, ... Is required and the vector amount changes to +1, +2 ,.
A delay amount of H, 1125H, ... Is required. The delay amount required for the color difference signal is constant and is 1125H. Here, FIG.
Looking at the absolute value of DY-DC as shown in (A), there is a maximum difference of 4H around 0, in order to obtain the same delay amount as the conventional one. This system focuses on this point.

Therefore, in this system, when the vertical vector is 0 or positive as shown in FIG.
The delay amount of the memory 2 is fixed to 1125H, and when the vector amount is negative, the delay amount is reduced by 1H from 1125H each time the vector amount is decreased by 1, and when the vertical vector is -4, the delay amount is controlled to 1121H.

For such control, the output of the FIFO memory 2 is input to the first line memory 5, the terminal a of the luminance signal selector 9 and the terminal a of the color difference signal selector 10. The output of the first line memory 5 is the second
Input to the line memory 6, the terminal b of the luminance signal selector 9 and the terminal b of the color difference signal selector 10. The output of the second line memory 6 is the third line memory 7, the terminal c of the luminance signal selector 9 and the color difference signal selector 10.
Input to the terminal c. The output of the third line memory 7 is input to the fourth line memory 8, the terminal d of the luminance signal selector 9 and the terminal d of the color difference signal selector 10. The output of the fourth line memory 8 is input to the terminal e of the color difference signal selector 10.

The luminance signal selector 9 and the color difference signal selector 10 are controlled by the memory control circuit 4 and are connected to the terminal 3
According to the amount of vertical vector signal input from FIG.
Selection control is performed in a mode as shown in (B) to selectively derive an input.

In this operation, a signal delayed from the output of the FIFO memory 2 by the absolute value of DY-DC is selected for the luminance signal and the color difference signal shown in FIG. It is like this.

The output of the luminance signal selector 9 is output to the terminal 11
The horizontal vector correction circuit 12 controlled by the input horizontal vector signal performs horizontal vector correction processing,
It is input to the selector 15. The output of the color difference signal selector 10 is output from the delay circuit 13 to the horizontal vector correction circuit 1.
It is delayed by the delay amount when the horizontal vector of 2 is 0 and input to the selector 15. The selector 15 selects the signal from the horizontal vector correction circuit 12 during the luminance signal period and the signal from the delay circuit 13 during the color difference signal period according to the signal indicating the timing of the luminance signal and the color difference signal input to the terminal 14. , From the terminal 16.

The above-mentioned functions are the same as the conventional ones, although the configurations are different. Although the correction of the delay amount of the horizontal vector correction circuit 12 when the vector is 0 is omitted in the present embodiment, in practice, the delay amount of the FIFO memory is set smaller by this delay amount.

As described above, in this system, the extraction position of the chrominance signal is not fixed by hardware and the luminance signal is corrected to the vertical movement position with this position as the center, but the temporal difference between the chrominance signal and the luminance signal is not corrected. Focusing on the deviation, the delay amounts of both are relatively controlled. As a result, the FIFO
You can minimize the required memory other than memory,
The entire hardware configuration can be simplified and cost reduction can be obtained.

FIG. 3 shows a second embodiment of the present invention.
In the first embodiment, the first to fourth line memories are not used simultaneously for the luminance signal and the color difference signal. MU
Since the SE signal uses the TCI method as shown in FIG. 4, it is possible to stop the operation of the line memory during the signal period which is not used. By doing so, it is possible to further reduce the memory.
The number of samples of the luminance signal of the MUSE signal is 760, the number of samples of the color difference signal is 190, which is a quarter of the luminance signal.
Referring now to FIG. 2, in the configuration using the present invention, F
It can be seen that a delay other than the IFO memory requires a maximum of 3H for the luminance signal (when the vertical vector is +3) and a maximum of 4H for the color difference signal (when the vertical vector is -4). The number of color difference signal samples is exactly one fourth of the number of luminance signal samples
Therefore, by dividing the luminance signal memory into four, it can be used as four color difference signal memories.
Therefore, all the memories other than the FIFO memory are required to have three 760 sample delays (the amount required for the maximum delay amount of the luminance signal = 3H), and one of them is divided into four 190 sample delays (delay of the color difference signal). Amount of maximum delay required for = 4
It turns out that it is good to use it as H).

The second embodiment will be described below with reference to the drawings. The MUSE signal input from the terminal 1 is input to the FIFO memory 2 controlled by the memory control circuit 4. The delay amount of the FIFO memory 2 is controlled by the vertical vector signal input from the terminal 3 as shown in FIG. The above is exactly the same as the case of the first embodiment. In this embodiment, when the vector is negative, the first
~ The fourth delay circuits 21 to 24 are used as delay circuits for four lines of color difference signals. At this time, the memory control circuit 4 outputs a timing signal for operating each color difference signal period to each delay circuit. When the vertical vector is 1 or more, the first
The fourth delay circuits 21 to 24 are treated as one luminance signal delay circuit, and are used as a delay circuit for three luminance signal lines together with the fifth and sixth delay circuits 62 and 63. At this time, the memory control circuit 4 outputs to each delay circuit a timing signal for operating only during the luminance signal period. FIF
Output of O memory 2 and each delay circuit 21-24, 62, 6
The output of 3 is input to the selector circuit 9. In the first embodiment, there are two selectors for the luminance signal and the color signal.
Although two selectors are used, the luminance / color difference signal selector 64 is used in the color difference signal period and the luminance signal period based on the signal indicating the luminance signal period and the color difference signal period input from the terminal 14.
The same function is realized by one selector by switching the signal selected by.

Since the operating principle itself is the same as that of the first embodiment, the selection operation mode of the luminance / color difference signal selector 64 is as shown in FIG. The operations of the horizontal vector correction circuit 12, the delay circuit 13, and the selector circuit 15 are exactly the same as those in the first embodiment. In the present embodiment, the first
In the embodiment, the functions of the luminance signal selector 9 and the color difference signal selector 10 are combined into one luminance / color difference signal selector 6.
Although it has been described with reference to the example realized in 4, the two selectors for the luminance signal and the color difference signal may be used. On the contrary, in the first embodiment as well, it goes without saying that the luminance signal selector 9 and the color difference signal selector 10 may be replaced with one luminance / color difference signal selector as in the second embodiment. In the present embodiment as well, the correction of the delay amount at the time of vector 0 of the horizontal vector correction circuit 12 is omitted, but in reality, the delay amount of the FIFO memory is set to be smaller by this delay amount. At the output of the above device, the absolute reference time is subjected to subsequent signal processing with the phase of the color difference signal as a reference.

[0023]

As described above, when the MUSE signal motion correction memory is configured using the FIFO memory, the FI
The memory other than the FO memory can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory view shown for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an operation explanatory view shown for explaining the operation of the circuit of FIG.

FIG. 5 is a diagram shown for explaining image transmission of the MUSE method.

FIG. 6 is a diagram illustrating an operation principle of motion vector correction and a correction circuit thereof.

[Explanation of symbols]

2 ... FIFO memory, 4 ... Memory control circuit, 5-8 ... 1
H memory, 9 ... Luminance signal selector, 10 ... Color difference signal selector, 12 ... Horizontal vector correction circuit, 13 ... Delay circuit.

Claims (5)

[Claims] 1. A memory for vertical vector correction of a MUSE decoder, comprising: a FIFO memory, and the FIFO memory having a smaller one of a delay amount required for a luminance signal and a delay amount required for a color difference signal according to a vertical vector signal. Memory control means for setting, delay means for four lines having an output for each line, selection means for selecting each output of the delay means for four lines and output of the FIFO memory, and according to the vertical vector signal Controlling the selection means,
A memory control circuit of a MUSE decoder, comprising: a control unit that controls the delay unit according to an absolute value of a difference between a delay amount required for a luminance signal and a delay amount required for a color difference signal. 2. The MUS according to claim 1, wherein the delay means for four lines comprises four delay circuits each having a delay amount for one line.
Memory control circuit of E decoder. 3. The delay means for the four lines includes four first delay circuit groups each having a delay amount of the number of color difference signal samples included in one line, and a number of luminance signal samples included in each line. A second delay circuit group having a delay amount, the control means operating the first delay circuit group only during a color difference signal period when the vertical vector signal is negative; 2. The memory control circuit of the MUSE decoder according to claim 1, further comprising means for operating the first and second delay circuit groups only during a luminance signal period when the signal is positive. 4. The selection means comprises a luminance signal selector to which each output from the delay means and an output from the FIFO memory are supplied to each input terminal, and a color difference signal selector. The memory control circuit of the MUSE decoder according to claim 1. 5. The selection means comprises a common selector for luminance signals and chrominance signals to which respective outputs from the delay means and outputs from the FIFO memory are supplied to respective input terminals. The memory control circuit of the MUSE decoder according to claim 3.