JPH07143013A - Input register circuit - Google Patents

Abstract

PURPOSE:To obtain an input register circuit in which a problem of its large momentary current is solved, the transfer of large amount of data in one cycle is not required and the momentary current is small CONSTITUTION:Sixteen cycles are set as one operation unit, and write on shift registers 111-118 in a shift register group 110 and the parallel output by every two bits of the data or shift registers 121-128 in a shift register group 120 are performed in eight cycles in the first half. On the other hand, the write on the shift registers 121-128 in the shift register group 120 and the parallel output by every two bits of the data in the shift registers 111-118 in the shift register group 110 are performed in eight cycles in the latter half adversely to the first half.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in, for example, a video conference system, a video telephone, etc., and is used for compressing and encoding image data in digital image processing, and a Discrete Cosine Transform,
Hereinafter referred to as DCT) and inverse transform (Inverse Discrete C)
The present invention specifically relates to an input register circuit provided in a circuit such as a osine transform (hereinafter referred to as IDCT) circuit.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference: Japanese Patent Application Laid-Open No. 4-17464 FIG. 2 shows a conventional DCT / IDCT described in the reference.
FIG. 3 is a schematic configuration block diagram showing a configuration example of an apparatus. This DCT / IDCT device uses the forward conversion command F to generate the first dimension D
It has a first-dimension DCT / IDCT calculation unit 10 that performs CT calculation and performs first-dimension IDCT calculation with an inverse transformation command I. The first-dimensional DCT / IDCT operation unit 10 is connected to an intermediate random access memory (hereinafter referred to as RAM) 20. Intermediate RAM
Reference numeral 20 is a circuit that stores the calculation result of the first-dimensional DCT / IDCT calculation unit 10. Further, the intermediate RAM 20 has 2
It is connected to the three-dimensional DCT / IDCT calculation unit 30.
The second-dimensional DCT / IDCT operation unit 30 uses the forward conversion command F
Is a circuit for performing the second-dimensional DCT operation with the inverse transformation command I.

Next, the operation of this DCT / IDCT apparatus will be described. The first-dimensional DCT / IDCT calculation unit 10 receives the row-direction input signal IN of the image block, performs the first-dimensional DCT calculation with the forward conversion command F, and performs the first-dimensional IDCT calculation with the inverse conversion command I. In the videophone, the image is compressed by the forward conversion command F at the time of transmission, and is restored to the original image at the transmission source by the reverse conversion command I at the time of reception from the other party. Intermediate R
The AM 20 stores the calculation result of the calculation unit 10. The second-dimension DCT / IDCT operation unit 30 uses the forward conversion command F for the second-dimension DC for the column-direction data stored in the RAM 20.
The T calculation is performed, the second-dimensional IDCT calculation is performed using the inverse conversion command I, and the calculation result S30 is output. FIG. 3 is a schematic configuration block diagram showing a configuration example of the first-dimensional DCT / IDCT calculation unit 10 in FIG. The second-dimensional DCT / IDCT calculation unit 30 has basically the same configuration. This arithmetic unit 10
Includes an input register circuit 11 that sequentially receives and holds the input signal IN. The input register circuit 11 is connected to a parallel / serial (Parallel / Serial, hereinafter, P / S) conversion unit 12. The P / S conversion unit 12 is a circuit that receives the output signal S11 of the input register circuit 11 and sequentially transfers it serially from the least significant bit (LSB).
The P / S conversion unit 12 is connected to one input side of the preprocessing unit 13 and the switching unit 14. The pre-processing unit 13 uses the P / S
It is a circuit that receives the output signal S12 of the conversion unit 12 and performs a butterfly operation. The preprocessing unit 13 is connected to the switching unit 14. The switching unit 14 is a circuit that selects the output signal S13 of the preprocessing unit 13 or the output signal S12a of the P / S conversion unit 12 corresponding to the forward / reverse conversion command F / I. The switching unit 14 is a read-only memory (Read Only Memo).
ry, hereinafter referred to as ROM). The calculation ROM unit 15 is a circuit that outputs the calculation result S15 corresponding to the input signal of the switching unit 14. Calculation ROM section 15
Is connected to one input side of the post-processing unit 16 and the switching unit 17. The switching unit 17 is a circuit that selects the output signal S15a of the calculation ROM unit 15 or the output signal S16 of the post-processing unit 16 in accordance with the forward / reverse conversion command F / I. The switching unit 17 is connected to the accumulator 18. The accumulator 18 is a circuit that receives and accumulates the output signal S17 of the switching unit 17. The accumulator 18 is connected to the shift register 19. Shift register 19
Is an output circuit that receives and holds the output signal S18 of the accumulator 18, and outputs the output signal S19.

Next, the operation of the first-dimensional DCT / IDCT calculation unit 10 will be described. The input signal IN is sequentially input and held in the input register circuit 11. Next, the P / S converter 12 serially transfers the least significant bit (LSB). Further, the pre-processing unit 13 performs butterfly calculation. This preprocessing operation is necessary only in the case of DCT operation, and is bypassed in the case of IDCT operation. The bypassed signal S12a and the preprocessed signal S13 are selected by the switching unit 14 in accordance with the forward / reverse conversion command F / I. The output signal S14 of the switching unit 14 is
It is input to the calculation ROM unit 15. This calculation ROM section 15
Outputs a calculation result S15 corresponding to a predetermined input signal. The calculation result S15 is input to the post-processing unit 16. This post-processing operation is necessary only for IDCT and bypassed in the case of DCT operation. Bypassed signal S15a
The post-processed signal S16 is selected by the switching unit 17 according to the conversion mode. Output signal S1 of switching unit 17
7 is input to the accumulator 18 and accumulated. The result is input to and held in the shift register 19, and the output signal S19 is output. The forward / backward conversion command F / I is given to the switching units 14 and 17, and the input signals S13 / S12a and 15a corresponding to the modes of DCT calculation and IDCT calculation are input.
/ 16 are switched respectively. FIG. 4 is a schematic circuit diagram showing a configuration example of the input register circuit 11 of FIG. The input register circuit 11 includes registers 41 to 48.
Register group 40 and shift registers 51 to 58
And a shift register group 50 composed of The registers 41 to 48 are cascaded so that the output signal of the previous stage is sequentially input to the next stage. The output sides of the registers 41 to 48 are connected to the input sides of the shift registers 51 to 58, respectively. The shift registers 51 to 58 are
This is a circuit for fetching the output signals S41 to S48 of the registers 41 to 48 and outputting the least significant 2 bits. The output sides of the shift registers 51 to 58 are connected to the input sides of the P / S conversion section 12 of FIG. 3, respectively.

FIG. 5 is a time chart showing the operation of the input register circuit of FIG. 4, and the operation of the input register circuit of FIG. 4 will be described with reference to this figure. Cycles T1 to T
In eight cycles of 8, a total of eight 16-bit data IN are sequentially input to the registers 41 to 48, and all the registers 41 to 48 are ready to be output in the cycle T9. In cycle T9, the output signals S41 to S48 of the registers 41 to 48 are transferred to the shift registers 51 to 58. Further, in the cycles T9 to T16, since the data IN is continuously input, the above operation is repeated,
The registers 41 to 48 sequentially store the data IN.
On the other hand, in the cycle T9, the shift registers 51 to 58 to which the data has been written repeat the operation of shifting the data IN to the right by 2 bits during the eight cycles of the cycles T10 to T17, and at the same time, the lowest ( LSB) 2
Bits S41 to S48 are output in parallel.

[0006]

However, the conventional input register circuit has the following problems. Eight registers 41-48 to eight shift registers 51-
Since the data of 16 × 8 bits is transferred when the data is transferred to the 58, there is a problem that the instantaneous current consumption becomes large and the noise and the ripple increase to adversely affect other circuits such as malfunction. It was SUMMARY OF THE INVENTION The present invention provides an input register circuit with a small instantaneous current consumption by reducing the amount of data transferred in one cycle in order to solve the problem that the prior art has a large instantaneous current consumption. is there.

[0007]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, n (however,
n has an integer of 1 or more), input data is taken into the shift register sequentially selected by the first control signal for n cycles, and m (however, of each taken data) m is an integer greater than or equal to 1 smaller than n) and outputs the bits in parallel during the next n cycles.
Of shift registers and n shift registers,
While the first shift register group is performing an output operation, the input data is fetched into the shift register sequentially selected by the second control signal, and after the output of the first shift register group is finished, the fetch is performed. The second bit that outputs m bits of each input data in parallel during the next n cycles
Shift register group. Further, n selection means for selecting and outputting any one of the output signals of the first and second shift register groups based on a third control signal and the first and second control signals are alternated. And a control circuit for outputting the third control signal corresponding to the above. In the second invention, a control circuit for outputting a control signal to the input register circuit, an input dividing means for dividing the input data into n pieces (where n is an integer of 1 or more) and outputting the input data, and the input data. Based on the control signal, two types of output operations are sequentially performed, that is, an output operation of sequentially inputting from the previous stage to the next stage and outputting from the last stage, and an output operation of taking in the input data divided by the input dividing means, shifting and outputting in parallel Selectively cascaded n shift registers, output dividing means for dividing the output signal of the final stage of the n shift registers into n pieces, and outputting each output signal of the output dividing means or And n selection means for selecting and outputting one of the output signals output in parallel from the n shift registers based on the control signal. Further, each of the shift registers has a first input terminal for receiving the input data, and a first output terminal for outputting the input data captured from the first input terminal,
A second input terminal for taking in the input data divided by the input dividing means and m based on a clock signal for the input data taken in from the second input terminal (where m is an integer greater than or equal to 1 and smaller than n) A second output terminal for shifting and outputting bit by bit, and a control input terminal for inputting the control signal for selecting one of the input data fetched from the first or second input terminal. There is.

[0008]

According to the first aspect of the invention, since the input register circuit is configured as described above, the n shift registers of the first shift register group sequentially take in input data during n cycles, and Each fetched data is shifted by m bits and output in parallel during the next n cycles. or,
The n shift registers of the second shift register group sequentially take in input data while the first shift register group is performing an output operation, and after the output of the first shift register group is completed, The input data thus fetched is shifted by m bits and output in parallel for the next n cycles. Further, the n selection means select and output one of the output signals of the first and second shift register groups. The control circuit controls alternating use of the first and second shift register groups and which shift register in one shift register group the input data is written to. According to the second aspect of the invention, the cascaded connection of the n shift registers takes in the input data from the first input terminal, sequentially inputs the fetched data from the previous stage to the next stage, and the first stage of the final stage. Output from the output terminal. Also, the input dividing means divides the input data into n pieces, and the n shift registers take in the divided input data from the second input terminal and the input data taken in from the second input terminal. Are shifted by m bits based on the clock signal and output from the second output terminal. The output dividing means divides the output signal of the first output terminal of the final stage into n pieces and outputs the divided signal. Further, the n selection units select and output either one of the output signals divided by the output division unit and the output signal of each of the second output terminals. The control circuit
An input terminal for capturing data is selected from one of the first and second input terminals, and the output signals of the n selection means are output signals of the output division means and the second output terminals. Output a control signal for selecting from one of the output signals.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a schematic circuit diagram of an input register circuit provided in a conventional DCT circuit showing a first embodiment of the present invention.
This input register circuit includes control signals S100a and S00.
b, S00c output control circuit 100, input data D
A plurality of output signals that select and output any one of the output signals of the first shift register group 110 and the second shift register group 120 that take in IN, and the first shift register group 110 and the second shift register group 120. It is provided with selectors 131 to 138 which are selection means. The write enable terminals WE0 and WE1 of the control circuit 100 are connected to the write enable terminal WE0a of the shift register group 110 and the write enable terminal WE1b of the shift register group 120, respectively. Further, the control terminal S of the control circuit 100
Are commonly connected to the control input terminals of the selectors 131 to 138. The control circuit 100 includes one shift register for inputting the input data DIN as the shift register group 1
10 and the shift register group 120 to output the first and second control signals S100a and S100b, and the third control signal S100c for controlling the selectors 131 to 138. The shift register group 110 includes shift registers 111 to 118,
Based on the control signal S100a, the shift registers 111 to
One of the 118 is sequentially selected, 16-bit input data DIN is taken in from each input terminal D for 8 cycles, and the least significant 2 bits of the taken-in data are taken in during the next 8 cycles. It is a circuit that outputs in parallel from the output terminal Q. The shift register group 120, like the shift register group 110, has shift registers 121 to 128.
And the shift register group 110 is performing an output operation, the shift register 121 based on the control signal S100b.
1 to 128 are sequentially selected to capture 16-bit input data DIN from each input terminal D, and after the shift register group 110 finishes the output operation, the least significant 2 bits of each captured input data are input. It is a circuit that outputs from each output terminal Q in parallel during the next eight cycles.
The output terminals Q of the shift registers 111 to 118 and 121 to 128 are connected to the input terminals of the selectors 131 to 138, respectively. The selectors 131 to 138 control the output signals S111 to 118 and S121 to 128 of the shift register group 110 and the shift register group 120 to the control circuit 1.
Is a circuit for selecting and outputting output signals S131 to S138 based on the control signal S100c of 00.

FIG. 6 is a schematic circuit diagram showing a configuration example of the control circuit 100 shown in FIG. This control circuit 100 has four
Bit counter 101, 3-input 8-output decoder 102,
An inverter 103, eight 2-input AND gates 104,
105, and are connected as shown. FIG. 7 is a time chart showing the operation of the input register circuit of FIG. 1, and the operation of the input register circuit of FIG. 1 will be described with reference to this figure. In eight cycles T1 to T8, the control circuit 100 sequentially outputs the output signal S100a from the write enable terminal WE0 to “00000001” and “0000”.
0010 ”,“ 00000100 ”,“ 0000100
0 "," 00010000 "," 0010000 ",
It is output as "01000000" or "10000000". On the other hand, the output signal S100b output from the write enable terminal WE1 is "00000000". Therefore, one of the shift registers 111 to 118 in the shift register group 110 is selected and the input data DIN is written in one cycle, and the data is written to all of the shift registers 111 to 118 in eight cycles. The shift registers 111 to 118 are all ready to output in cycle T9. After that, cycle T
During 8 cycles of 9 to T16, the shift registers 111 to
The 118 outputs the least significant (LSB) 2 bits and repeats the 2-bit shift operation to the right. At this time, the selection control signal S100C output from the terminal S of the control circuit 100.
Is “O”, and the selection circuits 131 to 138 select the output signals S111 to S118 of the shift registers 111 to 118 in the shift register group 110 to output the output signal S131.
~ S138 is output.

On the other hand, in the eight cycles T9 to T16, the shift register 121 in the shift register group 120 is one cycle in the same manner as the cycles T9 to T16.
Input data DIN when any one of
Is written, and it takes 8 cycles to shift register 12
Data is written in all of 1 to 128. The shift registers 121 to 128 are all ready to output in cycle T17. After that, during the eight cycles T17 to T24, the shift registers 121 to 128 output the least significant (LSB) 2 bits and repeat the 2-bit shift operation to the right. At this time, the selection control signal S100C output from the terminal S of the control circuit 100 is "1",
The selection circuits 131 to 138 output the output signals S121 to S121 of the shift registers 121 to 128 in the shift register group 120.
S128 is selected and output signals S131 to S138 are output. In cycles T17 to T24, cycles T1 to T
The same operation as 8 is repeated. That is, 16 cycles are set as one operation unit, and in the first 8 cycles, writing to the shift registers 111 to 118 of the shift register group 110 and shift register 1 of the shift register group 120 are performed.
21 to 128 data are output in parallel. On the other hand, in the latter eight cycles, the shift register group 12
0 to the shift registers 121 to 128 and the shift registers 111 to 118 of the shift register group 110.
Output the data in parallel. As described above, in this first embodiment, when input data is input, the shift registers 111 to 11 in the shift register groups 110 and 120 are input.
Since only the data in any one of the shift registers 8 and 121 to 128 moves, the power consumption of the other shift registers becomes almost zero. Also, since 16-bit data is divided into 2 bits and shifted, the instantaneous current consumption is reduced. Therefore, noise and ripples are reduced, adverse effects such as malfunctions on other circuits are reduced, the power supply unit can be downsized, and the amount of heat generation can be reduced.

Second Embodiment FIG. 8 is a schematic circuit diagram of an input register circuit provided in a conventional DCT circuit showing a second embodiment of the present invention.
The input register circuit includes a control circuit 140 that outputs a control signal S140, an input dividing unit 150 that divides the input data DIN into 8 bits by 2 bits, shift registers 161 to 168 that capture the input data DIN, and output signals of the shift register 168. Output dividing means 170, and a plurality of selectors 181 to 188 for selecting one of the output signals of the output dividing means 170 and the output signal of each output terminal QB. Control circuit 14
The control terminal S of 0 is commonly connected to the control input terminals S / L of the shift registers 161 to 168 and the control input terminals of the selectors 181 to 188. The control circuit 140 is a circuit that outputs the control signal S140. Input dividing means 1
Reference numeral 50 is a circuit that divides the 16-bit input data DIN into 8 bits by 2 bits and outputs the divided data. Shift register 1
Reference numerals 61 to 168 denote a first input terminal DA for taking in the input data DIN, a first output terminal QA for outputting the taken-in data, a second input terminal DB for taking in the input data divided by the input dividing means 150, Second input terminal DB
Input data taken in from 2 based on the clock signal
There is provided a second output terminal QB for shifting and outputting by bits, and a control input terminal S / L for inputting a control signal S140 for selecting an input terminal for capturing data from one of the input terminals DA and DB. is doing. Furthermore,
The shift registers 161 to 168 are cascaded so that the input data DIN is sequentially input from the output terminal QA of the previous stage to the input terminal DA of the next stage from the previous stage to the next stage and is output from the output terminal QA of the shift register 168 of the final stage. Has been done. The output terminal QA of the shift register 168 is the output dividing means 1
It is connected to the input side of 70. Output dividing means 170
Is the output signal S of the output terminal QA of the shift register 168.
168a is a circuit that divides the lower 2 bits into 8 pieces and outputs the divided pieces. The selectors 181 to 188 control the control signal S14.
It is a circuit that selects one of the output signals of the output dividing means 170 and the output signal S161b to S168b of each output terminal QB based on 0 and outputs the selected signal.

FIG. 9 is a schematic block diagram showing an example of the structure of the shift registers 161 to 168. This shift register is a delay flip-flop (hereinafter, D-FF).
That is) f1 to f16. Each D-FF f1
f16 is one data input terminal D, two output terminals Q
1, Q2, and one clock terminal C, respectively. Two-input selectors (hereinafter referred to as selectors) SL1 to SL16 for switching inputs to the D-FFs f1 to f16 based on the control signal S140 are connected to the input terminals D of the D-FFs f1 to f16, respectively. In this shift register, for example, when "0" is selected by the control signal S140, 16-bit data da1 to da16 are simultaneously sent from the input terminal DA to the selectors SL1 to SL.
It is taken into each D-FF f1 to f16 via 16 respectively. In addition, this shift register has a control signal S140.
When "1" is selected by, the 2-bit data db1 and db2 are fetched from the input terminal DB into the D-FFs f1 and f2 via the selectors SL1 and SL2, respectively, in synchronization with the clock signal CLK (not shown). D-FFf
Odd-numbered D arranged every other one of 1 to f16
-Each output terminal Q1 of FFf1, f3, f5, to f13
Are connected to the data input terminals D of the next odd-numbered D-FFs f3, f5, to f15 via selectors SL3, SL5, to SL15, respectively. Similarly, the output terminals Q of the even-numbered D-FFs f2, f4, f6, to f14
1 through selectors SL4, SL6, ... SL16,
These are connected to the data input terminals D of the next even-numbered D-FFs f4, f6, to f16, respectively. FIG.
9 is a time chart showing the operation of the input register circuit of FIG. 8, and the operation of the input register circuit of FIG. 8 will be described with reference to this figure. The control signal S140 is in the state of "1" during the eight cycles of the cycles T1 to T8, and the input data DIN input in each cycle is the shift register 161-1.
Data is sequentially written to the respective input terminals DA of 68. The output signal S168a of the shift register 168 is output from the selectors 181 to 181.
It is output via 188. 8 of cycles T9 to T16
During the cycle, the control signal S140 is in the state of "0", and each shift register 161 to 168 executes a shift operation by 2 bits to the right every cycle. At the same time, the input data DIN is divided by the input dividing means 150 into 8 bits of 2 bits each and written into the respective input terminals DB of the shift registers 161 to 168. After eight cycles, each shift register 161 to 168 finishes the right shift operation of all the data, and outputs the least significant 2 bits from each output terminal QB in the section, and outputs the output signal S
161 to 168 are output via the selectors 181 to 188. In the cycles T9 to T16, the data input from the input terminal DB by dividing the data by 2 bits into 8 times fills all the bits of the shift registers 161 to 168.
The content is equal to the data on the input data DIN in which eight specific 2-bit data are arranged. Therefore, in the next cycle T17 to T24, the cycle T
By repeating the operation from 1 to T8, the cycle from T9 to
At T16, the same type of data as the data output via the selectors 181 to 188 is output.

As described above, in the second embodiment, as in the first embodiment, 16-bit data is divided and shifted by 2 bits, and the instantaneous current consumption is reduced. Further, since the number of registers used is half that of the conventional one, the power consumption is about half that of the conventional one. Therefore, noise and ripples are reduced, adverse effects such as malfunctions on other circuits are reduced, the power supply unit can be downsized, and the amount of heat generation can be reduced.
The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) The shift register groups 110 and 120 shown in FIG.
Similar to the conventional register group 40 of FIG. (B) The number of shift register groups in FIG.
It can be changed according to the number of N bits. (C) The control circuit 100 of FIG. 1 may use a counter or the like. (D) The input division circuit 150 of FIG.
You may comprise by a gate etc. (E) The output division circuit 170 shown in FIG.
You may comprise by a gate etc. (F) The input register circuit of FIGS. 1 and 8 can also be used for the input section of another arithmetic processing circuit.

[0015]

As described in detail above, according to the first aspect of the invention, the first and second shift register groups for fetching and shifting the input data are provided, and the data are alternately output. Instantaneous current consumption can be reduced without transferring a large amount of data at one time. Therefore, noise and ripple can be reduced and other circuits are not adversely affected such as malfunction. Further, the power supply unit that supplies power to the first and second shift register groups can be downsized, and the amount of heat generation can be reduced. According to the second invention, the input data is taken in, the data is directly written to the plurality of shift registers for shifting, the operation of the shift registers is shifted to the right by 2 bits, and the data is passed between the respective shift registers. Since two types of operations, that is, an operation to perform, are provided, a large amount of data is not transferred at one time, and a reduction in instantaneous current consumption can be expected. Therefore, noise and ripples are reduced, adverse effects such as malfunctions on other circuits are reduced, the power supply unit can be downsized, and the amount of heat generation can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an input register circuit showing a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a conventional DCT / IDCT apparatus.

3 is a schematic block diagram of the first-dimensional DCT / IDCT circuit of FIG.

FIG. 4 is a schematic circuit diagram of a conventional input register circuit.

FIG. 5 is a time chart of FIG.

FIG. 6 is a schematic block diagram of a control circuit of FIG.

FIG. 7 is a time chart of FIG.

FIG. 8 is a schematic circuit diagram of an input register circuit showing a second embodiment of the present invention.

9 is a schematic configuration block diagram of a shift register in FIG.

FIG. 10 is a time chart of FIG.

[Explanation of symbols]

110, 120
Shift register group 111-118, 121-128, 161-168
Shift register 100,140
Control circuits 131 to 138, 181 to 188
selector

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 1/41 B 7/30 H04N 7/133 Z

Claims (2)

[Claims] 1. An n-number (where n is an integer of 1 or more) shift register is provided, and the input data is fetched into the shift register sequentially selected by a first control signal for n cycles and then fetched. M of each data (however, m
Has a first shift register group that outputs in parallel 1 or more bits smaller than n) during the next n cycles, and n shift registers, and the first shift register group performs an output operation. While inputting the input data to the shift register sequentially selected by the second control signal, and after the output of the first shift register group is completed, m bits of each input data that have been input are transferred to the next shift register. Of the second shift register group which outputs in parallel for n cycles of n, and n which selects and outputs one of the output signals of the first and second shift register groups based on the third control signal.
A plurality of selecting means, alternately outputting the first and second control signals,
An input register circuit comprising: a control circuit that outputs the third control signal correspondingly. 2. A control circuit which outputs a control signal, an input dividing means which divides input data into n pieces (where n is an integer of 1 or more) and outputs the input data, and the input data sequentially from the previous stage to the next stage. Cascade connection is performed by selecting two types of output operation based on the control signal: an output operation for inputting and outputting from the final stage and an output operation for taking in input data divided by the input dividing means, shifting and outputting in parallel. N shift registers, output dividing means for dividing the output signal of the final stage of the n shift registers into n pieces, and outputting each output signal of the output dividing means or the n shift registers. From one of the respective output signals output in parallel from the above, and n number of selecting means for selecting and outputting based on the control signal, each shift register having a first input terminal for receiving the input data. A child, a first output terminal for outputting the input data taken in from the first input terminal, a second input terminal for taking in the input data divided by the input dividing means, and a second input terminal A second output terminal for shifting the input data taken in by m (where m is an integer of 1 or more smaller than n) bits based on the clock signal, and outputting the data; and a second output terminal taken in from the first or second input terminal. An input register circuit for inputting the control signal for selecting any one of the inputted input data.