JPH07142591A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the number of manufacturing steps, which are increasing with the miniaturization of an element, and to decrease the manufacturing cost by forming the source/drain region of a CMOS structure by one patterning in a self-aligning mode. CONSTITUTION:A resist film 6 is formed on a PMOS region. With the film 6 as a mask, ion implantation is performed, and a shallow N-type high- concentration impurity-diffused-layer region 7 is formed. Thereafter, a silicon nitride film 8 is selectively grown in a region other the resist film 6 by a liquid- phase growing method. The silicon nitride film 8 is made to remain only at the side wall of the gate electrode of an NMOS by anisotropic etching, and ion implantation is performed. Thus, the deep N-type high-concentration impurity-diffused-layer region 7 is formed. A silicon oxide film 9 is selectively grown in a region other than the resist film 6. After the resist film 6 is peeled, ion implantation is performed, and a shallow P-type high-concentration impurity- diffused-layer region 10 is formed. A silicon nitride film is deposited again. After anisotropic etching, ion implantation is performed, and the deep P-type high-concentration impurity diffused region 10 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a CMOS by performing ion implantation in a self-aligned manner.

[0002]

2. Description of the Related Art A high-density, high-performance LSI is realized by shortening the gate length of a MOS element according to a scaling rule. However, as the densification and performance increase, the manufacturing process steps become more complicated, and the number of manufacturing steps is increasing significantly.

Taking DRAM as an example, 256K, 1MD
The number of processes was 200,300 in RAM, but 4MDRA
It is 400 in M, and is expected to reach 550,700 in 16M, 64M DRAM. The increase in the number of manufacturing steps is largely due to the increase in the number of times of patterning by lithography, which causes major problems such as a large increase in manufacturing cost and a sharp decrease in the yield rate of products.

Also, focusing on the element level, a normal C
In the MOS process, patterning by lithography is performed four times to form a source / drain region having a shallow junction and a deep junction such as an LDD structure. 5 and 6 show the manufacturing method. When the gate processing is performed using a normal CMOS process, the cross section shown in FIG. 5A is obtained. That is, the P-type impurity region 2 is formed on the N-type semiconductor substrate 1, and the silicon oxide film 3 by LOCOS is formed.
A gate electrode is provided in each of the regions separated by (1) through a gate insulating film 4. Next, the first patterning is performed to form a resist film 6 so that the PMOS region is not ion-implanted. Arsenic ions are implanted using this as a mask to form the shallow N-type high-concentration impurity diffusion layer region 7 shown in FIG. 5B. After removing the resist film 6, 2
By performing the patterning for the second time, the resist film 6 is formed this time so that ions are not implanted into the NMOS region. Boron ions are implanted using this as a mask to form the shallow P-type high-concentration impurity diffusion layer region 10 shown in FIG. 5C.
After removing the resist film 6, a silicon nitride film 8 is formed on the side wall of the gate electrode, followed by third and fourth patterning and first self-aligned ion implantation.
As in the second time, the deep N-type high concentration impurity diffusion layer region 7 shown in FIG. 6A and the deep P-type high concentration impurity diffusion layer region 10 shown in FIG. 6B are sequentially formed. If this manufacturing process can be performed by patterning only once, the number of manufacturing steps and the manufacturing cost will be significantly reduced.

[0005]

As described above, in the conventional method, an increase in the number of manufacturing steps associated with the miniaturization of elements has become a very serious problem.

An object of the present invention is to propose a manufacturing method for reducing the number of manufacturing steps and manufacturing costs.

[Constitution of Invention]

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a step of covering a part of a semiconductor substrate with a first protective film and the semiconductor substrate not covered with the first protective film. And a step of selectively forming a second protective film on the semiconductor substrate other than the first protective film by a liquid phase growth method, and a step of forming the first protective film. It is characterized by comprising a step of removing and a step of performing impurity diffusion on the semiconductor substrate not covered with the second protective film.

[0009]

According to the present invention, by one patterning,
Since the source / drain regions of the CMOS structure can be formed in a self-aligned manner, the number of manufacturing steps is reduced and the manufacturing cost is significantly reduced.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show a C according to an embodiment of the present invention.
It is a manufacturing step sectional view showing a method for manufacturing a MOSFET.
Hereinafter, the manufacturing method of the present invention will be described with reference to the drawings.

A normal CMOS process is used to form a P-type impurity region 2 on the N-type silicon substrate 1, and a silicon oxide film 3 is used for LOCOS type element isolation. After forming the gate oxide film 4, a polycrystalline silicon film 5 is deposited by the LPCVD method and patterned to form the gate electrode 5. FIG. 1A is a cross-sectional view when the processing of the gate electrode 5 is completed.

Next, patterning is performed by photolithography to form a resist film 6 on the PMOS region. Using this as a mask, arsenic ion implantation is performed to obtain a shallow N
A type high concentration impurity diffusion layer region 7 is formed. After that, the wafer is dipped in a saturated silicon nitride solution in which silicon nitride is dissolved in hydrofluoric acid to selectively grow the silicon nitride film 8 in a region other than the resist film 6. A cross section as shown in FIG. 1B is obtained by this liquid phase growth method.

Next, when the silicon nitride film 8 is anisotropically etched by RIE or the like, the resist film 6 is not etched and the silicon nitride film 8 is formed only on the side wall of the gate electrode of the NMOS.
Remains. After that, arsenic ion implantation is performed on the entire surface, and
As shown in (c), the deep N-type high-concentration impurity diffusion layer region 7
To form.

Then, the wafer is immersed in a saturated solution of silicon oxide in which quartz is dissolved in hydrofluoric acid until saturated,
A silicon oxide film 9 is selectively grown in a region other than the resist film 6. After removing the resist film 6, boron ion implantation is performed to form a shallow P-type high-concentration impurity diffusion layer region 10 as shown in FIG. At this time, the silicon oxide film 9 serves as a mask, and boron is not hit on the NMOS region.

The wafer is again immersed in a saturated silicon nitride solution to deposit a silicon nitride film. Next time,
Since there is no resist film, the silicon nitride film grows on the entire surface of the wafer. Anisotropic etching is performed to leave the silicon nitride film 8 on the sidewall of the PMOS gate electrode, and a deep P-type high-concentration impurity diffusion layer region 10 is formed by boron ion implantation. Finally, dilute hydrofluoric acid treatment is performed to form the silicon oxide film 9
2B is removed, the cross section becomes as shown in FIG. Although the silicon nitride film 8 remains on the element isolation region 3, there is no problem if it is left as it is. After that, if necessary, it is possible to form the metal silicide in a self-aligned manner.

As described above, the CMOSFET is completed.
An example of the physical quantity of each element is shown below. The impurity concentration of the silicon substrate 1 is 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ ,
The impurity concentration of the P-type impurity region 2 is 1 × 10 ¹⁶ cm ^{−3 to 1} × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the impurity diffusion regions 7 and 10 is 1 × 10 ¹⁸ cm ^{−3 to 1} × 10 ²⁰ cm ⁻³ , respectively. The depth of the deep impurity diffusion region 7 is 1000Å to 20
The depth of the shallow impurity diffusion region 10 is 00Å to 300Å to 1000Å. In some cases, the impurity concentration of the shallow impurity diffusion region may be made smaller than the impurity concentration of the deep impurity diffusion region to further suppress the short channel effect.

In this way, the source / drain structure exactly the same as that shown in FIG. 6B is obtained in a self-aligned manner by patterning once. As a result, the number of steps is reduced, and the selective growth and etching shown here can be realized at low cost as compared with lithography, so that the manufacturing cost can be significantly reduced.

3 and 4 are sectional views of manufacturing steps showing another method of manufacturing a semiconductor device according to the embodiment of the present invention.
In the above embodiment, the NMOS and the PMOS have a completely symmetrical structure, but as shown below, the asymmetric CMOS is used.
It is also possible to manufacture

In this embodiment, the same steps as in the previous embodiment are performed until the diffusion layer region 10 is formed in FIG. 2 (a).
That is, FIG. 3A is a cross section immediately after the ion implantation of the NMOS is completed and the resist film is peeled off. After that, the silicon nitride film 8 is deposited without boron ion implantation and anisotropically etched to leave the silicon nitride film 8 on the side wall of the gate electrode of the PMOS. Then, boron ions are implanted to form a shallow P-type high-concentration impurity diffusion layer region 10 as shown in FIG. 3B. Here, since the silicon nitride film 8 exists, the region 10 does not enter directly under the gate electrode 5. Next, as shown in FIG.
The silicon oxide film 11 is again formed on the entire surface, and the silicon oxide film 9 is left on the side wall of the gate electrode 5 by anisotropic etching (FIG. 4A). As a result, the double film 8,
9 is formed. Finally, boron ions are implanted using the double films 8 and 9 and the gate electrode 5 as a mask to form a P-type high-concentration impurity diffusion layer region 10 to obtain the structure of FIG. 4B. The silicon oxide film 9 is appropriately removed using dilute hydrofluoric acid as needed.

Since it is difficult to achieve a shallow junction with boron as compared with arsenic, if a symmetric type is used as shown in FIG.
The short channel effect is worse in the PMOS. Figure 4 (b)
If it is made asymmetrical, the result is NMOS and PMO
The effective channel lengths of S can be made almost equal, and a CMOS with little short channel effect can be realized. As described above, according to the present invention, it is possible to simultaneously form an NMOS and a PMOS having different sidewall film thicknesses and structures without increasing the number of times of patterning.

The present invention can be variously modified and used without departing from the spirit thereof.

[0023]

As described above, according to the present invention, the source / drain regions of the CMOS can be formed in a self-aligning manner by patterning once, so that the number of manufacturing steps is reduced and the manufacturing cost is significantly reduced. Can be reduced to

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the invention.

2A to 2D are process cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the invention.

3A to 3C are process cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the invention.

FIG. 4 is a process sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the invention.

FIG. 5 is a process sectional view showing a conventional manufacturing method.

FIG. 6 is a process sectional view showing a conventional manufacturing method.

[Explanation of symbols]

 1 N-type silicon substrate 2 P-type impurity region 3 Element isolation region 4 Gate oxide film 5 Gate electrode 6 Resist film 7 N-type high-concentration impurity diffusion layer region 8 Silicon nitride film 9, 11 Silicon oxide film 10 P-type high-concentration impurity diffusion Layer area

Claims (1)

[Claims] 1. A step of covering a part of a semiconductor substrate with a first protective film, a step of diffusing impurities into the semiconductor substrate not covered with the first protective film, and a liquid phase epitaxy method. A step of selectively forming a second protective film on the semiconductor substrate other than the first protective film; a step of removing the first protective film; and a step of covering with the second protective film. And a step of diffusing impurities in the semiconductor substrate that is not present.