JPH0714016B2 - Semiconductor element mounting structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor element mounting structure, a carrier having a modifiable surface layer is interposed between an LSI package and a multilayer printed circuit board to achieve high-density mounting of the multilayer printed circuit board. It enables improvement of manufacturing yield and improvement of pattern damage countermeasures.

Further, by forming the terminating resistor on the carrier, the mounting efficiency is further improved.

[Industrial application field]

The present invention relates to a structure for mounting a semiconductor element on a printed circuit board, and more particularly to a high density mounting structure for an LSI package having a high density and a large number of input / output terminals.

The high integration of printed circuit boards and the high integration of LSIs have led to a marked increase in the number of pins for input / output terminals provided on LSI chips. It is being put to practical use.

Various types such as DIP and flat package are well known as the type of the package containing the LSI chip (hereinafter, referred to as the LSI package), but as described above in the small and limited package size due to the high mounting density of the printed circuit board. As a powerful method that can secure a large number of input / output terminals, a PGA (PIN GRID ARRAY) type, that is, a type in which a large number of input / output terminals are arranged in a matrix on the bottom surface of the package is superior in efficiency. It has been known.

Further, when it is discovered that there is a design error in the pattern wiring after forming the pattern wiring of the printed circuit board, especially the multilayer printed circuit board having the signal wiring inside, or when there is a short circuit in the printed circuit board. Has
You must make modifications to the circuit or repair the printed circuit board, or discard the printed circuit board,
Which one is taken depends on the economical efficiency, but as the high density mounting of the printed circuit board progresses as described above, the necessity for the remodeling and the economical efficiency are increasing.

In addition, as the density of printed boards is increased, the influence of defective products during manufacturing and the impact of non-modifiable failures are also increasing.

Therefore, there is a demand for a structure in which a PGA or other type of LSI package is mounted on a printed circuit board, which has high-density mounting, remodelability, and excellent manufacturing yield.

[Conventional technology]

The conventional structure for mounting a PGA type LSI package on a printed circuit board was to insert its input / output terminals into each through hole of the printed circuit board.

Therefore, the packaging density of the input / output terminals is limited to 100 mil (2.54 mm) pitch due to the restriction of the pattern condition of the printed board, which is very unsatisfactory in terms of increasing the density of the printed board.

Therefore, as a structure for mounting a PGA type LSI package on a printed circuit board, a method of abutting the input / output terminals of the LSI package without inserting into the through holes of the printed circuit board has been proposed. It has become possible to realize higher density mounting of printed boards without being restricted by wiring conditions.

FIG. 5 is a front view illustrating a conventional structure in which a PGA type LSI package is mounted on a printed board by such a butting method.

In FIG. 5, 10 is a multilayer printed circuit board, 20 is a PGA type LSI package, 21 is a plurality of input / output terminals or chip pins arranged vertically downward from the bottom surface of the LSI package 20, and 11 is a multilayer printed circuit board. 10 surface layers, 12 are pads formed on the surface layer 11 as a part of the pattern of the multilayer printed circuit board 10 and arranged in a matrix corresponding to the matrix arrangement of the input / output terminals 21,
Shown respectively.

On the other hand, it is important to secure remodelability as a problem in printed boards.

Previously, a modification structure was provided in which a pattern cut portion and a bonding pad were installed on the back surface of the printed board or the surface of the printed board located around the package.

This technology has the drawbacks that the required area for mounting on one semiconductor element becomes large and the mounting density becomes rough, and the number of layers of the multilayer printed circuit board increases because the inner layer compensates for the insufficient area of the surface layer of the multilayer printed circuit board. there were.

In order to solve this, Japanese Patent Application No. 61-21090 discloses a surface 13 of a multilayer printed circuit board located within the external dimensions of a semiconductor element.
(Fig. 5) I / O terminal connection pads, in-board wiring pattern connection pier pads, and a modification structure including a disconnection pattern connecting both pads at the time of modification are arranged for each I / O terminal 21. An improved technology that completes the changed or repaired pattern by cutting the disconnection pattern at the time of modification and connecting the input / output terminal connection pad and an appropriate modification pad provided separately by discrete wiring. It has already been disclosed.

According to this improved technology, since the surface 13 of the multilayer printed circuit board 10 located below the LSI package 20 is used, it is possible to minimize the area for the modification, and therefore, the multilayer printed circuit board of the multilayer printed circuit board 10 can be minimized. It can contribute to high-density mounting.

However, when the structure of this improved technique is adopted, a plurality of and fine surface shapes are required as the wiring pattern of the multilayer printed board.

In particular, in the case of a high-density package in which the lead pitch of the LSI package to be mounted is 1 mm or less, there is a problem that it is difficult to form the surface layer by a normal plating process.

Therefore, when the multilayer printed circuit board to be mounted is an organic material, it is practically difficult to realize the above-mentioned improved technique.

On the other hand, when the multilayer printed circuit board to be mounted is a ceramic substrate, it is possible to form a complicated and fine surface layer required for mounting the high-density package as described above on the ceramic substrate by the thin film technology. However, even in this case, particularly in order to increase the mounting unit to the multilayer printed circuit board as a recent tendency, when the size of the ceramic substrate which is the multilayer printed circuit board is increased, the yield of the complicated and fine surface layer is remarkably increased. There is a problem that it will decrease.

Further, in the above-mentioned improved technique, when a part of the surface layer of the multilayer printed circuit board is damaged which is difficult to repair, the entire multilayer printed circuit board has to be discarded, which is economically feasible. Is inferior.

Next, various types of semiconductor element circuits are currently used, but the semiconductor element circuit format for high-speed computers is ECL (EMITT) in terms of operation speed and integration.
The ER COUPLED LOGIC) circuit is the best.

When using the ECL circuit, it is necessary to provide a terminating resistor for each net in order to secure the level, and the mounting method of the terminating resistor is a major point for realizing high-density mounting.

FIG. 5 shows a terminating resistor module 41 mounted on the multilayer printed circuit board 10 on which the PGA type LSI package 20 is mounted.

The terminating resistor module 41 is mounted close to the LSI package 20 on the surface 14 of the multilayer printed circuit board 10 located outside the outer dimensions of the LSI package 20.

Therefore, the mounting area per one of the LSI package 20, the other dimensions of the LSI package 20, it is necessary to take a space corresponding to the size of the terminal resistor module 41, therefore, the pitch P ₀ of the LSI package 20 However, there is a problem in that the mounting density of the multilayer printed circuit board decreases as a result.

[Problems to be solved by the invention]

In this conventional method, the LSI package 20 is provided on the multilayer printed circuit board 1
Since it is directly mounted on the multi-layer printed circuit board, high-density mounting on the multi-layer printed circuit board is limited, and mounting density is reduced due to mounting the terminating resistor 41 on the multi-layer printed circuit board. There are various problems in that the yield in forming the shape is poor, and the entire multilayer printed circuit board must be discarded when the fine surface pattern is damaged.

The present invention was created in view of these points.
To provide a mounting structure of a semiconductor element that realizes high-density mounting of an I package on a multilayer printed circuit board, improves yield when forming a fine surface layer of the multilayer printed circuit board, and improves countermeasures against damage to the fine surface pattern. It is also an object of the present invention to provide a mounting structure of a semiconductor element capable of efficiently mounting a terminating resistor on a multilayer printed circuit board if necessary.

[Means for solving problems]

In the structure of the present invention, as shown in FIGS. 1 and 2, the carrier 30 is interposed between the multilayer printed circuit board 10 and the LSI package 20 mounted thereon.

The carrier 30 has a mounting surface on the multilayer printed board for mounting the carrier 30 on the multilayer printed board 10 and an LSI chip mounting surface for mounting the LSI package on the carrier.

The carrier 30 has, on the mounting surface thereof on the multilayer printed circuit board 10, solder joints 33 for electrically connecting to the surface pads 12 of the multilayer printed circuit board.

Further, the carrier 30 has a chip pin mounting pad 34, a wire bonding pad 35, and a pattern cut portion 36 on the LSI chip mounting surface.

The chip pins 21 of the LSI package 20 are mounted on the chip pin mounting pads 34.

The wire bonding pad 35 is a chip pin mounting pad
It is electrically connected to 34 and is used for connecting a modification wire during modification.

The pattern cut portion 36 is electrically connected to each of the wire bonding pad and the solder joint portion, and is for cutting at the time of improvement.

In the embodiment of the present invention, the matching termination resistor 40 is formed on the surface of the carrier.

In another embodiment of the present invention, the solder joints are arranged in a matrix on the mounting surface of the carrier on the multilayer printed board, and the chip pin mounting pads are arranged in a matrix on the LSI chip mounting surface of the carrier.

[Action]

In the structure of the present invention, the solder pad of the carrier is electrically connected to the surface pad 12 of the multilayer printed circuit board 10,
A chip pin mounting pad is electrically connected to the solder joint portion of the carrier via a pattern cut portion and a wire bonding pad, and a chip pin of the LSI package is mounted on the chip pin mounting pad of the carrier.

Therefore, in the mounted state of the LSI package, each chip pin of the LSI package is electrically connected to the surface pad of the multilayer printed board.

Also, since the electrical connection between the LSI package and the carrier is made by mounting the chip pins on the chip pin mounting pads, it is possible to use the butting type PGA type as the LSI package, which in turn leads to the mounting density of the multilayer printed circuit board. Can improve.

In order to carry out remodeling work in order to repair circuit design changes and multilayer printed circuit board failures, the pattern cut part in the circuit part to be remodeled is cut, and the wire bonding connected to the pattern cut part is performed. The pad is connected to another pad which is to form a new circuit with a modification wire.

In this way, a new circuit including the other pad, the remodeling wire, the wire bonding pad, the chip pin mounting pad and the chip pin corresponding thereto is constructed.

Since both the pattern cut part and the wire bonding pad that are the target of the modification work are provided on the LSI chip mounting surface of the carrier, the LSI package may be temporarily removed from the carrier and modified when necessary for modification. , Remodeling work is easy.

One of the major features of the present invention is a multilayer printed circuit board and an LSI.
The carrier having such a structure for modification is interposed between the package and the package, and as a result, the following advantages are obtained.

First, as a structure for modification, a fine surface shape may be formed on the surface of the carrier, and since the carrier has a size similar to that of an LSI package, which is much smaller than a multilayer printed circuit board, the manufacturing yield is large. To be improved.

Secondly, since it is not necessary to provide a modification structure on the multilayer printed circuit board, it is sufficient to form each surface pad corresponding to the solder joint portion of the carrier together with the normal pattern wiring, and in this respect also, the manufacturing is easy. And the manufacturing yield is improved.

Thirdly, if the surface pattern on the carrier is damaged for some reason and cannot be recovered, only that carrier needs to be replaced and other carriers and the multilayer printed circuit board are not affected. Therefore, the loss of one carrier is limited, and the economy is excellent.

Fourthly, since the carrier is interposed between the LSI package and the surface layer of the multilayer printed circuit board, a temperature hierarchy including the carrier is formed between the LSI package and the surface layer of the multilayer printed circuit board. The influence of the heat generated from the LSI package during the operation of the printed circuit board on the solder joint between the surface pad of the multilayer printed circuit board and the solder joint of the carrier is greatly mitigated, and therefore high reliability of the solder joint is realized. .

In the embodiment of the present invention, the matching terminating resistor is formed on the surface of the carrier. Therefore, when it is necessary to mount the terminating resistor by using the ECL circuit as the circuit type, the mounting structure of the terminating resistor is simplified. In addition, since it is not necessary to mount the terminating resistor directly on the surface layer of the multilayer printed circuit board, the area required for mounting the LSI package can be small, and therefore high density mounting is possible.

In another embodiment of the present invention, since the solder joints and the chip pin mounting pads are both arranged in a matrix, the chip pins of the LSI package can be arranged in a matrix, and the LSI package is of the PGA type. Can be used to implement multiple input and output terminals.

〔Example〕

1 to 4 show an embodiment of the present invention.
FIG. 2 is a front view, FIG. 2 is a perspective view showing a portion of the carrier 30,
FIG. 3 is a developed sectional view showing the mounted state of the LSI package, and FIG. 4 is a developed sectional view after the modification.

Structure In FIGS. 1 to 3, one carrier 30 is interposed between the multilayer printed board 10 of the ceramic board and the LSI package 20.

The LSI package 20 is a PGA type that uses an ECL circuit.
A large number of chip pins 21 extend vertically downward from the bottom surface of the SI package 20 in a matrix arrangement.

The carrier 30 is a flat plate having substantially the same external dimensions as the LSI package 20, and both surfaces thereof are a mounting surface 31 on a multilayer printed board and an LSI chip mounting surface 32.

The LSI package 20 is mounted on the LSI chip mounting surface 32 of the carrier 30.
The chip pin mounting pads 34 arranged in the same matrix as the chip pins 21 in the matrix arrangement, the wire bonding pads 35 electrically connected to the chip pin mounting pads 34 through the connecting portions 37, and the wire bonding pads 35.
And a pattern cut portion 36 electrically connected to the.

In the direction in which the pattern cut portion 36 extends from the wire bonding pad 35, the angular phase is shifted for each pattern cut portion 36 corresponding to the adjacent chip pin mounting pad 34, as shown in FIG.

Solder joints 33 are provided on the mounting surface 31 of the carrier 30 on the multilayer printed circuit board in a matrix-shaped arrangement that is out of phase with the matrix-shaped arrangement of the chip pin mounting pads 34.

Inside the carrier 30, the wire bonding pad
36 and the solder joint portion 33 are electrically connected to each other by the connecting portions 38A, 38B, 38C.

The intermediate connecting portion 38B extends in the lateral direction, and the extending direction is set to the adjacent chip pin mounting pad 34 as shown in FIG. 2 so as to match the angular phase shift of the pattern cut portion 36. The angular phase is shifted for each corresponding connecting portion 38B.

On the surface layer 11 of the multilayer printed circuit board 10, the surface pads 12 arranged in the same matrix as the solder joint portions 33 of the carrier 30 are formed.

39 is the solder joint 33 of the carrier 30 and the multilayer printed circuit board 10
Is a solder bump for soldering to the surface pad 12 of.

A matching termination resistor is provided on the LSI chip mounting surface 32 of the carrier 30 and around the area where the chip pin mounting pad 34 is formed.
40 is formed by thin film technology.

Mounting Procedure In the mounting structure of the semiconductor element of the present invention, the hierarchical structure of assembly can be set arbitrarily. An example of the mounting procedure will be described. Mainly in FIGS. Surface pads 12 arranged in a matrix on the surface layer 11 are electrically connected. At this time, the surface pad 12
Can be easily formed by an ordinary plating process or a thick film process.

In addition, the chip pin mounting pads 34 arranged in accordance with the arrangement of the chip pins 21 of each LSI package 20 and the solder joints arranged in accordance with the arrangement of the surface pads 12 of the multilayer printed circuit board 10.
33, a connection part 37 for electrically connecting these, a wire bonding pad 35, a pattern cut part 36, connection parts 38A, 38
Each carrier 30 having a structure having B and 38C and having a matching termination resistor 40 formed by a thin film technique is manufactured.

The carrier 30 is fixed and electrically connected to the multilayer printed board 10 by soldering the solder joints 33 of the carrier 30 to the surface pads 12 of the multilayer printed board 10 with eutectic solder of tin and lead.

By soldering each chip pin 21 of the LSI package 20 to each chip pin mounting pad 34 of the carrier 30 by low-temperature solder, the LSI package 20 is fixed and electrically connected to the carrier 30.

The semiconductor element mounting structure is thus completed.

Remodeling work Next, the remodeling work to be performed for the purpose of changing or repairing the circuit will be explained.

Pattern cut part corresponding to chip pin 21 that needs modification
Cut 36 as shown in FIG.

The wire bonding pad 35 connected to the pattern cut portion 36 is electrically connected to another appropriate pad by the modification wire 42.

As a result, the old circuit part is abolished and a new circuit part is constructed.

Functions and Effects of Embodiments Next, the functions and effects of the present invention will be described based on the embodiments.

Conventionally, in the case of providing a modification structure, the complicated and fine surface layer which should have been formed over the entire wide surface layer of the multilayer printed circuit board has substantially the same size as the LSI package 20 in this embodiment. Since it is sufficient to divide and form it on as many carriers 30 as there are LSI packages 20, the manufacturing yield can be greatly improved.

Also, if you want to recover the surface pattern on the carrier 30 if it gets damaged for some reason,
You only have to replace the 30 and it is very economical. Moreover, for that purpose, after the soldering between the carrier 30 and the multilayer printed circuit board 10 and the soldering between the carrier 30 and the LSI package 20 are released, the carrier 30 may be replaced and the same mounting procedure as described above may be performed. Recovery work is easy.

The shape of the surface pattern of the multilayer printed circuit board 10 is a carrier.
Only the surface butt for connecting the solder bumps 39 of 30 need be arranged, and therefore the pattern can be simplified.

Furthermore, as a side effect, since the carrier 30 has a structure in which it is inserted between a high heat-generating LSI chip and a ceramic substrate having a large heat capacity, the carrier 30 becomes a puffer of the temperature difference between the LSI package 20 and the multilayer printed circuit board 10, and Distortion can be dispersed and high reliability can be ensured.

Particularly when the substrate material is an organic material, a large thermal expansion difference occurs between the multilayer printed circuit board 10 and the LSI package 20 due to the temperature difference, and the carrier 30 serves as a buffer that absorbs this thermal expansion difference. Therefore, it is possible to obtain high reliability also in this respect.

Since the modification work may be performed on the surface of the carrier 30,
Its workability is excellent.

Since the terminating resistor 40 can be formed on the surface of the carrier 30 by a thin film technique, the mounting structure thereof can be simplified, and the mounting density can be improved by saving space.

〔The invention's effect〕

As described above, according to the present invention, the yield at the time of forming the fine surface layer is improved by interposing the carrier having the modified structure between the multilayer printed circuit board and the LSI package with a simple structure. However, measures against damage to the fine surface pattern have been improved, and high-density mounting of the LSI package on the multilayer printed circuit board has been realized. The efficient mounting on the multilayer printed circuit board enables higher density mounting, which is extremely useful in practice.

[Brief description of drawings]

1 is a front view showing an embodiment of the present invention, FIG. 2 is a perspective view showing a portion of the carrier shown in FIG. 1, FIG. 3 is a developed sectional view showing a portion where an LSI package is mounted, and FIG. Is a developed sectional view after modification, and FIG. 5 is a front view of a conventional structure. 1 to 4, 10 is a multilayer printed circuit board, 12 is a surface pad of the multilayer printed circuit board, 20 is an LSI package, 21 is a chip pin of the LSI package, 30 is a carrier, 31 is a carrier of the multilayer printed circuit board. A mounting surface, 32 is a carrier LSI chip mounting surface, 33 is a solder joint portion, 34 is a chip pin mounting pad, 35 is a wire bonding pad, 36 is a pattern cut portion, and 40 is a matching termination resistor.

Claims (3)

[Claims] 1. A carrier (30) is interposed between a multilayer printed circuit board (10) and an LSI package (20), and the carrier (30) mounts the carrier (30) on the multilayer printed circuit board (10). Mounting surface (31) on the multilayer printed circuit board and the carrier (30) for mounting the LSI package (20)
The carrier (30) has an LSI chip mounting surface (32) to be mounted on a surface pad (12) of the multilayer printed circuit board (10). The carrier (30) has a solder joint (33) for electrical connection, and the carrier (30) has a chip pin mounting pad for mounting the chip pin (21) of the LSI package (20) on the LSI chip mounting surface (32). (34) and a wire bonding pad (35) electrically connected to the chip pin mounting pad (34) and for connecting a modification wire during modification.
And a pattern cut portion (36) electrically connected to each of the wire bonding pad (35) and the solder joint portion (33) and for cutting at the time of remodeling, a semiconductor element mounting structure. . 2. The carrier (30) is the carrier (30).
2. The semiconductor element mounting structure according to claim 1, wherein a matching termination resistor (40) is formed on the surface of the semiconductor device. 3. The solder joint (33) on the mounting surface (31) of the carrier (30) on the multilayer printed circuit board (10).
Are arranged in a matrix, and the chip pin mounting pads (34) are arranged in a matrix on the LSI chip mounting surface (32) of the carrier (30). The semiconductor element mounting structure according to item 1.