JPH0713871A - Address control method of eeprom - Google Patents

Abstract

PURPOSE:To improve the security by preventing EEPROM data from being forged. CONSTITUTION:When a control ROM area 24b where 4 process routine P for EEPROM rewriting is called from a user program area 24a through a subroutine, a jump to a control ROM area 24b is made through a jump table 24c once. When this jump table 24c is referred to, an offset value (y) stored in a register 30 composed of an EEPROM is added by an adder 31 to call the process routine P assigned to a fixed address even when an entry address (x) which is different, user by user, is assigned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an electrically erasable non-volatile memory EEPROM (Electrically Erasable) incorporated in a microcomputer used for an IC (integrated circuit) card or the like and storing highly confidential data and the like. &
Programmable Read Only Memory) address control method.

[0002]

2. Description of the Related Art Conventionally, for example, an EEPROM incorporated in a microcomputer for an IC card stores highly confidential data, and therefore it is desirable that a third party cannot illegally rewrite the data. As a technique relating to such an IC card microcomputer, for example, there is one described in the following documents. Reference: Oki R & D, 57 [2] (1990-4) Bise et al. 39 is a functional block diagram showing one configuration example of the conventional IC card microcomputer described in the above-mentioned document. This IC card microcomputer includes a serial input / output terminal 1 for inputting / outputting a serial signal SIO to / from an IC card reader / writer, a power supply potential VDD (for example,
5 V) power supply terminal 2, a reset terminal 3 for inputting an inverted reset signal RES _N , a clock input terminal 4 for inputting a clock signal CLK, a power supply terminal 5 for GND (= 0 V), an internal data bus 6, Central processing unit (hereinafter C
PU), a semiconductor memory, and a register.

A CPU is a timing / control circuit 11 connected to terminals 2 to 5 for generating various timing signals and control signals, for example, an 8-bit arithmetic logic operation unit (hereinafter referred to as ALU) 12, and an operation result of the ALU 12. Register (B register) 13 for temporarily storing
It is composed of an accumulator (A register) 14 for accumulating the operation results of 12, a condition code register 15, and the like. The ALU 12, the auxiliary register 13, and the accumulator 14 are connected to the internal data bus 6. The condition code register 15 is connected to the serial input / output terminal 1 and also to the ALU 12 and the accumulator 14. The semiconductor memory includes a RAM (random access memory) 21 capable of reading and writing data at any time, a read-only ROM (read only memory) 24, and an EEPROM 26, which are connected to the internal data bus 6. The RAM 21 is addressed by the data pointer 22, a part of the RAM 21 is used as a push-down stack, and is addressed by the stack pointer 23. The ROM 24 is composed of, for example, a mask ROM, and is addressed by the program counter 25. This R
The OM 24 has a user program ROM area for storing application programs, an internal test and EEPRO.
And a control ROM area for storing an M access routine (processing routine). EEPROM 26
Is a memory for storing highly confidential data, and B
Addressing is performed by the pair register 27 of the register and the A register. The storage area of the EEPROM 26 cannot be executed as an instruction.

In the microcomputer of FIG. 2, when the power supply potential VDD is applied to the power supply terminal 2 and the clock signal CLK is input to the clock input terminal 4, various timings and control signals are output from the timing / control circuit 11. Occur. When the serial signal SIO is input from the IC card reader / writer to the serial input / output terminal 1, the serial signal SIO is input to the condition code register 15
Sent to. The program in the ROM 24 addressed by the program counter 25 is read, and the ALU 12, for example, outputs the serial signal SIO in accordance with the program.
And the data in the RAM 21 are subjected to arithmetic processing, and the arithmetic result is temporarily stored in the auxiliary register 13 or the accumulator 14 and stored in the RAM 21 or the like via the internal data bus 6. The data of the EEPROM 26 is stored by changing the threshold value of the transistor of the memory cell. Since this stored data requires particularly confidentiality (security), it is desirable that a third party cannot illegally rewrite the stored data. Therefore, as a security measure, conventionally, a rewrite preventing unit of the EEPROM 26 as shown in FIG. 3 is taken.

FIG. 3 is a diagram showing the ROM map of FIG. In the conventional method of preventing rewriting of the EEPROM 26, the procedure of data rewriting of the EEPROM 26 is converted into firmware, and the control RO is stored in the ROM 24 separately from the user program ROM area 24a.
An M area 24b is provided, and this control ROM area 24
EEPROM rewriting routine (processing routine) P in b
And the processing routine P is called by the entry address x stored in the user program ROM area 24a. This allows the EEPR
Even if the control method of the OM 26 is not disclosed to the user, the EEPROM 26 can be rewritten simply by calling the processing routine P which is a subroutine.
Further, the entry address x of the processing routine P is disclosed only to the minimum necessary person such as the user program creator,
By not disclosing the information to the public, end users such as IC card holders cannot illegally tamper with the EEPROM data.

[0006]

However, the conventional security measures have the following problems, and it is difficult to solve them. The processing routine P for rewriting the EEPROM 26 is placed on the ROM 24 composed of, for example, a mask ROM, and its entry address x is always the same, and even if different users use the same entry address x. There is. for that reason,
If the entry address x leaks from the user program creator to a third party, the end user will know how to rewrite the EEPROM data, and there is a risk that the alteration of the EEPROM data can be easily executed. As a preventive measure, there is also a method of changing the entry address x for each user or even for the same user at regular intervals. However, with this method, the mask ROM data must be recreated each time the entry address x is changed, which wastes cost and development time, and is not practical. The present invention solves the above problems and provides EEP
It is an object of the present invention to provide an EEPROM address control method capable of allocating a different entry address x to each user while the ROM rewriting processing routine P remains arranged at a fixed address.

[0007]

In order to solve the above problems, the present invention provides an E provided in a microcomputer.
The procedure for rewriting the EPROM data was converted to firmware and placed at a fixed address in the control ROM area.
In the EEPROM address control method in which the processing routine for rewriting the EPROM is called by the entry address in the user program ROM area, the following means are taken. That is, the entry address in the user program ROM area and the EEP
The offset value corresponding to the entry address stored in the register of the ROM structure is added, and the processing routine in the control ROM area is called via the jump table arranged at the added address. .

[0008]

According to the present invention, since the EEPROM address control method is configured as described above, the user program R
When making a subroutine call from the OM area to the control ROM area in which the processing routine for rewriting the EEPROM is arranged, the control ROM area is jumped once via the jump table. At the time of referring to the jump table, the offset value stored in the register configured by the EEPROM is added. As a result, even if a different entry address is assigned to each user, the processing routine for rewriting the EEPROM assigned to the fixed address can be called. Therefore, the above problem can be solved.

[0009]

1 is a functional block diagram showing an address control method for an EEPROM according to an embodiment of the present invention. Elements common to those shown in FIGS. 2 and 3 of the related art are designated by common reference numerals. There is. E which is the target of the address control method of this embodiment
The EPROM 26 is provided in the conventional microcomputer shown in FIG. 2, and the ROM 24 provided in the microcomputer has a user program ROM area 24a in which an entry address x is placed and an EEPR.
In addition to the control ROM area 24b where the processing routine P for OM rewriting is placed, the jump table 24 where the fixed address A assigned to the fixed address z is placed
c is provided. Further, in the microcomputer, for example, a register 30 configured by an 8-bit EEPROM for storing an offset value y, and an adder 31 for adding the entry address x and the offset value y to give a fixed address z to the jump table 24c. Is provided. In the above configuration, when the processing routine P of the control ROM area 24b in the ROM 24 is called from the user program ROM area 24a in the ROM 24, the entry address x of the call destination is set to
The fixed address z obtained by adding the offset value y previously stored in the register 30 by the adder 31 becomes the effective address. Since the fixed address z is the address of the jump table 24c, the processing routine P in the control ROM area 24b can be called via this jump table 24c.

Even if different entry addresses x ₁ , x ₂ , ..., X _n are assigned to each user, the offset values y ₁ , y ₂ , ..., Y _n corresponding to them are assigned to x _i +.
If y _i = z (where i; any value of 1 to n) is stored in the register 30 in advance, the fixed address A is also passed through the jump table 24c assigned to the fixed address z. It is possible to execute the processing routine P arranged in. For example, assume that the entry address x ₁ is assigned to a certain user U ₁ as 2010h. Further, it is assumed that the fixed address z of the jump table 24c is 2020h and the start address of the processing routine P is fixed to 3000h. Then, the offset value y ₁ for the user U ₁ is from _{x 1 + y 1 = 2020h,} 10h , and the
If this value 10h is written in the register 30, 201
By calling subroutine 0h, 300
The processing routine P in the control ROM area 24b starting from the address 0h can be executed. Here, if the offset value y _i stored in the register 30 is expanded to a negative number in the two's complement representation, the entry address x _i does not have to be before the fixed address z of the jump table 24c. For example, if another user U ₂ is assigned the entry address x ₂ to 2050h and the offset value y ₂ is D0h, x ₂ + y ₂ = 2020h, and the same processing routine P can be called. This increases the degree of freedom in assigning the entry address x to the user.

As described above, in the present embodiment, even if different entry addresses x ₁ , x ₂ , ..., X _n are assigned to each user, the offset value y stored in the register 30 is set.
ROM that stores the firmware prepared by the manufacturer because it is only necessary to rewrite ₁ , y ₂ , ..., Y _n
There is no need to recreate the 24 mask ROM data many times, and the cost and development period can be reduced. Moreover, with such a simple structure, it is possible to prevent the data in the EEPROM 26 from being tampered with, which is a very effective means in terms of security. The present invention is not limited to the above embodiment, and various modifications are possible, for example, by changing the circuit configuration of the microcomputer in which the EEPROM 26 is provided to a circuit configuration other than that shown in FIG. 2 or providing it in a device other than the IC card. is there.

[0012]

As described above in detail, according to the present invention, the entry address in the user program ROM area and the offset value stored in the register are added, and the jump is placed at the added address. Since the processing routine in the control ROM area is called via the table, even if a different entry address is assigned to each user, it is only necessary to rewrite the offset value stored in the register. ROM that stores the firmware prepared in
The cost and development period can be reduced because data does not need to be recreated many times. Moreover, by changing the offset value of the register, the processing routine can be executed without disclosing the address of the processing routine of the fixed address, so that the secret address can be improved and the EEPROM can be improved.
It is possible to prevent unauthorized alteration of data and improve security.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an EEPROM address control method according to an embodiment of the present invention.

FIG. 2 is a functional block diagram showing a configuration example of a conventional IC card microcomputer.

FIG. 3 is a diagram showing a ROM map of FIG.

[Explanation of symbols]

 11 Timing / Control Circuit 12 ALU 13 Auxiliary Register 14 Accumulator 15 Condition Code Register 21 RAM 22 Data Pointer 23 Stack Pointer 24 ROM 24a User Program ROM Area 24b Control ROM Area 24c Jump Table 25 Program Counter 26 EEPROM 27 Pair Register 30 Register 31 Addition Device A, z Fixed address P Processing routine x Entry address

Claims (1)

[Claims] 1. An E provided in a microcomputer
The procedure for rewriting the EPROM data was converted to firmware and placed at a fixed address in the control ROM area.
In an EEPROM address control method in which a processing routine for rewriting EPROM is called by an entry address in a user program ROM area, the entry address in the user program ROM area and an EEPROM configuration register are stored. An address control method for an EEPROM, wherein an offset value corresponding to an entry address is added, and a processing routine in the control ROM area is called via a jump table arranged at the added address.