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JPH0713661A - Semiconductor integrated circuit and its using method - Google Patents

Semiconductor integrated circuit and its using method

Info

Publication number
JPH0713661A
JPH0713661A JP5145296A JP14529693A JPH0713661A JP H0713661 A JPH0713661 A JP H0713661A JP 5145296 A JP5145296 A JP 5145296A JP 14529693 A JP14529693 A JP 14529693A JP H0713661 A JPH0713661 A JP H0713661A
Authority
JP
Japan
Prior art keywords
power source
memory
circuit
capacitor
battery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5145296A
Other languages
Japanese (ja)
Inventor
Akihiko Okamoto
明彦 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5145296A priority Critical patent/JPH0713661A/en
Publication of JPH0713661A publication Critical patent/JPH0713661A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To operate a circuits and to hold data in a relatively short time without a battery or a power source connected from an outside at the time of using the circuit. CONSTITUTION:A memory circuit part M and a power source circuit part A are provided on the same substrate. In the power source circuit part A, a capacitor C constituted of a high dielectric is serially connected with a resistance R. First, a voltage is impressed from an outside power source to a power source terminal V, and charged in the capacitor C. Next, when the outside power source is disconnected, a charged charge Q is discharged through the resistance R, and current is supplied to the memory circuit M. The insulating film of the capacitor C is SrTiO3 whose area is 1cm<2>, thickness is 10A, and dielectric film constant is 200. For example, the current consumption of a memory circuit with 4000 gates is almost 0.3mumA, and when the voltage impressed from the outside power source is 10V, 6000 second = 100 minute memory holding can be attained. Thus, information can be transferred while secrecy can be held in an IC memory or an IC card, and information can be prevented from leaking by automatically deleting data after the lapse of a holding time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は演算回路または記憶回路
またはセンサー素子を有する半導体集積回路とその使用
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an arithmetic circuit, a memory circuit or a sensor element and a method of using the semiconductor integrated circuit.

【0002】[0002]

【従来の技術】半導体集積回路はコンピュータやテレ
ビ、各種制御システム等に広く用いられている。特に最
近ではICカード等の携帯用装置に組み込まれ、さらに
小型化、電圧化が進められている。ところで一般に半導
体集積回路はチップ外より一定電圧の電源を接続して使
用するものが多い。通常の場合、半導体集積回路はチッ
プホルダに実装され、ソケットに装着されて、電源を外
部より接続して動作する。通常の論理回路やRAM(ラ
ンダムアクセスメモリ)メモリ等では電源がなければ、
動作しない。無電源で記憶を保持できるメモリとしては
EEPROM(電気的に消去、書き込みができる読みだ
し専用メモリー)、フラッシュメモリ等が開発されてい
る。また電池を半導体集積回路とともに同一チップホル
ダ上に実装する場合もある。
2. Description of the Related Art Semiconductor integrated circuits are widely used in computers, televisions, various control systems and the like. In particular, recently, it has been incorporated in a portable device such as an IC card, and has been further miniaturized and made to have a higher voltage. By the way, generally, many semiconductor integrated circuits are used by connecting a power source of a constant voltage from outside the chip. In the usual case, the semiconductor integrated circuit is mounted on a chip holder, mounted in a socket, and operated by connecting a power source from the outside. If there is no power supply in a normal logic circuit or RAM (random access memory) memory,
Do not work. As a memory that can hold a memory without a power source, an EEPROM (a read-only memory that can be electrically erased and written), a flash memory, and the like have been developed. Further, the battery may be mounted on the same chip holder together with the semiconductor integrated circuit.

【0003】[0003]

【発明が解決しようとする課題】携帯用装置では小型
化、軽量化が期待され、電池は携帯用装置として大きな
障害となっている。電池はその化学的性格上、危険性を
伴ったり、有害廃棄物として処理する必要が生じる。
The portable device is expected to be smaller and lighter, and the battery is a major obstacle for the portable device. Due to the chemical nature of batteries, batteries are dangerous and need to be treated as hazardous waste.

【0004】特開昭61−15537号公報には大容量
のコンデンサを時計用ICの電源供給部に接続して電源
断や電圧低下のときのバックアップとして使用すること
が記載されている。また実開昭63−19784号公報
にはICソケットにバックアップ用のコンデンサを設け
たものが記載されている。また特開平2−133728
号公報には揮発性のメモリICと同じプリント基板上に
バックアップ用電池とバックアップ用コンデンサを載せ
電池の交換時にこのコンデンサでバックアップすること
が記載されている。また特開平2−158892号公報
にはICカード用端末の電源として大容量のコンデンサ
を載せ、この電源を充電するため太陽電池も内蔵したも
のが記載されている。また特開昭62−7343号公報
にはICメモリのバックアップ電源回路として、電源ラ
インとICメモリ回路の間にコンデンサと電池を並列に
接続したものが記載されている。しかしこれらはいずれ
も外部電源あるいは電池をメモリまたは時計用IC回路
に接続して使用することを前提としており、前述と同じ
問題点がある。
Japanese Unexamined Patent Publication No. 61-15537 discloses that a large-capacity capacitor is connected to a power supply unit of a timepiece IC and used as a backup in case of power failure or voltage drop. Japanese Utility Model Laid-Open No. 63-19784 discloses an IC socket provided with a backup capacitor. In addition, JP-A-2-133728
The publication describes that a backup battery and a backup capacitor are placed on the same printed circuit board as the volatile memory IC, and backup is performed by this capacitor when the battery is replaced. Further, Japanese Patent Application Laid-Open No. 2-158892 discloses that a large-capacity capacitor is mounted as a power source for an IC card terminal and a solar cell is also built in to charge the power source. Further, Japanese Patent Application Laid-Open No. 62-7343 discloses a backup power supply circuit for an IC memory in which a capacitor and a battery are connected in parallel between a power supply line and the IC memory circuit. However, both of these are based on the assumption that an external power source or a battery is used by connecting to a memory or a timepiece IC circuit, and thus have the same problems as described above.

【0005】また電池の不要なEEPROMやフラッシ
ュメモリのような記憶素子では書き込みの場合、比較的
高い電圧が必要となる。
Further, in a memory element such as an EEPROM or a flash memory which does not require a battery, a relatively high voltage is required for writing.

【0006】本発明の目的は電池あるいは外部から接続
する電源なしに比較的短時間論理回路やセンサー素子を
動作させたり、データを保持することを可能とする半導
体集積回路とその使用方法を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit which can operate a logic circuit or a sensor element for a relatively short time and retain data without using a battery or a power supply connected from the outside, and a method of using the semiconductor integrated circuit. Especially.

【0007】[0007]

【課題を解決するための手段】本発明は同一基板上に演
算回路または記憶回路またはセンサー回路と、高誘電体
物質よりなる蓄電機能をもつ素子を有する半導体集積回
路である。
The present invention is a semiconductor integrated circuit having an arithmetic circuit, a memory circuit or a sensor circuit on the same substrate, and an element having a storage function made of a high dielectric material.

【0008】またこれは電池あるいは外部電源を接続し
て、蓄電機能を持つ素子に蓄電し、そのあと電池あるい
は外部電源を取り外して半導体集積回路を使用する。
Further, this is connected to a battery or an external power source to store electricity in an element having an electricity storage function, and then the battery or the external power source is removed to use a semiconductor integrated circuit.

【0009】[0009]

【作用】同一基板上に論理回路等と高誘電体よりなるコ
ンデンサを形成することにより、電荷を蓄積することが
できる。外部より電源ラインを接続せずに動作すること
が可能となり、電源の準備、接続の煩雑性がなくしかも
軽量になる。また電池をもっていないので繰り返し使用
することのない装置などでは使いすてができ、その際電
池の廃棄の問題がない。
By forming a capacitor made of a high dielectric material with a logic circuit or the like on the same substrate, it is possible to accumulate charges. It is possible to operate without connecting the power supply line from the outside, and there is no complexity of preparation and connection of the power supply, and it is lightweight. Also, since it does not have a battery, it can be used in a device that is not used repeatedly, and there is no problem of battery disposal at that time.

【0010】[0010]

【実施例】図1はこの発明の一実施例によるICメモリ
の電源回路の構成を示す図である。符号Vは”初期に”
直流電圧が印加される正電源端子であり、ダイオードD
1のカソードは電源ラインL1に接続されている。また
電源ラインL2は接地され、電源ラインL1,L2間に
ICメモリのメモリ回路Mが設置されている。また符号
Aは高誘電体よりなる電源回路部で電源ラインL1、L
2間に抵抗Rおよび高誘電体よりなるコンデンサCが直
列に配置されている。
1 is a diagram showing the configuration of a power supply circuit of an IC memory according to an embodiment of the present invention. Code V is "In the beginning"
A positive power supply terminal to which a DC voltage is applied, and a diode D
The cathode of No. 1 is connected to the power supply line L1. The power supply line L2 is grounded, and the memory circuit M of the IC memory is installed between the power supply lines L1 and L2. Reference numeral A is a power supply circuit section made of a high dielectric material, and power supply lines L1 and L
A resistor R and a capacitor C made of a high dielectric material are arranged in series between the two.

【0011】本構造において電源端子Vに直流電圧が供
給されている場合、ダイオードD1を介してメモリ回路
部Mに電力が供給され、また抵抗Rを通してコンデンサ
Cに電荷Qが蓄積される。次に電源端子Vから電源を切
り放すとコンデンサCに蓄積されている電荷Qが抵抗R
を介して放電される。そしてメモリ回路部に電荷が供給
される。
In this structure, when a DC voltage is supplied to the power supply terminal V, power is supplied to the memory circuit section M via the diode D1 and electric charge Q is stored in the capacitor C through the resistor R. Next, when the power source is cut off from the power source terminal V, the charge Q accumulated in the capacitor C is transferred to the resistor R.
Be discharged through. Then, charges are supplied to the memory circuit section.

【0012】図2は面積1cm2 、厚み10Aのキャパ
シタの誘電率と容量の関係である。バリウムタイタネー
ト(BaTiO3 )やストロンチウムタイタネート(S
rTiO3 )の比誘電率はそれぞれ約100および20
0であり、その場合、容量は8.8×10- 4 および
1.78×10- 4 ファラッドである。ところで一般に
ICメモリなどでは消費電流量は現状の4,000ゲー
トのメモリ回路では0.3〜1μA程度である。いま比
誘電率を200として、1.78×10- 4 ファラッド
の容量のコンデンサを10Vで充電し、0.3μAの電
流を消費するICメモリの使用時間、t、は 1.78×10- 4 ×10=0.3×10- 6 ×t より t=6000(sec) となり、約100分メモリ保持が可能となる。しかも本
実施例では電源端子に再度直流電源を接続することによ
り、容量に充電され、再使用が可能である。
FIG. 2 shows the relationship between the dielectric constant and the capacitance of a capacitor having an area of 1 cm 2 and a thickness of 10A. Barium titanate (BaTiO 3 ) and strontium titanate (S
The relative permittivity of rTiO 3 is about 100 and 20 respectively.
0, in which case the capacity is 8.8 × 10 - 4 and 1.78 × 10 - a 4 Farad. By the way, generally, the current consumption of an IC memory or the like is about 0.3 to 1 .mu.A in the current 4,000 gate memory circuit. Now dielectric constant as 200, 1.78 × 10 - 4 was charged at 10V capacitor capacity of Farad, time use of IC memory that consumes a current of 0.3 .mu.A, t, is 1.78 × 10 - 4 × 10 = 0.3 × 10 - 6 × t from t = 6000 (sec), and the it is possible to approximately 100 minutes memory retention. Moreover, in this embodiment, the capacity is charged and the battery can be reused by reconnecting the DC power supply to the power supply terminal.

【0013】このような蓄電機能を付加したICメモリ
やICカードは比較的短時間ではあるが、電池なしにデ
ータを保存できる。たとえばICメモリやICカードに
機密を保持しながら、速やかに情報を移することが可能
となる。しかもこの場合は保持時間を越えるとデータが
自動的に消去されるため、さらに情報の漏洩を防ぐこと
ができる。
An IC memory or IC card having such a storage function can store data without a battery for a relatively short time. For example, it becomes possible to quickly transfer information while maintaining confidentiality in an IC memory or IC card. Moreover, in this case, since the data is automatically erased when the holding time is exceeded, it is possible to further prevent information leakage.

【0014】また本実施例の装置は記憶回路と蓄電素子
を同一基板上に形成することができる。したがって製造
工程は長くなるが、個別に形成した場合と比較し、チッ
プホルダ上に実装する工程は短くなり、信頼性は向上す
る。
In the device of this embodiment, the memory circuit and the storage element can be formed on the same substrate. Therefore, although the manufacturing process becomes long, the process of mounting on the chip holder becomes shorter and the reliability is improved as compared with the case of individually forming.

【0015】さらに本装置には電池による電源のサポー
トをしないため、電池等の有害廃棄物の処理の問題も考
慮する必要がない。
Further, since this apparatus does not support the power supply by the battery, it is not necessary to consider the problem of treating hazardous waste such as the battery.

【0016】実施例ではメモリカードを用いて、本発明
を説明したが、シリコン基板を用いたセンサー素子や演
算回路を備えた装置に適応してもよいことは明らかであ
る。
Although the present invention has been described by using the memory card in the embodiments, it is obvious that the present invention may be applied to an apparatus having a sensor element and an arithmetic circuit using a silicon substrate.

【0017】[0017]

【発明の効果】以上説明したように、この発明によれば
電源の装着や持ち運びがなく、また電池の廃棄問題を考
慮する必要がない。特に野外で用いるようなセンサー素
子の場合、軽量化、装置の使い捨てが可能となりうる。
As described above, according to the present invention, there is no need to mount or carry a power source, and it is not necessary to consider the problem of battery disposal. Particularly in the case of a sensor element used outdoors, it may be possible to reduce the weight and make the device disposable.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

【図2】面積1cm2 、厚み10Aのキャパシタの誘電
率と容量の関係を示す図である。
FIG. 2 is a diagram showing a relationship between a dielectric constant and a capacitance of a capacitor having an area of 1 cm 2 and a thickness of 10A.

【符号の説明】[Explanation of symbols]

V 電源端子 C コンデンサ D1 ダイオード R 抵抗 M メモリ A 電源回路部 L1、L2 電源ライン V power supply terminal C capacitor D1 diode R resistance M memory A power supply circuit section L1, L2 power supply line

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 同一基板上に演算回路または記憶回路ま
たはセンサー回路と、高誘電体物質よりなる蓄電機能を
もつ素子を有する半導体集積回路。
1. A semiconductor integrated circuit having an arithmetic circuit, a memory circuit, or a sensor circuit on the same substrate and an element having a storage function made of a high dielectric material.
【請求項2】 電池あるいは外部電源を接続して蓄電機
能を有する素子に蓄電し、その後前記電池あるいは外部
電源を取り外して前記回路を使用することを特徴とする
請求項1に記載の半導体集積回路の使用方法。
2. The semiconductor integrated circuit according to claim 1, wherein a battery or an external power supply is connected to store the power in an element having a power storage function, and then the battery or the external power supply is removed to use the circuit. How to use.
JP5145296A 1993-06-17 1993-06-17 Semiconductor integrated circuit and its using method Pending JPH0713661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5145296A JPH0713661A (en) 1993-06-17 1993-06-17 Semiconductor integrated circuit and its using method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5145296A JPH0713661A (en) 1993-06-17 1993-06-17 Semiconductor integrated circuit and its using method

Publications (1)

Publication Number Publication Date
JPH0713661A true JPH0713661A (en) 1995-01-17

Family

ID=15381870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5145296A Pending JPH0713661A (en) 1993-06-17 1993-06-17 Semiconductor integrated circuit and its using method

Country Status (1)

Country Link
JP (1) JPH0713661A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002032685A (en) * 2000-05-11 2002-01-31 Nec Corp Contents rental system
JP2002108717A (en) * 2000-07-27 2002-04-12 Nec Corp Disk system with contents reproduction limiting mechanism, and medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160154A (en) * 1984-01-30 1985-08-21 Nec Kansai Ltd Hybrid integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160154A (en) * 1984-01-30 1985-08-21 Nec Kansai Ltd Hybrid integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002032685A (en) * 2000-05-11 2002-01-31 Nec Corp Contents rental system
JP2002108717A (en) * 2000-07-27 2002-04-12 Nec Corp Disk system with contents reproduction limiting mechanism, and medium

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