JPH07135508A - Atmhec synchronization circuit - Google Patents

Abstract

PURPOSE:To realize the cell synchronization system with distributed sample scrambler used for a cell base ATM interface and to conduct an error correction operation for a full 8-bit syndrome normally required in the same timing. CONSTITUTION:A high-order 2-bit of a HEC code is extracted from the midway of a syndrome generation matrix circuit 1e by providing a bit extract circuit 1f. That is, an extract timing is extracted from a timing in 4-bits before a synchronization pattern detection timing and used for the synchronization operation of a cyclic local PRBS generating circuit 7. A syndrome high-order two-bits descrambled from a transfer bit collation circuit 5 are outputted in a timing coincident with low-order 6-bits of the syndrome from an HEC arithmetic circuit 1. A syndrome combining circuit 11 combines syndromes of full 8-bits and the result is given to an error correction circuit 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATMHEC (Asynchrono) for realizing a cell synchronization system with a distributed sample scrambler used in a cell-based ATM interface.
us TransferMode Header Error Control) Synchronous circuit.

[0002]

2. Description of the Related Art Conventionally, the cell synchronization method of the cell-based ATM interface is CCITT II. 432B-ISDN
The distributed sample scrambler and cell synchronization mechanism are recommended in the User / Network Interface Physical Layer Recommendation. This Recommendation recommends a distributed sample scrambling mechanism and a cell synchronization mechanism. According to this, the cell synchronization is established in the reception side HEC synchronization circuit by using the header error control code (HEC code) added to the fifth byte of the header part of the cell. In the process, the hunting state and the pre-synchronization state are reached depending on the number of cells to be synchronized to reach the synchronization establishment state. In this process, in the hunting state and the pre-synchronization state, the lower 6 bits of the total 8 bits of the HEC code are used to perform the cell synchronization operation. After that, the result that the synchronization state continues for the specified number of times or more is detected, and the synchronization establishment state is entered. All 8 HEC codes in the synchronization established state
Cell synchronization retention, 1-bit error correction of header data, or multiple-bit error detection is performed using bits (FIG. 5). Here, the hunting state is a state in which cell boundaries are searched in a state out of synchronization, and the pre-synchronization state is a state in which it is checked bit by bit whether the header error control coding rule is applied to the assumed header area. Say.

The code synchronization operation between transmission and reception of the distributed sample scrambler is performed in the cyclic local PRBS generation circuit on the reception side. This synchronization establishment operation is performed in parallel with the cell synchronization operation, and is started from the time when the cell synchronization is in the pre-synchronization state. The synchronization establishing operation of the cyclic local PRBS generation circuit is such that when the cell synchronization is in the pre-synchronization state, the upper 2 bits of the HEC code (HEC7, HEC7,
8) and the HEC code upper 2 bits as a result of operation from the received 4 bytes of header data are modulo-added.
As a result, the sender PRBS (Pseudo Random Bit)
Sequence) transmission bits are extracted, and the extracted transmission bits are compared with the sample bits of the receiving-side local PRBS at cell half cycle intervals. The comparison result is the cyclic local P
Apply to the feed-forward tap of the RBS generator. The code synchronization state of the cyclic local PRBS generation circuit is established by the number of application times under the transition management of the synchronization pull-in state, the confirmation state for confirming the number of code matches after pull-in, and the stable state.

Through the above process, after the cell synchronization is in the synchronization established state and the code synchronization of the cyclic PRBS generation circuit is in the stable state, the cell synchronization operation is performed by the upper 2 bits of the descrambled HEC code. All HEC codes including 8 bits are performed. Error detection of 2 bits or more and 1 at the same time
Bit header part error correction is performed, and H of the cell header part is corrected.
The received cell data excluding the EC code is descrambled and sent to the next processing step.

(Description of Cell Synchronous Circuit for Cell-based ATM Interface with Distributed Sample Scrambler)
Conventional distributed sample scrambler cell-based ATM
The interface cell synchronization circuit is shown in FIG.
This will be specifically described with reference to the time chart of. The received cell data (A) is input to a CRC (Cyclic Redundancy Check) operation circuit 1a. The HEC arithmetic circuit 1 receives the serial data stream and generates a multi-formula (X ⁸ + X
² + X + 1) performs input cancellation CRC remainder calculation.
As for the syndrome as the calculation result, 6 bits are output to the syndrome zero detection circuit 2 and 2 bits are output to the transfer bit matching circuit 5 at the timing of FIG. In the syndrome zero detection circuit 2, the lower 6 bits of the syndrome are "0".
When it is detected, it is determined that cell synchronization has been achieved,
The resulting sync signal is sent to the sync management circuit 4 as shown in FIG.
Is output at the timing of. The synchronization management circuit 4 determines whether the cell synchronization state is hunting, pre-synchronization,
It manages which of the following states, and the synchronization establishment state.

When the cell synchronization state becomes the pre-synchronization state, the transmission bit collation circuit 5 is enabled by the output of the synchronization management circuit 4. In the transmission bit matching circuit 5, the transmission side source PRBS transmission bits (U _t-211 and U _t ) extracted by the syndrome generation matrix circuit 1e at the timing of FIG.
_{t + 1} ) and the predicted value (F) (Vt _-211 and Vt _{+ 1} ) of the receiving side local PRBS generated by the cyclic local PRBS generating circuit 7 are modulo 2 added. When the synchronization is not established, a mismatch detection signal between the PRBS transmission bit on the transmitting side and the local PRBS predicted value on the receiving side is obtained as the addition result.
This addition result is used as a cyclic local PRBS for every half cell cycle.
By applying the feedback tap of the generation circuit 7 a prescribed number of times, the source PRBS on the transmission side and the local PRB on the reception side
S can be synchronized. Source PR in the synchronization state
The code phases of the BS and the local PRBS on the receiving side are shown in FIG.
And (F). Further, the transmission bit collating circuit 5 receives the local PRBS on the receiving side at the timing shown in FIG.
(V _t-211 and V _{t + 1} ) are extracted, and the upper 2 bits of the syndrome in the cell synchronization established state (corresponding to HEC7 and HEC8)
Descramble.

[0007]

However, the top two syndromes descrambled at the timing shown in FIG. 4 (E).
The decision timing of the bit syndrome is shown in FIG. 4 (G), which is deviated from the 6-bit syndrome coincidence detection timing of the timing shown in FIG. 4 (D). Therefore, all 8-bit syndrome coincidence detection cannot be performed. Therefore, the error correction operation that requires all 8-bit syndrome at the same timing cannot be normally performed. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an ATMHEC synchronization circuit that can normally perform an error correction operation.

[0008]

In order to solve the above-mentioned problems, in the ATMHEC synchronizing circuit according to claim 1, the HEC
An HEC operation circuit that performs a CRC operation on a header length of 40 bits for each bit of received cell data for detecting synchronization, and the lower 6 bits of the operation result are verified to verify whether the syndrome is "0". Syndrome zero detection circuit, a synchronization management circuit for monitoring the cell synchronization state, and a cell time slot (cell T synchronized with the verification result).
Cell TS generating circuit for generating S), a timing generating circuit for generating timing for extracting a transmission bit, and a transmission bit for comparing the source side PRBS transmission bit with the reception side local PRBS prediction value to detect a mismatch. A matching circuit, a cyclic local PRBS generation circuit for generating a reception side local PRBS for descramble the scrambled reception cell data, and a phase of the output code of the cyclic descramble circuit and the reception cell data Phase adjustment circuit and cyclic local PRB
Local PRB for monitoring the synchronization state of the S generation circuit
S state management circuit (confidence counter), error correction circuit for displaying 1-bit error correction and 2 or more-bit error detection of cell header part, descrambling circuit for descrambling received cell data, and reception syndrome And a syndrome delay circuit for adjusting the output timing of the error correction circuit and the operation timing of the error correction circuit, and a syndrome combining circuit for combining the descrambled upper 2 bits of the syndrome with the lower 6 bits of the syndrome.

Further, the ATMHEC synchronizing circuit according to the second aspect does not include the syndrome delay circuit for adjusting the output of the receiving syndrome and the operation timing of the error correction circuit according to the first aspect. Instead, HEC
A bit extraction circuit that extracts the upper 2 bits of the HEC code from the matrix that performs the CRC calculation on the header length of 40 bits for each 1 bit of the received cell data for detecting synchronization, and all 8 bits or the lower 6 bits of the calculation result And a syndrome combination circuit that outputs the result to the syndrome zero detection circuit.

[0010]

According to the ATMHEC synchronizing circuit thus constructed, all 8-bit syndromes have the same timing, and the error correcting operation can be normally performed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of the first embodiment, and FIG. 4 is a time chart of each point in the block diagram.
The HEC arithmetic circuit 1 uses the generation polynomial formula (X ⁸ + X ² + X +
In 1), a CRC calculation circuit (X ⁸ + X ² + X + 1 remainder calculation circuit) 1a for performing input cancellation CRC remainder calculation, a 32-bit delay circuit 1b, an input data reproduction circuit 1c, an 8-bit delay circuit 1d, and 40 bits before The matrix circuit 1e is provided for canceling the input data, newly inputting 1 bit, and generating the syndrome of the CRC calculation result every 1 clock. The HEC operation circuit 1 receives the serial data stream and outputs the syndrome generated as the HEC operation result for the input data stream to the next stage.

(HEC Synchronous Operation) In the HEC synchronous operation, the syndrome zero detection circuit 2 detects whether the syndrome output from the HEC arithmetic circuit 1 becomes zero (divided) (synchronous pattern detection), and detects zero. It is determined that synchronization has been achieved at that point. Once it is determined that the synchronization has been achieved, it is assumed that the cell synchronization state in the synchronization management circuit 4 for managing the synchronization state has changed from the hunting state to the previous synchronization state. In the pre-synchronization state, the cell TS generation circuit 3 that generates one cell length (424 bits) is activated from the time when the syndrome zero is first detected in the hunting state, and the counting result is given to the synchronization management circuit 4. In the synchronization management circuit 4, the syndrome zero detection circuit 2
It is verified from the output result of 1) and the cell TS generation circuit whether zero can be detected again at the signal position one cell length after the position where zero was detected previously. When β zero syndrome zero is detected continuously in one cell interval, the synchronization state is managed as a transition from the previous synchronization state to the synchronization establishment state. On the contrary, if the syndrome zero is not detected continuously at 1 cell intervals from the synchronization established state, the synchronization management circuit 4 returns the synchronization state to the hunting state as a loss of synchronization.

The cell synchronization establishment operation differs depending on the synchronization state of the cyclic local PRBS generation circuit 7 described below. When the synchronization state of cyclic local PRBS generation circuit 7 is other than the synchronization stable state, the synchronization establishment operation is performed with the lower 6 bits of all 8 bits of the HEC code. In the synchronization stable state, the synchronization establishment operation is performed with all 8 bits. Switching between 6 bits and 8 bits is performed by the local PRBS state management circuit 8
Is performed by the syndrome combination circuit 11.

(Synchronous Operation of Cyclic Local PRBS Generating Circuit 7) When the HEC synchronization state becomes the pre-synchronization state or later, the upper 2 bits (7, 8 bits) of the HEC code are received from the received HEC code by the HEC arithmetic circuit 1. To be extracted. 8 and 7 bits of the extracted HEC code are the source P of the transmission side
It is scrambled with RBS Ut _-211 and _{Ut + 1} .
The cyclic operation of the cyclic local PRBS generation circuit 7 is performed by transmitting transmission source PRBS transmission sample bits (U _t-211 and U _{t + 1} ), and receiving local PRBS transmission sample bits predicted values (V _t-211 and V _{t). t + 1} ) and modulo addition,
It is connected to the transfer bit matching circuit 5 for comparison and matching. By applying the addition result of the transfer bit collating circuit 5 to the feedforward tap of the cyclic local PRBS generating circuit 7 at the timing of the half cell cycle generated from the cell counter value in the cell synchronization timing generating circuit 6, Be seen.

The synchronous state of the cyclic local PRBS generating circuit 7 is managed by the local PRBS state managing circuit 8 according to the number of times the addition result from the transfer bit collating circuit 5 is applied. Apply the matching result of the source PRBS transmission sample bit of the transmission side and the local PRBS transmission sample bit of the reception side for 31 bits of transmission sample bit without error in 6 bits of HEC to the feedforward tap of the cyclic local PRBS generation circuit 7. After that, the cyclic local PRBS generation circuit 7 is managed as having transited to the synchronization verification state. In the synchronization verification state, the transmission source PRBS transmission sample bits and the reception local PRBS transmission sample bits have the same predicted value consecutively for verification. In this state, the transmission sample bit of the source PRBS on the transmitting side and the predicted value of the cyclic local PRBS generating circuit 7 already match, so the generated code string of the cyclic local PRBS generating circuit 7 changes the signal string depending on the collation result. Not done.

In the verification state, the transmission source source PRBS transmission sample bits and the reception local PRBS are transmitted 16 times in succession.
When a match of the transmission sample bits is detected, the cyclic local PRBS generation circuit 7 transits to the stable synchronization state. When the cyclic local PRBS generation circuit 7 enters a stable synchronization state, the upper 2 bits of the HEC code (HEC8, HEC7)
Is descrambled by the receiving side local PRBS synchronized with the transmitting side source PRBS in the transfer bit matching circuit 5. Further, the upper 2 bits of the HEC code are combined with the lower 6 bits of the HEC code by the syndrome combination circuit 11 to be used as an 8-bit HEC code in the error correction circuit 9 that performs error detection and 1-bit error correction of 2 bits or more of the header. .

However, as shown in FIGS. 4D and 4E, the HEC lower 6 bits output timing (synchronization establishment timing) from the syndrome matrix and the upper 2 bits syndrome determination timing position are shifted by 4 bytes. As a result, the problem that syndrome combination is not performed normally occurs. In order to solve this, the syndrome delay circuit 10 delays the upper 6 bits of the HEC code by 4 bytes, and the syndrome combining circuit 11 inputs the timing of all 8 bits of the HEC code to the error correction circuit 9 and inputs them to the HEC code.
In the synchronization stable state, error correction is performed using all 8 bits of the HEC code.

Since the cyclic local PRBS generation circuit 7 descrambles the received cell data in the stable synchronization state, the source P on the transmission side caused by passing through the error correction circuit 9 or the like.
Correct the code positions of the RBS and the receiving local PRBS. Therefore, the phase adjustment delay circuit 12 is connected to the output of the cyclic local PRBS generation circuit 7. The received cell data output from the error correction circuit 9 includes a descramble circuit 13 for descramble the scrambled received cell data. The received cell data descrambled here is output to the next stage as output data of the ATMHEC synchronizing circuit.

[Second Embodiment] FIG. 2 is a block diagram of the second embodiment. In the first embodiment, H is calculated from the HEC calculation result syndrome at the 6-bit synchronization pattern detection timing.
The circuit is realized by a method of extracting the upper 2 bits (7, 8 bits) of the EC code. In the second embodiment, by providing the bit extraction circuit 1f, the upper 2 bits of the HEC code are extracted from the middle of the syndrome generation matrix circuit 1e. That is, the extraction operation is performed 4 bits before the synchronization pattern detection timing, and the synchronous operation of the cyclic local PRBS generating circuit 7 is performed. After the cyclic local PRBS generating circuit 7 is in a stable synchronization state, the transfer bit collating circuit 5 descrambles the upper 2 bits (HEC8, 7) extracted and a syndrome zero detection circuit for detecting cell synchronization. 2 and error correction circuit 9.

In the first embodiment, the lower 6 bits of the syndrome from the HEC arithmetic circuit 1 are adjusted in timing by the syndrome delay circuit 10 and then combined with the upper 2 bits of the descrambled syndrome from the transfer bit collating circuit. Then, a syndrome of all 8 bits was constructed and output to the error correction circuit 9. On the other hand, in the second embodiment, the descrambled high-order 2 bits of the syndrome are output from the transmitted-bit collation circuit 5 at the same timing as the low-order 6 bits of the syndrome from the HEC operation circuit 1. Therefore, the syndrome delay circuit 10 required in the first embodiment is unnecessary. All 8-bit syndromes are combined by the syndrome combination circuit 11 and input to the error correction circuit 9.

[0021]

As described above, the ATMHE of the present invention
According to claim 1 of the C synchronization circuit, the syndrome delay circuit 10 for adjusting the output of the reception syndrome and the operation timing of the error correction circuit 9, and the descrambled upper 2 bits of the syndrome are combined with the lower 6 bits of the syndrome. The syndrome combination circuit 11 is provided. Further, according to claim 2, the bit extraction circuit 1f for extracting the upper 2 bits of the HEC code from the matrix for performing the CRC operation and all 8 bits or the lower 6 bits of the operation result are switched and verified to obtain the syndrome zero. The syndrome coupling circuit 11 for outputting to the detection circuit 2 is provided. for that reason,
An error correction operation that requires all 8-bit syndromes at the same timing can be performed normally.

[Brief description of drawings]

FIG. 1 shows a configuration diagram of a first embodiment of the present invention.

FIG. 2 shows a block diagram of a second embodiment of the present invention.

FIG. 3 shows a configuration diagram of a conventional example.

FIG. 4 shows a time chart of each point in the configuration diagram.

FIG. 5 shows a cell synchronization probability state transition diagram.

[Explanation of symbols]

1 ... HEC arithmetic circuit, 2 ... Syndrome zero detection circuit, 3
... cell TS generation circuit, 4 ... synchronization management circuit, 5 ... transmission bit collation circuit, 6 ... timing generation circuit, 7 ... cyclic local PRBS generation circuit, 8 ... local PRBS state management circuit, 9 ... error correction circuit, 10 ... Syndrome delay circuit, 11 ... Syndrome combination circuit, 12 ... Phase adjustment circuit, 13 ... Descramble circuit, 1f ... Bit extraction circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H04L 29/02 H04Q 3/00 (72) Inventor Shinichi Aoyagi 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. An HEC operation circuit (1) for performing a CRC operation on received cell data (A) for detecting HEC synchronization and a lower 6 of an operation result (B) of the HEC operation circuit.
A syndrome zero detection circuit (2) for verifying the bit to verify whether the syndrome is "0", and a synchronization management circuit (4) for monitoring the cell synchronization state using the verification result of the syndrome zero detection circuit. And a cell TS generation circuit (3) for generating a cell time slot synchronized with the verification result,
Timing generation circuit (6) for generating the timing (C) of extracting the transmission source PRBS transmission bit in the cell
And the transmission source PRBS transmission bit and the reception local PRB at the timing generated by the timing generation circuit.
A transmission bit collating circuit (5) that compares the S prediction values to detect a mismatch, and a receiving side local PRBS (for descrambling the scrambled reception cell data by performing a synchronous operation with the mismatch signal of the transmission bit matching circuit). F) generating a cyclic local PRBS generating circuit (7), and a local PRBS state for monitoring the synchronous status of the cyclic local PRBS generating circuit by combining the mismatch signal of the transfer bit collating circuit and the verification signal of the syndrome "0". The output of the management circuit (8), the error correction circuit (9) for displaying the 1-bit error correction or the error detection of 2 bits or more of the cell header part of the received cell data reproduced by the HEC operation circuit, and the error correction circuit output A descramble circuit (13) for descramble received cell data, and the receiving side local PR
A phase adjustment circuit (12) for matching the phase of the BS with the phase of the received cell data output from the error correction circuit,
Combined with the syndrome delay circuit (10) for adjusting the timing of the output of the reception syndrome from the HEC arithmetic circuit, the descrambled upper 2 bits of the descrambling syndrome which is the output of the transfer bit matching circuit, and the lower 6 bits of the syndrome whose timing is adjusted. And an ATMHEC synchronization circuit including a syndrome coupling circuit (11). 2. An HEC operation circuit (1) for performing a CRC operation on received cell data (A) for detecting HEC synchronization, and a lower 6 of an operation result (B) of the HEC operation circuit.
A syndrome zero detection circuit (2) for verifying the bit to verify whether the syndrome is "0", and a synchronization management circuit (4) for monitoring the cell synchronization state using the verification result of the syndrome zero detection circuit. And a cell TS generation circuit (3) for generating a cell time slot synchronized with the verification result,
Timing generation circuit (6) for generating the timing (C) of extracting the transmission source PRBS transmission bit in the cell
And the transmission source PRBS transmission bit and the reception local PRB at the timing generated by the timing generation circuit.
A transmission bit collating circuit (5) that compares the S prediction values to detect a mismatch, and a receiving side local PRBS (for descrambling the scrambled reception cell data by performing a synchronous operation with the mismatch signal of the transmission bit matching circuit). F) generating a cyclic local PRBS generating circuit (7), and a local PRBS state for monitoring the synchronous status of the cyclic local PRBS generating circuit by combining the mismatch signal of the transfer bit collating circuit and the verification signal of the syndrome "0". Output from the management circuit (8), the error correction circuit (9) for displaying the 1-bit error correction or the error detection of 2 bits or more of the cell header part of the received cell data reproduced by the HEC operation circuit, and the error correction circuit. A descramble circuit (13) for descramble received cell data, and the receiving side local P
Phase adjusting circuit (12) for matching the phase of the RBS with the phase of the received cell data output from the error correction circuit
And a bit extraction circuit (1f) for extracting the upper 2 bits of the HEC code from the matrix for performing the CRC operation of the HEC operation circuit, and all 8 bits or the lower 6 bits of the operation result are switched and verified to change the syndrome. An ATMHEC synchronization circuit having a syndrome coupling circuit (11) for outputting to a zero detection circuit.